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Antti wrote: > > actually yes. I have just looked at Xilinx website online shop and > all distributors > > there is ABSOLUTLY no deliver information for ANY spartan-3A or 3AN > device yet. And S3A is not new anymore. Even S3AN is out for some > time, still NO BUYING options, nothing nothing nothing. Xilinx has > really mis-understood the meaning of "online shop"... My FAE, who is a good chap, assures me that the S3A is just about there - approx 6 weeks before the parts I am interested in get into distribution. No doubt Steve, who is also a good chap, will jump in with the authoritative picture.Article: 120276
Looking at the Xilinx website, it does look like partitions are the replacement for modular design flow. I was wondering why the modular design flow chapter was missing in the 9.1 docs. I was having to use the 8.1 docs. Unfortunately the documentation for parititions appears to be worse than for modular design flow! I see some references to partitions in the tcl chapter, but that is about it. I see nothing showing how I would use it with area_groups or the floorplanner. On Jun 4, 4:01 pm, Sean Durkin <news_ju...@durkin.de> wrote: > javaguy11...@gmail.com wrote: > > The device is aSpartan3. > > The project was previously synthesized without using modular design > > and there is nothing mentioned in that log about problems withTBUF's. > > I think during a normal synthesis run, TBUFs are automatically replaced > by logic. I know that at least in Virtex4, there are no internal > tristates, so if you describe tristate busses, the tools don't complain > but just replace them with logic. > > But if you do the modular design flow, the TBUFs become sort of > "external ports" that can't be changed automatically, so the synthesis > tool tries to keep the TBUFs, and ngdbuild/map stop later because there > aren't any in that architecture. > > I don't think the "-iobuf"-option will help in that case, since it turns > on/off automatic insertion of IO buffers by the tools, but it will not > change/remove buffers that you have instantiated manually. > > I guess the only thing you can do is have two seperate signals for the > two directions and one direction signal as module ports, instead of the > tristate-line. Not sure how you would properly constrain the localtion > of the module crossings in that case, though. > > BTW, I thought the whole modular is deprectaed since ISE8/9, and now > there is only "partitions"? Haven't tried that out yet, but maybe you > should have a look. > > -- > My email address is only valid until the end of the month. > Try figuring out what the address is going to be after that...Article: 120277
On Jun 4, 8:30 pm, emu <e...@ecubics.com> wrote: > On May 30, 10:28 am, mozilla <godzilla...@gmail.com> wrote: > > > Hi, > > > I recently got anexys-1000 board for a project i'm working on and > > would like to put a xilinx EDK design on the board, however Digilent > > don't provide a .xbd (board description file) for this board. Rather > > than re-invent the wheel i was wondering if anyone out there had found > > one or had already compiled one? > > > Any help would be greatly appreciated. > > I guess, 13 answers later you still didn't get the .xbd file, right ? Indeed it's proving very hard to track down, i even asked someone on the inside at xilinx and digilent if they had one and still came up blank.Article: 120278
Tim, Unfortunately, Steve Knapp has left Xilinx to pursue an opportunity that intrigued him. We will miss him. As far as I am aware, the Spartan 3A, 3AN rollout is proceeding just fine. There are ES available now, with production coming very soon. Distributors will not stock ES, as they can not return it. Peter and I have made some suggestions (like accepting unsold ES back from distributors), but I don't know how far that goes (what may work for LX330T ES, may not work for 3S400A). In any event, we are still trying to work on the "store." As always, if anyone has an issue with getting parts, Peter and I will intervene and try to find out what the problem is. If you are willing to place an order, the distributor will order from us (immediately), and your parts will be on their way. The only case where they may not be on their way is if you have ordered production parts, and that part is not in production yet, or you have ordered some package/part/RoHS combination that needs to be assembled (because no one is ordering it). Be very careful about leaded, vs "un-leaded" (RoHS), as we can not ship any non-RoHS to the EU any longer (the fences are up!). AustinArticle: 120279
Hi, I'm trying to install system generator on MATLAB R2007a. I can't get pass the license agreement as the wizard keep on prompting me for not being able to detect matlab. The message suggests also modifying the environment variables which I did but nothing happened. So basically, has anybody had luck installing SysGen on MATLAB R2007a, or it only works on R2006a/b. The thing is that I don't have access to the previous version and I would like to use SysGen 9x instead of 8. Any help would be greatly appreciated. Thanks, MannyArticle: 120280
John_H wrote: > "Barry Brown" <b0_nws2@agilent.com> wrote in message > news:1180971829.270177@newsreg.cos.agilent.com... >> But can the BRAM FIFO be made to work with back-to-back reads? Since the >> BRAM registers the address, it won't work if you just increment the read >> address pointer when read enable is true - the output data is a clock >> behind the read address pointer, so you need an idle clock cycle between >> each read. >> Barry Brown > > If the read address changes combinatorially with the read enable, the clock > edge will provide the data for the next address in the back-to-back reads > for the BlockRAM. No problem. Hmm... that is an interesting approach I had not thought of. I did not carefully read through your longer discussion, and missed that point. I'll definitely have to consider that in future things, thanks.Article: 120281
OOPS! As usual, I was a bit too low key: "The Spartan-3A family is now released to production two months ahead of schedule. The entire family is shipping on all speed grades, all temperature grades, and all part and package types! We have production volumes on the shelf now with over XXX,XXX units in the pipe today. Lead times are short and order entry is open." Also, of some interest: "Not only was the power reduced on the Spartan-3A family but we were also able to reduce the power numbers across the entire Spartan-3 Generation. In both Spartan-3 and Spartan-3E we have made reductions across the devices that are as much as 50% improvement in our power numbers. On the Spartan-3E platform, the changes have been made to the data sheet already. By mid-May, you will see the changes made to the Spartan-3 data sheet." Enjoy, AustinArticle: 120282
Are you doing this in Verilog or VHDL? Can you post your code (or the important part with the clock) so we can see what's going on? Is 'myclk' input to a clock pad or just a regular I/O?Article: 120283
austin wrote: > OOPS! > > As usual, I was a bit too low key: > > "The Spartan-3A family is now released to production two months ahead of > schedule. The entire family is shipping on all speed grades, all > temperature grades, and all part and package types! We have production > volumes on the shelf now with over XXX,XXX units in the pipe today. Lead > times are short and order entry is open." > > Also, of some interest: > > "Not only was the power reduced on the Spartan-3A family but we were > also able to reduce the power numbers across the entire Spartan-3 > Generation. In both Spartan-3 and Spartan-3E we have made reductions > across the devices that are as much as 50% improvement in our power > numbers. On the Spartan-3E platform, the changes have been made to the > data sheet already. By mid-May, you will see the changes made to the > Spartan-3 data sheet." That power note is a little unclear. Is it a decrease in the MAX column, from better testing data [so no change in typicals], or is it a process change, that has resulted in both MAX, and TYP values decreasing. Also, how does such a change affect the precision of mA/MHz power-models ? -jgArticle: 120284
Jim, Basically, the entire Spartan 90nm process node has benefited from UMC getting to the point where we are in really good shape on leakage. As you know, speed and leakage are not something that can be separated easily. Make it fast, it gets leaky. Make it slow, it gets less leaky. Through a lot of just plain old hard work, the process is so stable (and varies so little), and predictable, that we can specify a much lower static power level. When you are a large enough company to interest your fab in meeting your needs, well, very good things happen as a result. If you are too tiny, and not able to command the fab's attention, well, then you "gets what you gets." Basically, whatever comes out of the fab, you either pay for it, or scrap it. Today at DAC, I heard nothing but good stories about UMC - about how good they are. Yes, UMC is part of Xilinx' success. We could not have done it without them. But, Toshiba is also now part of that success, too. We are careful to approach those fabrication facilities that have the best possible reputation, where being a supplier to Xilinx is something they are actively involved in, consciously working on every day. So, just when our competition announces their "super low" static power numbers, we also drop our specification to make their announcement unimportant. Magic? No, just good old hard work. I feel sorry for the other FPGA vendors: they have no ability whatsoever to get anything from their fab partner, other than whatever their partner is presently making money from. So, if cell phones are the big money maker, you can have a cell phone process. If microprocessors are the product, you get a microprocessor process. That works for a cell phone company, or a microprocessor company, but it is really tough on a FPGA company. One year, one month, and counting. AustinArticle: 120285
Totally_Lost wrote: > I've been looking at the various core/macro generators and they all > seem horribly large and slow, almost like student designs. Has anyone > seriously taken a good look at hand fitting multipliers and squarers > into Altera/Xilinx FPGA's? > If you haven't already, you might look at the multiplication in FPGAs page on my website at http://www.andraka.com/multipli.htm. The partial product LUT multipliers are about as efficient as you are going to get with the FPGA LUT structure. If you can use multiple cycles, then you can combine that with sequential multiplication to make the multiplier smaller at the expense of more clock cycles per product.Article: 120286
austin wrote: > Jim, > > Basically, the entire Spartan 90nm process node has benefited from UMC > getting to the point where we are in really good shape on leakage. > > As you know, speed and leakage are not something that can be separated > easily. Make it fast, it gets leaky. Make it slow, it gets less leaky. > > Through a lot of just plain old hard work, the process is so stable (and > varies so little), and predictable, that we can specify a much lower > static power level. > > When you are a large enough company to interest your fab in meeting your > needs, well, very good things happen as a result. > > If you are too tiny, and not able to command the fab's attention, well, > then you "gets what you gets." Basically, whatever comes out of the > fab, you either pay for it, or scrap it. > > Today at DAC, I heard nothing but good stories about UMC - about how > good they are. Yes, UMC is part of Xilinx' success. We could not have > done it without them. But, Toshiba is also now part of that success, > too. We are careful to approach those fabrication facilities that have > the best possible reputation, where being a supplier to Xilinx is > something they are actively involved in, consciously working on every day. > > So, just when our competition announces their "super low" static power > numbers, we also drop our specification to make their announcement > unimportant. Magic? No, just good old hard work. > > I feel sorry for the other FPGA vendors: they have no ability > whatsoever to get anything from their fab partner, other than whatever > their partner is presently making money from. So, if cell phones are > the big money maker, you can have a cell phone process. > > If microprocessors are the product, you get a microprocessor process. > > That works for a cell phone company, or a microprocessor company, but it > is really tough on a FPGA company. > > One year, one month, and counting. Thanks Austin, but in all the above, you seem to have overlooked answering my questions :) -ie have UMC changed the process since you started, ( which means newer silicon is measurably different from older silicon ) ? or did you start with more spec-headroom on MAX values (as one does, on any new process), but the process itself has not actually changed, and thus the typicals are also unchanged, but the better experience allows the MAX to be decreased ? MAX can also be decreased with some marketing push, where some yield rejects are allowed, to hit soms magic number. Doing this brings the TYPs up closer to MAX. Is this change ["as much as 50% improvement"] purely static Icc, or does it impact mA/MHz ? -jgArticle: 120287
Hi, I=B4m new to card using Xilinx chips. I=B4m developping a new vhd
prgogram, and on one Mesa example, at the very beginning of the code,
the following statements appear:
entity main is
port
(
-- bus interface signals --
LW_R: in std_logic;
DEN: in std_logic;
ADS: in std_logic;
BLAST: in std_logic;
WAITO: in std_logic;
READY: out std_logic;
INT: out std_logic;
HOLD: in std_logic;
HOLDA: inout std_logic;
RESET: in std_logic;
DISABLECONF: out std_logic;
DREQ: in std_logic;
DACK: in std_logic;
CCS: out std_logic;
INIT: out std_logic;
LAD: inout std_logic_vector (31 downto 0); -- data/address bus
lBE: in std_logic_vector (3 downto 0); -- byte enables
CHANDATA: inout std_logic_vector (31 downto 0);
RXEN: out std_logic_vector (15 downto 0);
TXEN: out std_logic_vector (15 downto 0);
LCLK: in std_logic;
-- led bits
LEDS: out std_logic_vector(7 downto 0)
);
end main;
CHANDATA refears to the I/O card signals, but I woul like to know what
are the others signals for. Are they internal signals, and no need of
manipulation is requiered?
thanks in advance,
Martin
Article: 120288Jim Granville, I thought I was clear. Sorry. No change to the process. Just tighter, cleaner, process controls. As you may be aware, as dimensions shrink, it becomes increasingly difficult to control variation. Even on a single wafer, one can experience 6 sigma variation (+/- 3). In effect, all possible process corners may happen on the same wafer, sometimes on the same die. It is only after tens of millions of shipped Spartan 3 family die that the process becomes well enough known that we are able to take advantage of it, and not lose yield by a tightening of the specifications. AustinArticle: 120289
austin wrote: > Jim Granville, > > I thought I was clear. Sorry. > > No change to the process. Just tighter, cleaner, process controls. > > As you may be aware, as dimensions shrink, it becomes increasingly > difficult to control variation. Even on a single wafer, one can > experience 6 sigma variation (+/- 3). In effect, all possible process > corners may happen on the same wafer, sometimes on the same die. > > It is only after tens of millions of shipped Spartan 3 family die that > the process becomes well enough known that we are able to take advantage > of it, and not lose yield by a tightening of the specifications. Hi Austin So that means the MAX column has come down, but the TYP column has not changed ? What about the mA/MHz values ? - Tho I'd imagine they are rather less process dependant than leakage values -jgArticle: 120290
Thank you!
Will Quartus-II 8.0 support unnamed-block variable-declarations?
(The example below causes syntax-error in Quartus-II 7.1 April 2007.)
always_comb begin
for ( int i = 0; i < 256; ++i )
my_array[i] = in_a[i] + in_b[i];
end
"Subroto Datta" <sdatta@altera.com> wrote in message
news:1180985053.020785.303430@a26g2000pre.googlegroups.com...
> On May 27, 10:12 pm, "Xilinx user" <xilinx_u...@nowhere.net> wrote:
>> DoesQuartus-II 7.1 support theSystemverilogpreprocessor's ``
>> concatenator?
>>
>> `define pori_reg(r) \
>> r <= def_``r
>> ...
>
> No, Quartus II does not support any of the `define extensions defined
> by the SystemVerilog language. These include `", `\`", and ``. These
> features will be added to Quartus II 8.0.
>
> - Subroto Datta
> Altera Corp.
>
>
Article: 120291
On Mon, 4 Jun 2007 09:08:53 -0700, jacky <jr3002@wanadoo.fr> wrote:
>Hi does anyone already made a tcl command to write down any signals from
> the wave into a CSV file (excel compatible) thanks for your help
It's rather easy to write a single CSV record in Tcl:
# First argument $file is a Tcl file handle
# obtained from the [open] command. Second argument $arglist
# is a Tcl list of the items in the comma-separated record.
#
proc writeCSVrecord {file arglist} {
puts $file [join $arglist ,]
}
And you can quite easily combine that with the [examine] command:
# Second argument $signals is a list of signal names
# to include in the CSV record
proc writeCSVsignals {file signals} {
set values [list]
foreach sig $signals {
lappend values [examine $sig]
# or ... lappend values $sig [examine $sig]
# if you also want the signal name in the file
}
writeCSVrecord $file $values
}
Now it's simply necessary to open a file for output, call procedure
[writeCSVsignals] as many times as required, and finally close
the file.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 120292many thanks Jonatham have a great dayArticle: 120293
Patrick Dubois wrote: > On 4 juin, 10:22, Tim <tmorl...@gmail.com> wrote: >> In edif flow, xst is not used as synthesis tool. A third party synthesis tool, >> like Synplify Pro, generates an edif, which is passed to the xilinx ngdbuild, >> map and par tools. >> For the xilinx tools to know which partitions are defined and which partions >> have been changed, the third party synthesis tool has to write writes this >> information into the edif file. So both the third party synthesis tool and >> xilinx tools agree on where this information is found in the edif. >> That is what my question is about, where can I find documentation on what >> exactly is written in the edif file, for what concerns partitions. >> >> In addition, I have read somewhere that Synplify Pro also generates a tcl file >> with some info regarding partitions, but again with no details. > > Yes, I understand that Synplify generates the edif. My point is that > in order for the ngdbuild, map and par tools to know about partitions, > the design must be implemented using the ISE environnement (no need to > use xst after all, my mistake). > The only place where you can specify what part of the design is a > partition, is within the ISE flow. > Basically you can't just feed your edif to ngdbuild, it won't > recognize the partitions. Ok, this is new for me. > >>From AR 24870: > "When ISE parses the EDIF file, it will create the relative Partition > for each tagged hierarchical node." > Only ISE can create partitions which will be understood by ngdbuild. > > I just found this article, it seems to explain everything we need to > know about partitions+Synplify. > http://syndicated.synplicity.com/Q107/xilinx.html This was also my source. It's a bit strange although that xilinx does not include this information into their documentation. > > If you want to stay all command-line, you need to use the new tcl > interface to run the Xilinx tools (you can't run them directly to use > partitions). See chapter 3 of the Development System Reference Guide. > I will give the tcl interface a try then, Thanks > Good luck. >Article: 120294
> As always, if anyone has an issue with getting parts, Peter and I will > intervene and try to find out what the problem is. Well, I designed a board 2 years ago to use V4FX40 parts. Is there any sign of them yet? Lol JonArticle: 120295
Hi friends, I am new to this forum and found that you guys are really helpful to each other with strong knowledge on FPGAs. So I thought to get your help. So I would really appreciate you guys if you can help me. I am a undergraduate student in electronic and computer engineering and going to start my BS final project in next fall semester. I need your help to find an interesting, new project topic that have some thing new or contribution, I like to share my final effort in the web (in places like Opencores.org as OpenHW project/contribution) My abilities and interest is : I have fully familiar with Verilog HDL and it's advanced topics like PLI and FSM Design, but have a little practical experience. I have familiar with FPGA design flow an related Simulation and Synthesis tool (Modelsim, VCS, ISE ) and there are FPGA board in my university that I can use it. I like to use SystemC in my project and extend my knowledge to system level descriptions. So I think that SoC design would be good but I don't know which topic in this area fit to my interest, so looking for some interesting project ideas or contribution idea. I have some knowledge about graphic processors (GPU) and wrote several articles about new GPUs architecture like R600 (GPU on the ATI Radeon HD 2900XT Graphic card). Also I have some Knowledge about pipelined processor and Datapath- Control Design. My Verilog HDL Class project was describe/validate a programmer Timer approximately like Intel 8254 and I am familiar with synchronous design. I am undergraduate student and I don't want to do big project that eat all of my project time to design process and waste documentation and verification process time. So for these reason I want to select a smallish project something that I can implement in about 50% of my available time and then spend the other 50% on trying to answer/ implement/study some of the above issues. I am looking for experienced individuals of the FPGA development community that would be willing to aid me as mentors or technical advisors. my project is strictly academic and unfortunately the only thing that I can offer for any assistance is my gratitude. I would appreciate any suggestions, at the least they would give me a direction to think in. ThanksArticle: 120296
Hello, I am trying to use the OPB IPIF Master Attachment. Does anyone know where I can find a working example of this? Thanks, pkArticle: 120297
austin wrote: > > Unfortunately, Steve Knapp has left Xilinx to pursue an opportunity that > intrigued him. We will miss him. If he's reading this, many thanks to Steve for all the help and support over the years. And good luck for the future. If at first you don't succeed, try and try and Triscend again.Article: 120298
Jon Beniston <jon@beniston.com> wrote: > > As always, if anyone has an issue with getting parts, Peter and I will > > intervene and try to find out what the problem is. > Well, I designed a board 2 years ago to use V4FX40 parts. Is there any > sign of them yet? Lol I wish Xilinx would have an inventory page like TI has, e.g. http://focus.ti.com/docs/prod/folders/print/ads1112.html -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 120299
Try contributing to this:- http://wiki.duskglow.com/tiki-index.php?page=open-graphics Plenty of opportunity for BS. ;-) HTH, Syms.
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