Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 cs_posting@hotmail.com wrote: > On May 31, 12:41 pm, Stephen Williams <spamt...@icarus.com> wrote: >> I have a demo board of my own that I put together that uses an >> EZ-USB-FX1/2. I've got it to talk USB using the default device >> and sdcc. The source code is really quite simple. I'll put a >> snapshot here: >> >> <ftp://ftp.icarus.com/pub/steve/mmc-20070531.tar.gz> > > Steve, > > Thank you for posting that. Could you perhaps provide a little > explanation as to what is there? In particular, while I see some fx2 > code and host code, and can't seem to figure out the relation between > that and the mmc card stuff. Is there an fx2 interface state machine > or anything like that in the verilog that I'm overlooking? Also, were > you running the fifo's on the fx2, or did you have the 8051 core > playing middleman? What I have there is a work in progress:-) The wb_mmc/ directory is a core I'm working on for microSD interface. The xst/ directory is a stub of a Verilog design that will contain the wb_mmc core and the interface with the FX chip. So far, it's just a stub. The demoboard/ directory is a board I designed to support my development of that core, and to provide a working example when I get there. It includes schematics and a PCB layout. Under the demoboard/ directory there are: api/ host side code (that uses libusb) to talk to the board. firmware/ 8051 code that runs on the board. For the sake of figuring out how to get an FX1 talking to the host, these are what you are looking for. The firmware/Makefile shows how to build the firmware.ihx downloadable firmware using sdcc. The api/ directory contains sample code that uses libusb to talk to the downloaded firmware. - -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.2 (GNU/Linux) Comment: Using GnuPG with SUSE - http://enigmail.mozdev.org iD8DBQFGYDbbrPt1Sc2b3ikRAiFaAKDSKaJy4wnSufDvHHkhpSeisBS5PACg4Iqr cMwMFogufE+qzfbUpY2fF18= =VmPj -----END PGP SIGNATURE-----Article: 120126
Pablo wrote: > Hi, I am very interesting in how could I use ISE to create a PowerPC > model. I know that there is a Export to Project Navigator, but it > doesn't seem to work fine. > First, I use EDK to create my PowerPC model with peripheral, > dcm_modules,... > Then I open ISE and add the system.xmp from EDK. Then I instantate and > I get the system_stub.vhd which I save at the project navigator folder > and I add to the project, so my solution is: > > system_stub.vhd > system.xmp > system.ucf > > But I cannot see the complete vhdl code. For example I cannot see the > code from the dcm_module, the code from the util_vector_module, etc. > Have you looked in $XILINX_EDK/hw/XilinxProcessorIPLib/pcores ? For example, for the dcm_module, there should be in there the directory dcm_module_v1_00_a/hdl/vhdl which contains the code for the dcm module. If you wanted to edit the code, you would create a directory "pcores" in your project, copy the core to there and give it another name, edit the various files there, and use it within your project.Article: 120127
On 1 Jun., 17:03, Pablo <pbantu...@gmail.com> wrote: > Hi, I want to ask if it is possible to load a program in the BRAM able > to run another main program (with PowerPC) in the DDR Sdram. I know > this is done by XMD but I would like another launcher program in bram > instead of running the XMD of Xilinx. > > Regards. of course! just write your own bootloader and use it ! this is not a generic task, as the bootloader has to support some method to load the code from.. AnttiArticle: 120128
On 2007-06-01, MM <mbmsv@yahoo.com> wrote: > Another thing I don't quite understand is why running > $XILINX_EDK/settings.sh script doesn's seem to have any effect on the > environment variables... So far I had to set some of them manually from bash > and some in /etc/environment... Just a quick comment regarding this.. Are you sourcing the settings.sh script as in the following? > source $XILINX_EDK/settings.sh Or are you running it as in > sh $XILINX_EDK/settings.sh If the later is true you will start a new subshell where the settings will take effect and then happily disappear after the shell script has finished running (which will occur in say a couple of microseconds after it has started...) If you are indeed sourcing the script I have no idea why it doesn't work for you. /AndreasArticle: 120129
On Jun 1, 10:10 am, Stephen Williams <spamt...@icarus.com> wrote: > >> I have a demo board of my own that I put together that uses an > >> EZ-USB-FX1/2. I've got it to talk USB using the default device > >> and sdcc. The source code is really quite simple. I'll put a > >> snapshot here: > > >> <ftp://ftp.icarus.com/pub/steve/mmc-20070531.tar.gz> > The xst/ directory is a stub of a Verilog design that will contain > the wb_mmc core and the interface with the FX chip. So far, it's > just a stub. I think you left the xst/ directory out of the tar file. > tar -tzf mmc-20070531.tar.gz | grep '/$' mmc-20070531/ mmc-20070531/demoboard/ mmc-20070531/demoboard/api/ mmc-20070531/demoboard/firmware/ mmc-20070531/demoboard/packages/ mmc-20070531/sim/ mmc-20070531/wb_mmc/Article: 120130
On 1 jun, 17:35, Antti <Antti.Luk...@googlemail.com> wrote: > On 1 Jun., 17:03, Pablo <pbantu...@gmail.com> wrote: > > > Hi, I want to ask if it is possible to load a program in the BRAM able > > to run another main program (with PowerPC) in the DDR Sdram. I know > > this is done by XMD but I would like another launcher program in bram > > instead of running the XMD of Xilinx. > > > Regards. > > of course! > > just write your own bootloader and use it ! > > this is not a generic task, as the bootloader has to support some > method to load the code from.. > > Antti Perhaps, SREC file could be run at the BRAM. Couldn't it?Article: 120131
On 1 Jun., 17:48, Pablo <pbantu...@gmail.com> wrote: > On 1 jun, 17:35, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > > > On 1 Jun., 17:03, Pablo <pbantu...@gmail.com> wrote: > > > > Hi, I want to ask if it is possible to load a program in the BRAM able > > > to run another main program (with PowerPC) in the DDR Sdram. I know > > > this is done by XMD but I would like another launcher program in bram > > > instead of running the XMD of Xilinx. > > > > Regards. > > > of course! > > > just write your own bootloader and use it ! > > > this is not a generic task, as the bootloader has to support some > > method to load the code from.. > > > Antti > > Perhaps, SREC file could be run at the BRAM. Couldn't it?- Zitierten Text ausblenden - > > - Zitierten Text anzeigen - if you parse SREC then sure AnttiArticle: 120132
On Jun 1, 7:34 am, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote: > On May 31, 11:36 pm, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > On 1 Jun., 07:41, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote: > > > > On May 31, 4:42 pm, ghel...@lycos.com wrote: > > > > > On May 31, 3:43 pm, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote: > > > > > > Anyone know how the USB Blaster cable loads data to the C3 fpga on the > > > > > board? The schematic shows a CPLD between the FPGA and the USB port. > > > > > There is a USB to parallel chip between the cpld and the usb port. > > > > > But I do not see any serial or parallel data going to the fpga. > > > > > > I wish Altera added more details to the starter kit documentation. > > > > > There is all this source code but it is encrypted. So cannot even > > > > > look at that. > > > > > > TIA > > > > > -sanjay > > > > > That CPLD along with the FT245 is the "embedded USB Blaster". You > > > > won't see any lines to the FPGA except for the JTAG leads. (I found > > > > the JTAG lines on the schematic - look again.) > > > > > The documentation looked pretty complete to me. For the Xilinx board, > > > > the page of schematic with the USB loader is *missing*, and that area > > > > of the layout is obscured. > > > > > Both companies used to ship separate dongles with their eval boards. > > > > But the plastic case of the dongle is the most expensive part, > > > > followed by the JTAG leads. By leaving those out, they can add the > > > > USB programmer for almost nothing. > > > > > It's possible that both companies contracted out the design of their > > > > USB programming pods, so they can't (legally) distribute the > > > > information on the device. (Both companies make a ton of money > > > > selling IP; you have to understand that they will respect the IP > > > > rights of others.) > > > > > Do a web search. There are a number of people actively tring to > > > > reverse engineer both dongles. At least until they discover hat > > > > they're spending 100's of hours to duplicate a gizmo that can be had > > > > for $50... > > > > > G. > > > > Sorry I wasn't clear. By data I did not mean the configuration or > > > jtag stream. Not sure if you are familiar with the C3 starter board. > > > But they have something called control panel, which you use to test > > > the dram access besides other things. You can read and write to the > > > sdram. Store entire files, etc. And the only host interface I see > > > for this is the usb interface. But I do not see any data lines. So > > > that is what I mean by data. > > > > Please let me know where to look if you find that in their > > > documentation. > > > > Thanks. > > > Best, > > > -sanjay- Zitierten Text ausblenden - > > > > - Zitierten Text anzeigen - > > > well, there is no need for more then JTAG lines ;) > > Altera FPGAs can have user logic in fabric connected to the JTAG TAP, > > so the same JTAG pins can be used to talk to the user app as well. > > this is how signaltap works as example Jtag can scan all boundary cells (most I/O pins) and using them to drive external devices as well. > > > Antti > > Thanks Antii. I had suspected this. And I think this is a cool > feature for low bandwidth operations such as serial communication. As long as the serial pins are in the boundary scan chain, which is usually the case. However, sometimes the internal buffers get in the way of boundary scans. > I am thinking how can I use this in my application? Build (or buy) your jtag scan engine, like many of us do. > Please let me know > if you have any pointers. > > TIA. > -sanjayArticle: 120133
On May 31, 11:24 pm, "Altera User" <altera_u...@nospam.com> wrote: > Ok, I tried your suggestion, but Quartus-II doesn't seem to like > interface-modports as port-declarations Last I checked it was supported. > I'd be very grateful if you could post a known *working* example > with modports in module-port declarations! Take a look at the (older) LRM: http://www.eda.org/sv/SystemVerilog_3.1a.pdf -- Edmond Cot=E9Article: 120134
"Sandip" <sandip.gaikwad@gmail.com> wrote in message news:1180686398.230080.174080@q75g2000hsh.googlegroups.com... > On Jun 1, 10:11 am, Thomas Stanka <usenet...@stanka-web.de> wrote: >> On 1 Jun., 06:52, Sandip <sandip.gaik...@gmail.com> wrote: >> >> > my design on ISE 8.1i. I completed simulation after synthesis then, >> > Translate, Post-map and Post-PAR. I was getting desired results on >> > Simulation using 100Mhz as my clock frequency. >> >> Post-PAR means at least using the netlist instead of rtl code. >> But is useless without timing information. I assume you used timing, >> else start using sdf files. >> >> > Next thing i did was put it on board and verify that design. Input >> > clock was now 8Mhz. But the output I was getting was not desirable. >> >> Identify differences between your testbench and the real world. >> First thing to look: simulate asynchronous inputs switch typically >> with fixed delay to clock, real asynchronous inputs need proper >> handling. >> >> The designflow you described seems to include all necessary steps, so >> I expect the problem to arise from your design. >> >> bye Thomas > > Hi Thomas, > > I have only two input signals, one is the clock and another is the > reset. All the signals are synchronous to the clock. > Can you please explain in detail how can move ahead using sdf files, > and giving timing constraints. I have presently not used any > constraints other than the clock frequency. > > Thanks, > Sandip > Dude .. look for clues in the real world. What are you monitoring to know that the design doesn't work? Do you have any outputs? :) Modify your design to add some debug features. For instance .. for very very basic sanity ... create an output that is a div2 of the clock and see what frequency it is in the real world. That at least tells you the FPGA has been programmed and has a valid clock. Create some other debug points that indicate certain events of your design have occured. This may give you some insight as to where things are going wrong. MikeArticle: 120135
Hello everyone, I just bought a brand new ML402 development board and found that all reference designs are bit streams. I'd like to start implementing a VGA interface much like the one provided as a reference design (ie. load data from CF and show them on monitor), so I am searching for either sourcecodes of the reference design (in case they are available and I have overlooked them) and/or for simulation models for peripherals if these are commonly available. Any pointers and directions welcome. Regards, Tomas PS: I am sorry for doubleposting, I am still trying to come to grips with Thunderbird as a news clientArticle: 120136
On Jun 1, 8:24 am, ferorcue <le_m...@hotmail.com> wrote: > On Jun 1, 11:48 am, "CTU FEE Jan Krakora" > > <krak...@control.felk.cvut.cz> wrote: > > Hi fellows, > > > no, the problem is not OS specific, because I'm using Windows XP system (due to USB cable, not working under any Linux system). I think the problem is in thesimulationIP cores used by ModelSim tool. I think we should inquire ofXilinxcorp. after the problem to be solved, as soon as better. > > > I have also tried to change the OPB core revision to the depricated version 1.10b (older version of 1.10c, the default one), but Modelsim refused me with any warnings and errors. I will analyse it, we will see. > > > Stay in touch Regards Jan > > Hi friends, > > I think that I have the solution, I found it in axilinxwebcase. > in system_setup.do change: > "vsim -novopt -t ps system_conf; set xcmds 1;" > > Source: > > 9.1i EDK ModelSim - Error message: "logic.vhd(359): (vopt-1144) Value > 0 is out of std.standard.natural range 1 to 32" > 04/24/07 11:14:13 > > Problem Description: > > Keywords: optimization, -vopt, -novopt > > I am trying to simulate my EDK system. When I run thesimulationin > ModelSim 6.2b, I receive an error message similar to the following > during the optimization phase: > > "Error Message: > --------------------------------------- > > D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_v20_v1_10_c/hdl/vhdl/ > opb_v20. > vhd(550): (vopt-1144) Value 0 is out of std.standard.natural range 1 > to > 32. > # ** Error: > D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/ > park > _lock_logic.vhd(359): (vopt-1144) Value 0 is out of > std.standard.natural > range 1 to 32. > # ** Error: > D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/ > park > _lock_logic.vhd(429): (vopt-1144) Value 0 is out of > std.standard.natural > range 1 to 32. > # Optimization failed > # Error loading design > # Error: Error loading design > # Pausing macro execution" > > I was able to simulate this same design using a previous version of > ModelSim (for example, 6.0a and 6.2a). The previous version of > ModelSim did not include this optimization phase. What could be the > problem? > Solution 1: > The problem is that in the later version of ModelSim, it is > automatically inserting the -vopt command by default, which clashes > with the EDK IP files for the EDK cores. This command performs global > optimization on Verilog and mixed-HDL designs after they are compiled, > which is not necessary for the EDK IP models. > > You can work around this issue by inserting the -novopt command in the > "do file" that you are using to run thesimulation. Alternatively, you > can work around this issue by setting the "modelsim.ini" variable > "VoptFlow" to 0 (zero). The "modelsim.ini" files are located in the c: > \<modelsim>\, c:\<ise_compiled_libraries> and c: > \<edk_compiled_libraries> directories Hi, Please send this information to Mentor Grpahics. They implemented vopt by default in order to improve simulation performance, although that does mean that it works seamlessly. Mentor is very keen on fixing all issues that have to do with vopt, so please send them this feedback so that you no longer have to use the -novopt switch. Using the simulator in default should be the ideal solution and all problems with the optimizer should be addressed. Thanks DuthArticle: 120137
Peter Alfke <peter@xilinx.com> wrote: >Just to put it in perspective: >Amsterdam to Eindhoven is 120 km or 75 miles, barely an hour's drive. That is probably true on sunday 22:00 in the evening during the summer holiday and if you have money to pay for the speeding tickets. The rest of the week it is a bigger misery due to traffic congestion. 3 hours is more likely (using the train may be faster if nothing goes wrong there). >But 6 hours by bicycle, the favorite mode of transportation. >Nice, flat country... :-) >(I grew up just on the other side of that border, and rode my bike all >over the Netherlands, long time ago.) >Peter > > > >Nico Coesel wrote: >> Peter Alfke <peter@xilinx.com> wrote: >> >>> Avnet picked Eindhoven as the preferred site in the Netherlands. >> >> They probably didn't want to drive too far themselves. Eindhoven is a >> bit of a technology hotspot due to Philips but it is in the east part >> of the country. Most people and companies are located in the west part >> of the country. Most major events are therefore either located in >> Amsterdam or Utrecht. >> >>> But the X-Fest seminar there was a month ago... >>> But the traditional European FPGA conference will be in Amsterdam in >>> August. >> >> Allright! >> -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 120138
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 cs_posting@hotmail.com wrote: > On Jun 1, 10:10 am, Stephen Williams <spamt...@icarus.com> wrote: > >>>> I have a demo board of my own that I put together that uses an >>>> EZ-USB-FX1/2. I've got it to talk USB using the default device >>>> and sdcc. The source code is really quite simple. I'll put a >>>> snapshot here: >>>> <ftp://ftp.icarus.com/pub/steve/mmc-20070531.tar.gz> > >> The xst/ directory is a stub of a Verilog design that will contain >> the wb_mmc core and the interface with the FX chip. So far, it's >> just a stub. > > I think you left the xst/ directory out of the tar file. > >> tar -tzf mmc-20070531.tar.gz | grep '/$' > mmc-20070531/ > mmc-20070531/demoboard/ > mmc-20070531/demoboard/api/ > mmc-20070531/demoboard/firmware/ > mmc-20070531/demoboard/packages/ > mmc-20070531/sim/ > mmc-20070531/wb_mmc/ > Guess it's not in CVS. I made the tarball via a CVS export. Oh well, it's a blank stub anyhow. For the purposes of getting the FX chip working iwth sdcc, demoboard/api and demoboard/firmware are all you need anyhow. - -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.2 (GNU/Linux) Comment: Using GnuPG with SUSE - http://enigmail.mozdev.org iD8DBQFGYEiDrPt1Sc2b3ikRAqczAKDIKwfymq6E+YUUCa7c53bpDik8HACgskEY qPLyPfHJtKEgRvPG3zjzV68= =PnZL -----END PGP SIGNATURE-----Article: 120139
On Jun 1, 11:25 am, Stephen Williams <spamt...@icarus.com> wrote: > Guess it's not in CVS. I made the tarball via a CVS export. Oh well, > it's a blank stub anyhow. For the purposes of getting the FX chip > working iwth sdcc, demoboard/api and demoboard/firmware are all you > need anyhow. My issue is not with getting the computer talking to the fx2 chip - I can already do that (can jtag program an FPGA with it). The issue is finding a generic example for using the fx2 fifos to interface with an FPGA. Most the projects I'm aware of that implement this also implement a lot of extraneous stuff which makes it very hard to tell what exactly they are doing. Thus I'm back to sorting it out from scratch.Article: 120140
Tomas Davidovic wrote:
> Hello everyone,
> I just bought a brand new ML402 development board and found that all
> reference designs are bit streams.
> I'd like to start implementing a VGA interface much like the one
> provided as a reference design (ie. load data from CF and show them on
> monitor), so I am searching for either sourcecodes of the reference
> design (in case they are available and I have overlooked them) and/or
> for simulation models for peripherals if these are commonly available.
>
> Any pointers and directions welcome.
>
> Regards,
> Tomas
> PS: I am sorry for doubleposting, I am still trying to come to grips
> with Thunderbird as a news client
We have all of the reference designs online in the ML402 board area
http://www.xilinx.com/ml402
-> (Documentation) ML402 Demo and Reference Designs
-> ML402 DSP48 Video Demonstration (I think this is the one you want)
-> documentation and source files (ZIP)
Ed McGettigan
--
Xilinx Inc.
Article: 120141OK, I am now a little bit stuck with the EDK... When I try to start it, it says the following: _xps: error while loading shared libraries: libPortability.so : cannot open shared object file : no such file or directory. If I set LD_ASSUME_KERNEL=2.4.7 (or 2.4.1) then it seems to break something severely in bash so that I can't even do printenv and xps doesn't start either... I suspect that the problem might have something to do with the fact that I have both libstdc++5 and libstdc++6 installed. According to the http://ubuntuforums.org:80/showthread.php?t=349336 only libstdc++5 is required, however I am not sure now at which point libstdc++6 was installed and what will I break if I try uninstalling it... All other environment variables seem to be set correctly, at least in the bash session I am using to launch the app...ISE launches fine as well as Impact does... Another thing I don't quite understand is why running $XILINX_EDK/settings.sh script doesn's seem to have any effect on the environment variables... So far I had to set some of them manually from bash and some in /etc/environment... Thanks, /MikhailArticle: 120142
On 1 Jun., 17:53, linnix <m...@linnix.info-for.us> wrote: > On Jun 1, 7:34 am, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote: > > > > > > > On May 31, 11:36 pm, Antti <Antti.Luk...@googlemail.com> wrote: > > > > On 1 Jun., 07:41, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote: > > > > > On May 31, 4:42 pm, ghel...@lycos.com wrote: > > > > > > On May 31, 3:43 pm, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote: > > > > > > > Anyone know how the USB Blaster cable loads data to the C3 fpga on the > > > > > > board? The schematic shows a CPLD between the FPGA and the USB port. > > > > > > There is a USB to parallel chip between the cpld and the usb port. > > > > > > But I do not see any serial or parallel data going to the fpga. > > > > > > > I wish Altera added more details to the starter kit documentation. > > > > > > There is all this source code but it is encrypted. So cannot even > > > > > > look at that. > > > > > > > TIA > > > > > > -sanjay > > > > > > That CPLD along with the FT245 is the "embedded USB Blaster". You > > > > > won't see any lines to the FPGA except for the JTAG leads. (I found > > > > > the JTAG lines on the schematic - look again.) > > > > > > The documentation looked pretty complete to me. For the Xilinx board, > > > > > the page of schematic with the USB loader is *missing*, and that area > > > > > of the layout is obscured. > > > > > > Both companies used to ship separate dongles with their eval boards. > > > > > But the plastic case of the dongle is the most expensive part, > > > > > followed by the JTAG leads. By leaving those out, they can add the > > > > > USB programmer for almost nothing. > > > > > > It's possible that both companies contracted out the design of their > > > > > USB programming pods, so they can't (legally) distribute the > > > > > information on the device. (Both companies make a ton of money > > > > > selling IP; you have to understand that they will respect the IP > > > > > rights of others.) > > > > > > Do a web search. There are a number of people actively tring to > > > > > reverse engineer both dongles. At least until they discover hat > > > > > they're spending 100's of hours to duplicate a gizmo that can be had > > > > > for $50... > > > > > > G. > > > > > Sorry I wasn't clear. By data I did not mean the configuration or > > > > jtag stream. Not sure if you are familiar with the C3 starter board. > > > > But they have something called control panel, which you use to test > > > > the dram access besides other things. You can read and write to the > > > > sdram. Store entire files, etc. And the only host interface I see > > > > for this is the usb interface. But I do not see any data lines. So > > > > that is what I mean by data. > > > > > Please let me know where to look if you find that in their > > > > documentation. > > > > > Thanks. > > > > Best, > > > > -sanjay- Zitierten Text ausblenden - > > > > > - Zitierten Text anzeigen - > > > > well, there is no need for more then JTAG lines ;) > > > Altera FPGAs can have user logic in fabric connected to the JTAG TAP, > > > so the same JTAG pins can be used to talk to the user app as well. > > > this is how signaltap works as example > > Jtag can scan all boundary cells (most I/O pins) and using them to > drive external devices as well. > > > > > > Antti > > > Thanks Antii. I had suspected this. And I think this is a cool > > feature for low bandwidth operations such as serial communication. > > As long as the serial pins are in the boundary scan chain, which is > usually the case. However, sometimes the internal buffers get in the > way of boundary scans. > > > I am thinking how can I use this in my application? > > Build (or buy) your jtag scan engine, like many of us do. > > > > > Please let me know > > if you have any pointers. > > > TIA. > > -sanjay- Zitierten Text ausblenden - > > - Zitierten Text anzeigen -- Zitierten Text ausblenden - > > - Zitierten Text anzeigen - hm, when you use the "JTAG in FPGA fabric" approuch then JTAG boundary scan chain is NOT USED. so it doesnt matter at all how the boundary scan is implemented or if it even exists. "custom instructions" are handled by FPGA fabric the speed depends on the JTAG master, it may reach 40MHz+ AnttiArticle: 120143
On Jun 1, 10:12 am, Antti <Antti.Luk...@googlemail.com> wrote: > On 1 Jun., 17:53, linnix <m...@linnix.info-for.us> wrote: > > > > > On Jun 1, 7:34 am, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote: > > > > On May 31, 11:36 pm, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > On 1 Jun., 07:41, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote: > > > > > > On May 31, 4:42 pm, ghel...@lycos.com wrote: > > > > > > > On May 31, 3:43 pm, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote: > > > > > > > > Anyone know how the USB Blaster cable loads data to the C3 fpga on the > > > > > > > board? The schematic shows a CPLD between the FPGA and the USB port. > > > > > > > There is a USB to parallel chip between the cpld and the usb port. > > > > > > > But I do not see any serial or parallel data going to the fpga. > > > > > > > > I wish Altera added more details to the starter kit documentation. > > > > > > > There is all this source code but it is encrypted. So cannot even > > > > > > > look at that. > > > > > > > > TIA > > > > > > > -sanjay > > > > > > > That CPLD along with the FT245 is the "embedded USB Blaster". You > > > > > > won't see any lines to the FPGA except for the JTAG leads. (I found > > > > > > the JTAG lines on the schematic - look again.) > > > > > > > The documentation looked pretty complete to me. For the Xilinx board, > > > > > > the page of schematic with the USB loader is *missing*, and that area > > > > > > of the layout is obscured. > > > > > > > Both companies used to ship separate dongles with their eval boards. > > > > > > But the plastic case of the dongle is the most expensive part, > > > > > > followed by the JTAG leads. By leaving those out, they can add the > > > > > > USB programmer for almost nothing. > > > > > > > It's possible that both companies contracted out the design of their > > > > > > USB programming pods, so they can't (legally) distribute the > > > > > > information on the device. (Both companies make a ton of money > > > > > > selling IP; you have to understand that they will respect the IP > > > > > > rights of others.) > > > > > > > Do a web search. There are a number of people actively tring to > > > > > > reverse engineer both dongles. At least until they discover hat > > > > > > they're spending 100's of hours to duplicate a gizmo that can be had > > > > > > for $50... > > > > > > > G. > > > > > > Sorry I wasn't clear. By data I did not mean the configuration or > > > > > jtag stream. Not sure if you are familiar with the C3 starter board. > > > > > But they have something called control panel, which you use to test > > > > > the dram access besides other things. You can read and write to the > > > > > sdram. Store entire files, etc. And the only host interface I see > > > > > for this is the usb interface. But I do not see any data lines. So > > > > > that is what I mean by data. > > > > > > Please let me know where to look if you find that in their > > > > > documentation. > > > > > > Thanks. > > > > > Best, > > > > > -sanjay- Zitierten Text ausblenden - > > > > > > - Zitierten Text anzeigen - > > > > > well, there is no need for more then JTAG lines ;) > > > > Altera FPGAs can have user logic in fabric connected to the JTAG TAP, > > > > so the same JTAG pins can be used to talk to the user app as well. > > > > this is how signaltap works as example > > > Jtag can scan all boundary cells (most I/O pins) and using them to > > drive external devices as well. > > > > > Antti > > > > Thanks Antii. I had suspected this. And I think this is a cool > > > feature for low bandwidth operations such as serial communication. > > > As long as the serial pins are in the boundary scan chain, which is > > usually the case. However, sometimes the internal buffers get in the > > way of boundary scans. > > > > I am thinking how can I use this in my application? > > > Build (or buy) your jtag scan engine, like many of us do. > > > > Please let me know > > > if you have any pointers. > > > > TIA. > > > -sanjay- Zitierten Text ausblenden - > > > - Zitierten Text anzeigen -- Zitierten Text ausblenden - > > > - Zitierten Text anzeigen - > > hm, > when you use the "JTAG in FPGA fabric" approuch then JTAG boundary > scan chain is NOT USED. There are certainly many ways to configurate the FPGA. For development and temperatory configuration, you can jtag into the FPGA directly. However, real app configuration is usually stored in external flash chip. A typical jtag tool would program the external flash chip via boundary scan.Article: 120144
"MM" <mbmsv@yahoo.com> wrote in message news:5cb28eF2v3r9cU1@mid.individual.net... > > Another thing I don't quite understand is why running > $XILINX_EDK/settings.sh script doesn's seem to have any effect on the > environment variables... So far I had to set some of them manually from > bash and some in /etc/environment... > For other linux newbies out there I figured this one out... Bash needs to be told that commands from the filename argument need to be executed in the _current_ shell context. Otherwise it will create another context, which will disappear as soon as the script ends... The way to tell this to bash is to precede the filename with a dot. Thus, assuming the settings.sh is made executable (and shebang added in the first line of the file) one has to do the following: $ . settings.sh and not $ settings.sh /MikhailArticle: 120145
Right now I'm using the ISE 8.2i for an FPGA project and doing simulation with a circuit in vhdl in different locations of a single FPGA. In order to make the compared parameters meaningful, I need to ensure that in all the different locations on the FPGA chip, the relative placement and routing of the circuit modules are the same. To ensure the same relative placement, I can move the whole circuit around the FPGA chip in the Floorplan program. But I'm not quite sure about how to guarantee the same routing of the whole circuit. If I choose automatic routing, will there be possibilities that ISE will make different routings between different locations of the circuit? Is manually routing the ONLY way to guarantee the same routing between different locations of the circuit? Thanks!Article: 120146
Thanks, I am looking for something in VHDL/Verilog, tho. Didn't realise these file could actually be the design. Tomas Ed McGettigan napsal(a): > Tomas Davidovic wrote: >> Hello everyone, >> I just bought a brand new ML402 development board and found that all >> reference designs are bit streams. >> I'd like to start implementing a VGA interface much like the one >> provided as a reference design (ie. load data from CF and show them on >> monitor), so I am searching for either sourcecodes of the reference >> design (in case they are available and I have overlooked them) and/or >> for simulation models for peripherals if these are commonly available. >> >> Any pointers and directions welcome. >> >> Regards, >> Tomas >> PS: I am sorry for doubleposting, I am still trying to come to grips >> with Thunderbird as a news client > > We have all of the reference designs online in the ML402 board area > > http://www.xilinx.com/ml402 > -> (Documentation) ML402 Demo and Reference Designs > -> ML402 DSP48 Video Demonstration (I think this is the one you want) > -> documentation and source files (ZIP) > > Ed McGettigan > -- > Xilinx Inc.Article: 120147
"MM" <mbmsv@yahoo.com> wrote in message news:5cb28eF2v3r9cU1@mid.individual.net... > OK, I am now a little bit stuck with the EDK... Having another problem :( I've decided to try installing the latest EDK service pack (SP2) and the installer refused to accept my Registration ID, which it happily accepted during the original EDK installation... /MikhailArticle: 120148
Is there an example of a modular design project for ISE that I can download. I could not find one on the xilnx website or included in the ISE examples directory Beyond a picture shown in the Development System Reference Guide and reading the chapter on modular design, I am really no closer to understanding how to setup such a project.Article: 120149
"MM" <mbmsv@yahoo.com> wrote in message news:5cb28eF2v3r9cU1@mid.individual.net... > OK, I am now a little bit stuck with the EDK... When I try to start it, it > says the following: > > _xps: error while loading shared libraries: libPortability.so : cannot > open shared object file : no such file or directory. I found that this library is in fact in the ISE directory $XILINX/bin/lin. I copied it into $XILINX_EDK/bin/lin (which is set to LD_LIBRARY_PATH) and it complained about another library, which I also found in the ISE tree. After I copied a few dozens of these libraries xps finally started, but with a blank window :( Arghh... What am I missing here?... I am posting the same question on Ubuntu forum in the "Xilinx on Ubuntu" thread: http://ubuntuforums.org/showthread.php?p=2763922#post2763922 Thanks, /Mikhail
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z