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Hi,everyone,now i want to know how can i change the high speed data between 2 chips=A3=A8one from lattice scm and one from xilinx=A3=A9,now I u= se the lattice sc for pci-e interface and the xilinx fpga for data processing=A3=A8coperate with others familiar with xilinx=A3=A9.Can any giv= e me some advice.Article: 118476
On Apr 26, 8:06 pm, motty <mottobla...@yahoo.com> wrote: > Yeah, I never could get that EDK wizard to work either. Don't know if > this will help, but I compiled the non-EDK libraries in the ISE and > that worked. I then used the command line to compile the EDK > libraries for a particular project. Then everything was happy. Hi, Motty: Can you tell me how to complie the ISE libaries in ISE? I used command line to complile the ISE file and then EDK widzard to compile the EDK library. Then the EDK can only recongnize EDK library.Article: 118477
How fortunate for me that this thread has evolved into a discussion about emacs. I am using Xemacs in Windows with the verilog mode. I want to insert spaces in place of tabs. I put (setq-default indent-tabs-mode nil); in my custom.el and in verilog.el, but tabs are not being implemented as spaces in my verilog files (but they are implemented as spaces in other files). Any ideas? --- Joe Samson Pixel VelocityArticle: 118478
If you want to generate a precise average output frequency, you must NOT clear the accunulator. The unavoidable problem is then that the output periods vary, which is called jitter. The max jitter is (almost) one whole clock period. If you reset, you avoid the jitter, but you are not generating the frequency you intended to generate. Peter Alfke On Apr 27, 6:22 am, fp <fpga002...@yahoo.com> wrote: > Hi, > > I am implementing a direct digital frequency synthesizer in FPGA. It > follows the equation > > Fo = N * Fs / (2^M) > > The implementastion is done by an M-bit phase accumulator. My question > is: if 2^M cannot be divided by N, should the accumulator be cleared > to zero when wrapping around? > > The VHDL code for automatical wrap-around is: > > process(clk, reset) > begin > if reset='1' then > q<=(others=>'0'); > elsif rising_edge(clk) then > q <= q + N; > end if; > end process; > > The VHDL code for clear-to-zero wrap-around is: > > process(clk, reset) > varaible:tmp: ... > begin > tmp := q + N; > if reset='1' then > q<=(others=>'0'); > elsif rising_edge(clk) then > if (q > tmp) then --reach 2^M-1 and wrap around > q <= (others=>'0') > else > q<= tmp; > end if; > end if; > end process; > > Which method is better ane why? Thanks in advance. > > S. C.Article: 118479
Hi everyone, I have a problem that is bugging me for 2 days now and I was hoping someone here might be able to help me out. The problem is as follows: I want to implement a DDR2 RAM Controller in a Xilinx Virtex 4 FX FPGA on the Xilinx ML410 eval board. It's supposed to run at 200 MHz, which I want to derive from the on-board 100 MHz oscillator. For this I need to use 2 DCMs cascaded (1 to get to 200 MHz, and the second one for all the other frequencies the RAM controller [generated with MIG 1.6] needs (main problem is the 200 MHz shifted by 90 deg). The first one works perfectly fine, only the second one never locks. Even in a module with just the 2 DCMs and Clock Buffers it fails to work. All the clocks fall well within the ranges of the modes I use and everything is connected as recommended by Xilinx. I use the CLK2X output of the first one to specifically avoid excessive jitter, I delay the config done flag until the first one has locked, I use the inverted lock output of the first one to reset the second one with a shift register in between. I already tried to manually place the DCMs at specific locations and impose timing constraints on the signal in between. The interesting thing is that the CLKFX output seems to work fine, I checked that on a scope, only the others fail to work. And even more interesting, 1 week ago I implemented a DDR RAM Controller in which I used exactly the same structure except that it was running at 160 MHz and I didn't have any problems at all. If I try to do same now, it still doesn't work!! So after about 20 hours of trying I just ran out of ideas. Maybe someone of you has another idea. Cheers, MichaelArticle: 118480
MNiegl <Michael.Niegl@cern.ch> wrote: >Hi everyone, > >I have a problem that is bugging me for 2 days now and I was hoping >someone here might be able to help me out. >The problem is as follows: >I want to implement a DDR2 RAM Controller in a Xilinx Virtex 4 FX FPGA >on the Xilinx ML410 eval board. It's supposed to run at 200 MHz, which >I want to derive from the on-board 100 MHz oscillator. For this I need >to use 2 DCMs cascaded (1 to get to 200 MHz, and the second one for >all the other frequencies the RAM controller [generated with MIG 1.6] >needs (main problem is the 200 MHz shifted by 90 deg). The first one >works perfectly fine, only the second one never locks. Even in a >module with just the 2 DCMs and Clock Buffers it fails to work. All >the clocks fall well within the ranges of the modes I use and >everything is connected as recommended by Xilinx. I use the CLK2X >output of the first one to specifically avoid excessive jitter, I >delay the config done flag until the first one has locked, I use the >inverted lock output of the first one to reset the second one with a >shift register in between. I already tried to manually place the DCMs >at specific locations and impose timing constraints on the signal in >between. >The interesting thing is that the CLKFX output seems to work fine, I >checked that on a scope, only the others fail to work. And even more >interesting, 1 week ago I implemented a DDR RAM Controller in which I >used exactly the same structure except that it was running at 160 MHz >and I didn't have any problems at all. If I try to do same now, it >still doesn't work!! >So after about 20 hours of trying I just ran out of ideas. Maybe >someone of you has another idea. Check the device's errata sheets to see if there is something wrong with the DCMs in certain batches. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 118481
Do not cascade the DCMs. Drive both in parallel from the 100 MHz oscillator. Peter Alfke On Apr 27, 11:07 am, MNiegl <Michael.Ni...@cern.ch> wrote: > Hi everyone, > > I have a problem that is bugging me for 2 days now and I was hoping > someone here might be able to help me out. > The problem is as follows: > I want to implement a DDR2 RAM Controller in a Xilinx Virtex 4 FX FPGA > on the Xilinx ML410 eval board. It's supposed to run at 200 MHz, which > I want to derive from the on-board 100 MHz oscillator. For this I need > to use 2 DCMs cascaded (1 to get to 200 MHz, and the second one for > all the other frequencies the RAM controller [generated with MIG 1.6] > needs (main problem is the 200 MHz shifted by 90 deg). The first one > works perfectly fine, only the second one never locks. Even in a > module with just the 2 DCMs and Clock Buffers it fails to work. All > the clocks fall well within the ranges of the modes I use and > everything is connected as recommended by Xilinx. I use the CLK2X > output of the first one to specifically avoid excessive jitter, I > delay the config done flag until the first one has locked, I use the > inverted lock output of the first one to reset the second one with a > shift register in between. I already tried to manually place the DCMs > at specific locations and impose timing constraints on the signal in > between. > The interesting thing is that the CLKFX output seems to work fine, I > checked that on a scope, only the others fail to work. And even more > interesting, 1 week ago I implemented a DDR RAM Controller in which I > used exactly the same structure except that it was running at 160 MHz > and I didn't have any problems at all. If I try to do same now, it > still doesn't work!! > So after about 20 hours of trying I just ran out of ideas. Maybe > someone of you has another idea. > > Cheers, > MichaelArticle: 118482
MNiegl, Well, it seems that if you are doing everything right, and it worked last time at 160 MHz, it has no excuse but to work this time. When I am faced with these kinds of problems, I go back and check absolutely everything: it is likely the mistake is right there in front of you, and you are not seeing it. Have you looked at the DCM in FPGA Editor? Sometimes you immediately see that the code you wrote is doing exactly what it is supposed to (and not what you want). Peter is fond of saying, "when your car dies on the road, do you first check to see if the spark plug gap is correct? No, you check the most likely cause - are you out of gas..." Austin > Hi everyone, > > I have a problem that is bugging me for 2 days now and I was hoping > someone here might be able to help me out. > The problem is as follows: > I want to implement a DDR2 RAM Controller in a Xilinx Virtex 4 FX FPGA > on the Xilinx ML410 eval board. It's supposed to run at 200 MHz, which > I want to derive from the on-board 100 MHz oscillator. For this I need > to use 2 DCMs cascaded (1 to get to 200 MHz, and the second one for > all the other frequencies the RAM controller [generated with MIG 1.6] > needs (main problem is the 200 MHz shifted by 90 deg). The first one > works perfectly fine, only the second one never locks. Even in a > module with just the 2 DCMs and Clock Buffers it fails to work. All > the clocks fall well within the ranges of the modes I use and > everything is connected as recommended by Xilinx. I use the CLK2X > output of the first one to specifically avoid excessive jitter, I > delay the config done flag until the first one has locked, I use the > inverted lock output of the first one to reset the second one with a > shift register in between. I already tried to manually place the DCMs > at specific locations and impose timing constraints on the signal in > between. > The interesting thing is that the CLKFX output seems to work fine, I > checked that on a scope, only the others fail to work. And even more > interesting, 1 week ago I implemented a DDR RAM Controller in which I > used exactly the same structure except that it was running at 160 MHz > and I didn't have any problems at all. If I try to do same now, it > still doesn't work!! > So after about 20 hours of trying I just ran out of ideas. Maybe > someone of you has another idea. > > Cheers, > Michael >Article: 118483
On Apr 27, 8:18 pm, n...@puntnl.niks (Nico Coesel) wrote: > MNiegl <Michael.Ni...@cern.ch> wrote: > >Hi everyone, > > >I have a problem that is bugging me for 2 days now and I was hoping > >someone here might be able to help me out. > >The problem is as follows: > >I want to implement a DDR2 RAM Controller in a Xilinx Virtex 4 FX FPGA > >on the Xilinx ML410 eval board. It's supposed to run at 200 MHz, which > >I want to derive from the on-board 100 MHz oscillator. For this I need > >to use 2 DCMs cascaded (1 to get to 200 MHz, and the second one for > >all the other frequencies the RAM controller [generated with MIG 1.6] > >needs (main problem is the 200 MHz shifted by 90 deg). The first one > >works perfectly fine, only the second one never locks. Even in a > >module with just the 2 DCMs and Clock Buffers it fails to work. All > >the clocks fall well within the ranges of the modes I use and > >everything is connected as recommended by Xilinx. I use the CLK2X > >output of the first one to specifically avoid excessive jitter, I > >delay the config done flag until the first one has locked, I use the > >inverted lock output of the first one to reset the second one with a > >shift register in between. I already tried to manually place the DCMs > >at specific locations and impose timing constraints on the signal in > >between. > >The interesting thing is that the CLKFX output seems to work fine, I > >checked that on a scope, only the others fail to work. And even more > >interesting, 1 week ago I implemented a DDR RAM Controller in which I > >used exactly the same structure except that it was running at 160 MHz > >and I didn't have any problems at all. If I try to do same now, it > >still doesn't work!! > >So after about 20 hours of trying I just ran out of ideas. Maybe > >someone of you has another idea. > > Check the device's errata sheets to see if there is something wrong > with the DCMs in certain batches. > > -- > Reply to nico@nctdevpuntnl (punt=.) > Bedrijven en winkels vindt U opwww.adresboekje.nl Thanks for the quick suggestions. First of all Peter, I would love to use them in parallel I just don't know how I can get a 90-deg phase- shifted 200 MHz clk without a lot of other twiddling. The DCMs provide that output only for the CLK0 and that is in parallel only 100 MHz. Other than that, I will check the erratas, thanks for that Cheers, MichaelArticle: 118484
On Apr 26, 10:43 pm, Bob <bob36...@yahoo.com> wrote: > I have a Spartan3E Starter Kit, and I am trying to > figure out how to use the DCM to double the freq > from 50MHz to 100MHz. > > NET "clk_50mhz" PERIOD=20.0ns HIGH 40%; > NET "clk_100mhz" PERIOD=10.0ns HIGH 50%; I think I made exactly this same error when I was first starting out. In this case, you're setting a constraint telling the placer/router that you want the net "clk_100mhz" to be routed such that it can safely carry a signal at 100Mhz. However, this doesn't actually /drive/ the line. You need to explicitly instantiate a dcm instance for that. Coregen can generate one for you, or it's almost as easy to look at the library guide to figure it out. See doc/usenglish/books/manuals.pdf inside your Xilinx install directory for the library guide for your platform. Good luck.Article: 118485
On Apr 27, 8:22 pm, Austin Lesea <aus...@xilinx.com> wrote: > MNiegl, > > Well, it seems that if you are doing everything right, and it worked > last time at 160 MHz, it has no excuse but to work this time. > > When I am faced with these kinds of problems, I go back and check > absolutely everything: it is likely the mistake is right there in front > of you, and you are not seeing it. > > Have you looked at the DCM in FPGA Editor? Sometimes you immediately > see that the code you wrote is doing exactly what it is supposed to (and > not what you want). > > Peter is fond of saying, "when your car dies on the road, do you first > check to see if the spark plug gap is correct? No, you check the most > likely cause - are you out of gas..." > > Austin > > > Hi everyone, Hi Austin, Actually, at the moment I'm heavily banking on my own stupidity and hope that it's only one small mistake I just can't find. Until now I only checked the DCM locations in FPGA Editor, I'll look at that some more intensively. And I love that quote from Peter, it's so true but sometimes so hard to obey. Cheers, MichaelArticle: 118486
Hi, I am designing a memory controller for a Micron CellularRam and would like to ask what is the best way to generate and what are the optimal buffers, constraints for the clock that needs to be fed to the RAM chip (75 MHz) when operating in synchronous mode and only then. This clock is solely sent to the chip and not used by any other internal logic. Thanks, MartArticle: 118487
Hello, to due a unfortunate chain of events, the cooler of the ep2s60 dropped to the right side of the chip and short-circuit an unkown number of lines (could be at least 1.2V and GND). Fuse F3 has been destroyed, so only LED5 was ON; the rest of the board has been dead. I replaced F3 and now the board is trying to program the FPGA from flash (User LED and Flash_CE_n are ON), but it never succeeds. Pressing the button 'Reset Config' turns all LEDs OFF, except LED5. If I press 'Factory Config' after that, the LED 'Loading' turns itself periodically ON and OFF (period is about 15-20 seconds) a few times and finally stops with the LED 'Error' ON (everything else beside LED5 is OFF). Programming the Stratix-II via JTAG works fine - with the exception that any bus access seems to fail (e.g. a Nios design reacts to the cpu reset button, but after a reset Flash_CE_n turns ON and never turns OFF again). Unfortunately I have no oscilloscope or logic analyzer at hand to further analyze the problem. So if you have any hint or advice except buying a new board (which I am already about to do), I am certainly listening. Thanks in advance, Bernhard FroemelArticle: 118488
You can either open an existing project or create a new one. In the Sources window you select the FPGA part. Then in the Processes window, expand Design Utilities. There is a Compile HDL Simulation Libraries selection. You can right click on it and choose Properties to change options. That's it.Article: 118489
Ups, my post was a little premature in retrospective :) It's been the oscillator ... now everything works again! Nice greetings, Bernhard Froemel On 27 Apr., 22:24, bfroe...@gmail.com wrote: > Hello, > > to due a unfortunate chain of events, the cooler of the ep2s60 dropped > to the right side of the chip and short-circuit an unkown number of > lines (could be at least 1.2V and GND). > Fuse F3 has been destroyed, so only LED5 was ON; the rest of the > board has been dead. I replaced F3 and now the board is trying to > program the FPGA from flash (User LED and Flash_CE_n are ON), but it > never succeeds. > Pressing the button 'Reset Config' turns all LEDs OFF, except LED5. If > I press 'Factory Config' after that, the LED 'Loading' turns itself > periodically ON and OFF (period is about 15-20 seconds) a few times > and finally stops with the LED 'Error' ON (everything else beside LED5 > is OFF). > > Programming the Stratix-II via JTAG works fine - with the exception > that any bus access seems to fail (e.g. a Nios design reacts to the > cpu reset button, but after a reset Flash_CE_n turns ON and never > turns OFF again). > > Unfortunately I have no oscilloscope or logic analyzer at hand to > further analyze the problem. > > So if you have any hint or advice except buying a new board (which I > am already about to do), I am certainly listening. > > Thanks in advance, > Bernhard FroemelArticle: 118490
Congrats !! I was worried for you and am glad you have the board up & running again. <bfroemel@gmail.com> wrote in message news:1177706407.736943.138170@b40g2000prd.googlegroups.com... > Ups, my post was a little premature in retrospective :) > > It's been the oscillator ... now everything works again! > > Nice greetings, > Bernhard FroemelArticle: 118491
On Apr 26, 11:41 pm, mohan <kulka...@math.net> wrote: > Can i programme non-xilinx fpga through xilinx impact tool & by using > xilinx parrellel four cable? Using their cable? Sure, you just need software to drive it. You might have to operate it in a slower bit bang sort of mode. Using impact? maybe, but it won't be easy. If you can get the data and algorithm into a generic form that impact will execute, such as maybe an SVF, you might be able to do it that way. Keep in mind that programming an FPGA is basically requires 1) a few bits interface to a processor, with suitable voltage level translation, this might be as simple as a parallel port and some resistors 2) software that can twiddle those bits the right way Neither is all that complicated if you can get your hands on the information. Both altera and actel for example provide example software for configuring their devices via a file format that their tools will export (jam/stp)Article: 118492
On Apr 27, 4:37 pm, motty <mottobla...@yahoo.com> wrote: > You can either open an existing project or create a new one. In the > Sources window you select the FPGA part. Then in the Processes > window, expand Design Utilities. There is a Compile HDL Simulation > Libraries selection. You can right click on it and choose Properties > to change options. That's it. Thanks a lot.Article: 118493
I have two pin one is IN and the other is INOUT and they each one goes to the D input of two FFs clocked by two different clocks Clk1, Clk2. When I start the PAR process, Xilinx tool complains with the following error: ERROR:Place:17 - The placement constraints of the IOBs sck and sdi makes this design unroutable due to a physical routing limitation. This device has a shared routing resource connecting the ICLK and OTCLK pins on pairs of IOBs. This restriction means that these pairs of pins must be driven by the same signal or one of the signals will be unroutable. Before continuing please remove the placement constraints or move one of these IOBs to a new location. The strange thing is that after looking at the design in the FPGA editor, IOBs OTCLK are not used at all in the mentioned IOBs and for one of the pins, the tool is using the internal FFs in the IOB while in the other it's using only an input buffer and that feeds a FF in another slice. Ofcourse removing the pin placement constraint fixes the problem but that is something that cannot be done for the time being. I wonder if somebody can help me figure out what's going on. I'm using ISE 9.1.03i with Spartan 3 Thank you.Article: 118494
Hello,
Thank you for giving me such a complete description; this helps me to
provide a complete answer. I believe you have two options; hopefully one of
these will work for you. These suggestions are based on iMPACT 9.1i Service
Pack 3.
1. You can use what is called Direct SPI programming. This is an iMPACT
mode where the four JTAG signals from our download cable are re-purposed to
work as the four SPI signals. To make this work, you must assert PROG# to
the FPGA, and then connect the {TMS, TDI, TDO, TCK} from the download cable
to the {CS#, SDI, SDO, SCK} of the SPI device on the board. You also need
to ensure that no other SPI devices sharing SDI, SDO, SCK will be driving
data out. This works even if the SPI device isn't connected to the FPGA at
all.
2. You can use what is called Indirect SPI programming. This is an iMPACT
mode where a "JTAG to SPI bridge" is first downloaded to the FPGA by JTAG,
and then iMPACT sends more data via JTAG user instructions that is used to
program an attached SPI device. In this case, the SPI device must be
connected to the FPGA's configuration port (i.e. a specific connectivity is
required, like that shown in XAPP445). This won't work if the SPI device is
connected to the FPGA using "randomly selected" general purpose I/O pins.
Hope this helps,
Eric
"Sven" <sven@is.com> wrote in message
news:46319d05$0$90269$14726298@news.sunsite.dk...
> It is my own design. The SPI flash is connected as in Xilinx XPAPP445 page
> 6 with the JTAG connected to the FPGA. But then I had to solder an extra
> connection as on page 11 to be able to program the SPI flash using DOS
> program xspi.exe.
>
> I don't want to redesign the PCB. So I hope it is programmable direct via
> the JTAG connector (I don't want to use the DOS-program).
>
> "Eric Crabill" <eric.crabill@xilinx.com> wrote in message
> news:f0qrhe$hgd1@cnn.xsj.xilinx.com...
>> Hi,
>>
>> The ISE iMPACT 9.1i does offer some expanded capability in this regard.
>> You didn't specify if your "system" is the Spartan-3E Starter Kit or if
>> it's another prototype/development board, or something of your own
>> design. If you clarify what you are working with I can then attempt to
>> describe your options.
>>
>> Thanks,
>> Eric
>>
>> "Sven" <sven@is.com> wrote in message
>> news:463077c7$0$90273$14726298@news.sunsite.dk...
>>>I have a system with a Spartan-3E with an SPI flash. I have been using
>>>the xspi.exe DOS program to configure the SPI flash. But now I'm
>>>wondering if the new ISE IMPACT 9.1 or later is able to configure the SPI
>>>flash though JTAG?
>>>
>>> I saw in XAPP974 for the Spartan-3A that it was possible at least for
>>> that device. But is the same possible for Spartan-3E?
Article: 118495As a sample here is some code. To be clear: I am not looking for alternate ways to code the following always block; I would like to know a way to access the power on reset from verilog. The block is just a simple example of where a reset might be used. I am aware that flip flops in an fpga get initialized globally upon power up. reg faultReg3; always @ (posedge slow_clk) if (reset) faultReg3 <= 0; else if (fault3) faultReg3 <= 1; else faultReg3 <= faultReg3;Article: 118496
"MNiegl" <Michael.Niegl@cern.ch> wrote in message news:1177698983.194188.262100@o40g2000prh.googlegroups.com... > On Apr 27, 8:22 pm, Austin Lesea <aus...@xilinx.com> wrote: > > MNiegl, > > > > Well, it seems that if you are doing everything right, and it worked > > last time at 160 MHz, it has no excuse but to work this time. > > > > When I am faced with these kinds of problems, I go back and check > > absolutely everything: it is likely the mistake is right there in front > > of you, and you are not seeing it. > > > > Have you looked at the DCM in FPGA Editor? Sometimes you immediately > > see that the code you wrote is doing exactly what it is supposed to (and > > not what you want). > > > > Peter is fond of saying, "when your car dies on the road, do you first > > check to see if the spark plug gap is correct? No, you check the most > > likely cause - are you out of gas..." > > > > Austin > > > > > Hi everyone, > > Hi Austin, > > Actually, at the moment I'm heavily banking on my own stupidity and > hope that it's only one small mistake I just can't find. > Until now I only checked the DCM locations in FPGA Editor, I'll look > at that some more intensively. > And I love that quote from Peter, it's so true but sometimes so hard > to obey. > > Cheers, > Michael Michael, Do you reset the second DCM after the first one has locked (a disturbed DCM doesn't get to it's senses without some help)? I agree that 2 DCMs in parallel would be better in this case, you only have to calculate the phase offset for the second one. Alvin.Article: 118497
On Apr 27, 3:47 pm, janb...@gmail.com wrote: > As a sample here is some code. To be clear: I am not looking > for alternate ways to code the following always block; I would > like to know a way to access the power on reset from verilog. > The block is just a simple example of where a reset might be > used. I am aware that flip flops in an fpga get initialized > globally upon power up. I believe you're looking for a way to poke at the GSR (global set/reset)? You didn't specify a device, but if you look in the library guide (doc/usenglish/books/manuals.pdf in the install dir), there are STARTUP_VIRTEX(|2|4) and STARTUP_SPARTAN(2|3) primitives that allow you to touch the GSR. Hope that helps.Article: 118498
janbeck@gmail.com wrote: > As a sample here is some code. To be clear: I am not looking for > alternate ways to code the following always block; I would like to > know a way to access the power on reset from verilog. The block is > just a simple example of where a reset might be used. I am aware that > flip flops in an fpga get initialized globally upon power up. > > reg faultReg3; > always @ (posedge slow_clk) > if (reset) faultReg3 <= 0; > else if (fault3) faultReg3 <= 1; > else faultReg3 <= faultReg3; > Have a wire in your top level named "reset" with no source. The synthesis tools should recognize this and replace "reset" with the GSR net. Instantiate the top level in your testbench, and in the testbench, do something like: assign uut.reset=(gsr_reset); Your testbench drives gsr_reset, maybe active for 100nS or so.Article: 118499
Peter, Thank you for your explanation. S. C. On Apr 27, 12:12 pm, Peter Alfke <p...@xilinx.com> wrote: > If you want to generate a precise average output frequency, you must > NOT clear the accunulator. > The unavoidable problem is then that the output periods vary, which is > called jitter. The max jitter is (almost) one whole clock period. > If you reset, you avoid the jitter, but you are not generating the > frequency you intended to generate. > Peter Alfke > > On Apr 27, 6:22 am, fp <fpga002...@yahoo.com> wrote: > > > > > Hi, > > > I am implementing a direct digital frequency synthesizer in FPGA. It > > follows the equation > > > Fo = N * Fs / (2^M) > > > The implementastion is done by an M-bit phase accumulator. My question > > is: if 2^M cannot be divided by N, should the accumulator be cleared > > to zero when wrapping around? > > > The VHDL code for automatical wrap-around is: > > > process(clk, reset) > > begin > > if reset='1' then > > q<=(others=>'0'); > > elsif rising_edge(clk) then > > q <= q + N; > > end if; > > end process; > > > The VHDL code for clear-to-zero wrap-around is: > > > process(clk, reset) > > varaible:tmp: ... > > begin > > tmp := q + N; > > if reset='1' then > > q<=(others=>'0'); > > elsif rising_edge(clk) then > > if (q > tmp) then --reach 2^M-1 and wrap around > > q <= (others=>'0') > > else > > q<= tmp; > > end if; > > end if; > > end process; > > > Which method is better ane why? Thanks in advance. > > > S. C.- Hide quoted text - > > - Show quoted text -
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