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mk <kal*@dspia.*comdelete> wrote: > On Tue, 24 Jul 2007 13:25:33 -0700, Chris Carlen > <crcarleRemoveThis@BOGUSsandia.gov> wrote: > >Petter Gustad wrote: > >> Chris Carlen <crcarleRemoveThis@BOGUSsandia.gov> writes: > >> > >>>Is there something wrong with my .vcd file, or Gtkwave? > > > >Thanks for the reply. > > > >> Did you try to: > >> > >> click on the + in the SST window > > > >What is the SST window? Do you mean the zoom-in? > Let's get some layout decided. At the top left there is a window which > says "VCD loaded succesfully[12] facilities..." right? You're also > seeing a window which has a title "Signals" and the content "Time" at > this point from what you're describing. Now below "VCD loaded ..." > window and to the left of "Signals" window, you should see a window > which has SST in its title with a '+' to the left of SST string. If > you see this click on the '+' and you should see your hierarchy. If > you don't see the SST window, it's possible that your GTK+ setup is > broken and you don't the right GTK+ installed. Another option might be Dinotrace... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 122276
Hi, You can actually add more lmb_bram_if_cntlr to the same lmb bus. This allows you to create more BRAMs on the same LMB bus. But it might have an impact on the maximum clock frequency since the BRAM outputs will be muxed in the LMB bus before reaching MicroBlaze. Göran Bilski "mfgunes" <mfgunes@yahoo.com> wrote in message news:AYadnT0D4es-ZjvbRVn_vw@giganews.com... > These are very precious information:)Thank you very much > > Fatih GunesArticle: 122277
Ulrich Bangert <df6jb@ulrich-bangert.de> wrote: > Eric, > although it is a Germany based company > http://www.siphec.com/ > may be worthwhile to have a look at And also the Zefant boards, especially the Zefant Nano: http://www.zefant.de/en/products/index.php -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 122278
Would anyone here know the history of pin B3 on the pci express connector? The latest PCISIG document shows it as +12V with no change bar associated with it. However I have found reference designs with it labelled as reserved. I can put a zero ohm link on it for development but sooner or later I have to work out what is compatible with all motherboards out there. regards ColinArticle: 122279
I have a set of verilog files that uses `defines. The same `define is applied to each file to select which code to use. Is there a way to setup Xilinx ISE so that when processing all verilog files it assumes that a certain `define has been defined ?Article: 122280
Stef <stef33d@yahooI-N-V-A-L-I-D.com.invalid> wrote: >Hi all, > >For a new project we will need an FPGA and need to select one, so the >question is: Altera or Xilinx? > >The designs needs a serial bus with automatic module enumeration (2 - 12 >changeable modules, not hotplug), access control (master slave probably), >buffers at each module (< 1kB), fixed timing, 10 - 40 Mbs. The master >module will need aditional buffering, ethernet and a processsor (probably >next to the fpga, not inside, but who knows). Slaves may or may not >require a (simple) processor. And in future there may be a need for >digital signal filters in some new slaves, but that could also be >implemented in a DSP. > >My guess is that if it wasn't for the buffers, it could probably fit >inside a CPLD. > >Any insights in what is the best FPGA for this (and other) application? >What is the major difference, are the differences, between Altera and >Xilinx? I'm under the impression that Altera parts are much easier to obtain in small quantities. Most 'hobbiest' projects seem to use Altera parts. Every time I buy Xilinx parts, I'll have to meet minimum order values so sometimes I must buy more devices than I actually need. Also if you really want to push an FPGA to its limits (space/speed) it is almost impossible to write FPGA independant code. So whatever you choose, you'll probably get stuck to it because changing vendors will require re-learning the quirks, tricks and basic fpga elements. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 122281
Andrea05 ha escrito:
> Is it possible in to define something like Xint32 but for 64bit?
I successfully use the following in EDK for PPC405:
typedef unsigned long long ulong64;
typedef signed long long slong64;
Regards,
Marc
Article: 122282Chris Carlen <crcarleRemoveThis@BOGUSsandia.gov> writes: > Interesting. Windows or Linux? Perhaps I will test a Windows version... Linux. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 122283
Dear Group,
I have a xilinx xc9536 , a 22 bit counter, and a 5 bit counter.
The 22 bit counter is used as a 48mhz clock divider for the
other 5 bit counter, hence bit 22 is used as humanly visible
clock. The counter stops when it reaches 11111.
The problem I am having is that when I apply my digital
multi meter to the pins of the counter to check if the count
has finished, then the counter seems to suddenly start
counting again. I also noticed that if before applying the
multimeter I disconnect the oscillator from the chip this will
not happen, so it seems the oscillator is making the design
unstable. Any ideas?
Also, as a beginner, which book do I need to understand
the tricks and quirks of xc9536 high speed design. Should
I be designing on a behavioural level, or should I use low
level?
My clock code is as follows
reg [21:0] nn;
assign cdiv= nn[21];
always @(posedge c0)
nn=nn+1;
my other clock goes like this
always @(posedge clock or posedge reset1)
begin
if (reset1)
aa <= 0;
else aa <= aa + 1;
end
The clocks are physically connected from external pins with a wire.
For the oscillator I use gck1.
Many thanks.
Article: 122284Hello, I am trying to import xmp file to my ise project.But i facing with this error on ise.Could you help me to solve this problem?Article: 122285
> The problem I am having is that when I apply my digital > multi meter to the pins of the counter to check if the count > has finished, then the counter seems to suddenly start > counting again. I also noticed that if before applying the 48 MHz ? With a multimeter ? Just solder a LED instead... or put a resistor at the end of your probe... resistor scope probe is THE low-tech low-cost "but it works!" way for high speed probing ;) A few possible causes : - you're wearing wool or something and generate enough static electricity to zap the circuits ; ground yourself properly before it costs you a replacement board - the parasitic cap of the probe is enough to cause mayhem, ringing, etc > multimeter I disconnect the oscillator from the chip this will > not happen, so it seems the oscillator is making the design > unstable. Any ideas? Well, without clock, all synchronous logic is on blind-deaf mode, and you used synchronous logic for your counter, so...Article: 122286
Hello, I am trying to import xmp file to my ise project.But i am facing with this error. ERROR:NgdBuild:927 - Failed to process BMM file edkBmmFile.bmm Best wishes, Fatih GunesArticle: 122287
Hi, I was wondering if anyone has ever use FPGA to communicate with another board that use PC/104 plus bus as the interface? To give a better view, I have one firewire board that uses a PCI-to-1394 host chip and another board that has an FPGA on it. I would like to control the firewire by using the FPGA. Does anyone has any suggestion on how to do this? I've tried using Xilinx PCi IPCore but did not work. I was wondering if I might need to use OPB bridge instead. I am open to any suggestion. Cheers!Article: 122288
Dear User, > 48 MHz ? With a multimeter ? > > Just solder a LED instead... or put a resistor at the end of your > probe... resistor scope probe is THE low-tech low-cost "but it works!" way > for high speed probing ;) > I do use a led, and this is why I divide the clock with 22 bits, so I can actually see the led flashing with different speeds on different counter pins. > A few possible causes : > > - you're wearing wool or something and generate enough static electricity > to zap the circuits ; ground yourself properly before it costs you a > replacement board > - the parasitic cap of the probe is enough to cause mayhem, ringing, etc > > > multimeter I disconnect the oscillator from the chip this will > > not happen, so it seems the oscillator is making the design > > unstable. Any ideas? > > Well, without clock, all synchronous logic is on blind-deaf mode, and you > used synchronous logic for your counter, so... Yes, this is silly of me, of course without a clock it cannot move. I was just wondering if there were any special checks I should make because I am using 50mhz. I think I can use a PIC to simulate a slower clock, I'll try that. And I forgot to mention as well that I have a "done" pin, which goes high when counter reaches "11111". Again, if I touch that pin with a led it will start counting again. This register actually controlls if the clock is multiplexed into the divider counter, when done=1 it stops the oscillator from reaching the divider. Clearing it would cause the counter to continue. Maybe when I touch the "done" pin with a led it acts as a momentary short ground. I can't think why that would be, my led is very low current, it is limitted with a relatively large 10K. I also have some other inputs, which once the clock is on 11111 should not make any difference, but again if I touch them with a led, or even just leave them floating, the counter starts to count again.Article: 122289
> I was just wondering if there were any special checks I should make > because I am using 50mhz. I think I can use a PIC to simulate a slower > clock, I'll try that. I hate to ask the obvious - but have you simulated the design at this clock rate? I haven't used the xc95xx stuff but certainly when I use a Spartan, simulation is the key to making a deisgn that does what I want it - and if it works, it narrows any problems to the hardware.Article: 122290
On Wed, 25 Jul 2007 02:00:39 -0700, colin <colin_toogood@yahoo.com> wrote: >Would anyone here know the history of pin B3 on the pci express >connector? > >The latest PCISIG document shows it as +12V with no change bar >associated with it. However I have found reference designs with it >labelled as reserved. I can put a zero ohm link on it for development >but sooner or later I have to work out what is compatible with all >motherboards out there. The 1.0 electromechanical spec (from April 2003) shows it as reserved; it was changed in the 1.1 spec (March 2005) to +12V. None of the other reserved pins were changed. I would just connect it directly to your other +12V pins. EvanArticle: 122291
On Wed, 25 Jul 2007 02:10:00 -0700, raphfrk <raphfrk@netscape.net>
wrote:
>I have a set of verilog files that uses `defines. The same `define is
>applied to each file to select which code to use.
>
>Is there a way to setup Xilinx ISE so that when processing all verilog
>files it assumes that a certain `define has been defined ?
vlogcomp has a '-d' option:
evan 63 > vlogcomp
Release - ISE Simulator Vlogcomp I.31
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
...
Usage: vlogcomp {options}
...
-d <macro> Define <macro>; The format of the <macro>
argument is <name>[=<val>] where <name> is
the name of the macro, and <val> is an
optional
value for the macro
Evan
Article: 122292On Tue, 24 Jul 2007 08:25:19 -0700, austin <austin@xilinx.com> wrote: >Paul, > >Bonjour, > >Il est meilleur si vous ouvrez un 'web case': > >http://www.xilinx.com/support/clearexpress/websupport.htm > >Vous recevrez une réponse beaucoup plus rapidement... > >Austin Apparently not when the Webcase system is down for maintenance. ------------------------------------------------------------------------------------------------------------------- To: brian@shapes.demon.co.uk Subject: Case 694071 has been registered with Xilinx Application Support From: Xilinx Technical Support <swssup@Xilinx.com> Date: Thu, 19 Jul 2007 12:24:18 -0700 (PDT) ------------------------------------------------------------------------------------------------------------------- No further correspondence as of 1pm UTC 25 July. - BrianArticle: 122293
Tonico wrote: > Dear Group, > > I have a xilinx xc9536 , a 22 bit counter, and a 5 bit counter. > The 22 bit counter is used as a 48mhz clock divider for the > other 5 bit counter, hence bit 22 is used as humanly visible > clock. The counter stops when it reaches 11111. > The problem I am having is that when I apply my digital > multi meter to the pins of the counter to check if the count > has finished, then the counter seems to suddenly start > counting again. I also noticed that if before applying the > multimeter I disconnect the oscillator from the chip this will > not happen, so it seems the oscillator is making the design > unstable. Any ideas? <snip> Do you use bypass capacitors from power to ground?Article: 122294
I cannot find any reference to powerPC cores in any of the Virtex-5 datasheets. The only reference to PowerPC in those documents is that PowerPC is a trademark of IBM. Does anyone know if Xilinx stopped including PowerPC cores in virtex-5 and why? ThanksArticle: 122295
Marc, Sorry for the delay. The training pattern is part of the protocol requirement. At 400Mbps, the clock will be in the center of the data window and there will be start of frame signal to do the frame alignment. When we switch from 400 to 3200Mbps then we may need to do the bit alignment and possibily packet alignment. Thus when we switch from 400 to 3200 we will need some training sequecne to do the bit and packet alignment. We will not be running 8b/10b encoding on this. I think that 400Mbps data rate oversampling can be supported in the fabric by sending each bit 8 times. But if the GTP has a way to do this then that will be more desirable. I read that it can support 5x oversampling but I am looking for 8x oversampling to get down to 400Mbps. With 5x oversampling it will be 3200/5 = 640 Mbps. Thanks. EddieArticle: 122296
On 25 Jul, 13:35, Evan Lavelle <nos...@nospam.com> wrote: > On Wed, 25 Jul 2007 02:00:39 -0700, colin <colin_toog...@yahoo.com> > wrote: > > >Would anyone here know the history of pin B3 on the pci express > >connector? > > >The latest PCISIG document shows it as +12V with no change bar > >associated with it. However I have found reference designs with it > >labelled as reserved. I can put a zero ohm link on it for development > >but sooner or later I have to work out what is compatible with all > >motherboards out there. > > The 1.0 electromechanical spec (from April 2003) shows it as reserved; > it was changed in the 1.1 spec (March 2005) to +12V. None of the other > reserved pins were changed. I would just connect it directly to your > other +12V pins. > > Evan Evan Many thanks for this info. I allways feel silly asking this sort of question but I could only find version 2.0 on the PCISIG website. Regards ColinArticle: 122297
On 25 Jul., 15:14, janb...@gmail.com wrote: > I cannot find any reference to powerPC cores in any of the Virtex-5 > datasheets. The only reference to PowerPC in those documents is that > PowerPC is a trademark of IBM. > > Does anyone know if Xilinx stopped including PowerPC cores in virtex-5 > and why? > > Thanks V5-FX will include PPC440 from AMC (IBM did sell PPC4xx to AMC) but the FX introduction is delaying (about 1 year)... you just have to wait. AnttiArticle: 122298
Nico Coesel wrote:
> if you really want to push an FPGA to its limits (space/speed) it
> is almost impossible to write FPGA independant code. So whatever you
> choose, you'll probably get stuck to it because changing vendors will
> require re-learning the quirks, tricks and basic fpga elements.
On the other side of the coin,
it is easy to write FPGA independent code if
I'm not near the limits and I study
the synthesis templates and learn some verilog or vhdl.
-- Mike Treseler
Article: 122299
On Jul 25, 5:30 am, <Tonico> wrote:
> Dear Group,
>
> I have a xilinx xc9536 , a 22 bit counter, and a 5 bit counter.
> The 22 bit counter is used as a 48mhz clock divider for the
> other 5 bit counter, hence bit 22 is used as humanly visible
> clock. The counter stops when it reaches 11111.
> The problem I am having is that when I apply my digital
> multi meter to the pins of the counter to check if the count
> has finished, then the counter seems to suddenly start
> counting again. I also noticed that if before applying the
> multimeter I disconnect the oscillator from the chip this will
> not happen, so it seems the oscillator is making the design
> unstable. Any ideas?
> Also, as a beginner, which book do I need to understand
> the tricks and quirks of xc9536 high speed design. Should
> I be designing on a behavioural level, or should I use low
> level?
>
> My clock code is as follows
>
> reg [21:0] nn;
> assign cdiv= nn[21];
> always @(posedge c0)
> nn=nn+1;
>
> my other clock goes like this
>
> always @(posedge clock or posedge reset1)
> begin
> if (reset1)
> aa <= 0;
> else aa <= aa + 1;
> end
>
> The clocks are physically connected from external pins with a wire.
> For the oscillator I use gck1.
>
> Many thanks.
I don't quite understand Verilog, but I don't see that the output of
your 22-bit counter has any affect on your 5-bit counter. Shouldn't
you have something like:
if cdiv = 1
aa <= aa + 1;
-Dave Pollum
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