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I don't know that my fpga is capable (spartan 3e 100k), but I thought I might like to try to do ethernet first. I remember finding a tutorial weeks ago but forgot to bookmark it, where the instructions had you hook up two io pins directly to an ethernet cable, and you could hardcode an IP address into the chip and ping it. Does anyone know of any like this, or even of the one I speak? (Might even have been verilog, I forget). Also, at the risk of sounding stupid, can an fpga hook up directly to ethernet? Supposing it is clocked at the right speed, the only consideration is the voltage of utp/ethernet, right? What other sort of hardware would I need to make all that work? Is it anything I can salvage off an old nic? Thanks in advance, John O.Article: 122326
austin wrote: > The silicon for the FX is back, and in house, so we are very very busy > with Verification and Characterization (V&C). Contact your FAE, disti, > or rep, for details. Right now we have many units in ovens at 100C (and > freezers at -40C) running Quake, Linux, etc. to shake out all the bugs. Will there be a Quake reference design available for download? :) SCNR, Sean -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 122327
Hi, all. Is it known to be possible to create a Microblaze system without the OPB? For example, say I have 1 MicroBlaze with 16KB of d&i BRAM, but I don't necessarily need the off-chip SDRAM or UART (or any OPB slave peripheral at all), so I don't include the OPB. And say it's part of a larger network to justify not needing the OPB for any peripherals. Currently, my 8.2 version has an issue with the BRAM when I don't include the OPB, and gives me an error (ERROR:Mablib:482). I was wondering if this is a problem with my particular system, or if it's a universal requirement for MicroBlaze projects to include at least one OPB slave. Or if it's a legitimate bug. Thanks! ----JD----Article: 122328
pbFJKD@ludd.invalid writes: > Xilinx (and Actel?) have free linux version of their programming tool. > Which Altera doesn't. You can download the Altera Quartus II Programmer for free. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 122329
Hello, I was working on a video font which I initially did as a 2 dimensional array of std_logic_vectors, one dimension for the bit output, and the other for the character and row selection. I suppose 3 dimensions may have also been an option. The simulation ran fine. The synthesis, however, took a long time, and I discovered that the tool (I still use ISE7.1) had synthesized the font in slices rather than a BRAM, which I originally intended. I vaguely remember reading that the synthesis tool will not synthesize multidimensional arrays into BRAM. Is this correct? In the case of my font, I was able to convert it easily into a single dimensional array of std_logic but I am concerned that in the future that may not be a clean looking VHDL solution. Thanks, Brad Smallridge AiVisionArticle: 122330
JD Newcomb wrote: > Hi, all. > > Is it known to be possible to create a Microblaze system without the > OPB? > > For example, say I have 1 MicroBlaze with 16KB of d&i BRAM, but I > don't necessarily need the off-chip SDRAM or UART (or any OPB slave > peripheral at all), so I don't include the OPB. And say it's part of a > larger network to justify not needing the OPB for any peripherals. > > Currently, my 8.2 version has an issue with the BRAM when I don't > include the OPB, and gives me an error (ERROR:Mablib:482). I was > wondering if this is a problem with my particular system, or if it's a > universal requirement for MicroBlaze projects to include at least one > OPB slave. Or if it's a legitimate bug. > It should be possible to create such a system. I've seen projects that only have MicroBlaze + LMB + a peripheral on FSL. -SivaArticle: 122331
Brad Smallridge wrote:
> I vaguely remember reading that the synthesis
> tool will not synthesize multidimensional arrays
> into BRAM. Is this correct?
The basic requirement to infer a bram is
a clocked process with no reset.
In other words the inference failure
may or may not have to do with array
dimensions. A simple array like this
does work as expected:
ram_access : process (clk) is
begin
if rising_edge(clk) then
if we = '1' then
mem(to_integer(push_tail_ptr)) <= (data_i);
end if;
data_q <= mem(to_integer(pop_head_ptr));
end if;
end process ram_access;
If the array type *is* the problem, I would
write a function to collect the required
ram address(es).
-- Mike Treseler
Article: 122332Petter Gustad wrote: > pbFJKD@ludd.invalid writes: >> Xilinx (and Actel?) have free *linux* version of their programming tool. >> Which Altera doesn't. > You can download the Altera Quartus II Programmer for free. The download page says: "Quartus® II Stand-Alone Programmer Version 7.1 Service Pack 1 Windows XP and Windows 2000 (Note: Solaris, Linux, and HP-UX are not supported)" -- Mike TreselerArticle: 122333
Two comments: I really hope that you use a series resistor to limit the current. It is not good to rely on the output characteritic of the CPLD to limit the current, and to dissipate the excess power. Most LEDs are driven in the current sink mode (LED+R connected between Vcc and the device output. This habit started with TTL circuts, where the output could sink far more current than it could source. Also, the Voh was poorly defined, being two diode drops below Vcc. And it still is, witness the silly 2.4 V specification. I would recomment using current sink. Perhaps you have to turn the output polarity around. Remember: there is nothing sacred about active High. It's all in the mind of the beholder... Peter Alfke ================Article: 122334
On Jul 24, 6:01 pm, KF4KJQ <bg...@mit.edu> wrote: > On Jul 24, 11:24 am, "jacob...@xilinx.com" <naude.j...@gmail.com> > wrote: > > > > > On Jul 23, 9:56 pm, bgelb.mit....@gmail.com wrote: > > > > Hello - > > > > I am trying to use the Xilinx MIG version 1.72 to generate a working > > > interface for the DDR2 memory on the Xilinx ML501 eval board. I am > > > having a bit of trouble. > > > > I am able to simulate the controller and testbench just fine using > > > ModelSim, but seem to be having issues getting it to work in hardware. > > > At the moment, I am simply checking the output of the phy_init_done > > > signal, which does not go high at any point, which indicates a problem > > > to me. I have not yet been able to delve much deeper into where things > > > are getting stuck. > > > > I plan to use ChipScope to try to see what is going on, but I wonder > > > before I get too far, if anybody else has tried a similar > > > configuration? What experiences (good/bad) have people had with the > > > MIG and Virtex-5 DDR2 designs? It would make me feel better if > > > somebody out there had gotten it to work - it sounds like - from > > > reading this group at least, that there are no shortage of issues with > > > this stuff. > > > > Thanks, > > > Ben > > > Did you do a behavioral simulation? Do a post-PAR simulation and check > > if the initialization still completes. > > > Also did you change the controller to work with the ML501? The ML501 > > has a SODIMM device on it. Check the following link on information on > > how to change the controller to work with a SODIMM memory:http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountry... > > > Jaco > > After my post-PAR simulation checked out I decided to check my sanity > and try loading my bitfile on another eval board. It worked! (or at > least phy_init_done gets asserted). Then I reseated the DIMM on the > board I'd been using and it works too. So I guess things are solved > for the moment. > > Thanks for the help. > > Ben Came across a weird problem - I realized that when I was generating the bit file for the ML501 (which seemed to function correctly) I still had the SIM_ONLY parameter (which disables the 200us start-up delay) set to 1. Things had been working fine anyway, but I decided to set it to the proper value of 0. When I do this, the phy_init_done line still gets asserted, but the error line from the synthesizable testbench also is asserted. Disabling the 200us delay makes the signal on the error line disappear. This doesn't make a whole lot of sense to me... I guess I can run the MIG core with the SIM_ONLY flag forced to 1 since it seems to work, but its a little unsettling to say the least. Any ideas? Thanks, BenArticle: 122335
On Jul 24, 5:48 pm, Stef <stef...@yahooI-N-V-A-L-I-D.com.invalid> wrote: > In comp.arch.fpga, > > Matthew Hicks <mdhic...@uiuc.edu> wrote: > > For low-end projects that need things like ethernet or other high-end macros > > I would look at Lattice. I haven't had the opportunity to use any of their > > hardware or software but it seems that they offer more to lower-end customers. > > Lattice! How could I forget? Used their CPLDs (isp1032?) some ten years ago. > It indeed looks like they have some nice devices and tools seem comparable > although the free version is only for evaluation (no sim?). Payed tools seem > a bit cheaper than actel/xilinx though. > > Any experiences with device and tools here? > > -- > Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) I've used the Lattice ECP and ECP2 series, although I haven't had the pleasure of using ECM2/M yet (the ones with the high-speed serial I/O). We bought the tools for a few hundred dollars. The front-end for synthesis is Synplify or Precision (your choice, they're both bundled in). If you're not used to anyone elses user interface yet there's probably no reason to pick Lattice vs Xilinx vs Altera. Many of those posting here gave up on the GUI front-ends long ago. That being said, a lot of Lattice flow is similar to Xilinx, mostly because the tools both originated at NeoCad. However they're just different enough that you'll need to learn the quirks, especially if you need to push the limits of the part. On the back-end, I'd say Xilinx is well ahead on the mapping and place&route, but again you can get good performance from Lattice if you know what to tweak and are not afraid to use multipass place and route. I haven't installed Lattice version 7 tools yet, but there's talk of improvement on the back end for that release. Both Lattice and Xilinx bundle branded versions of ModelSim with the paid tools. It may just be my imagination but it seems that the Xilinx version runs slower than the Lattice version. I think the Xilinx version inserts waits if your design exceeds a certain number of statements or non-Xilinx "leafs". I haven't run into that wall on the Lattice version, but I'm not sure if it's due to differences in the license or in the size of my designs. If you're going to do large designs and long simulations or if you do mixed language designs, I'd suggest getting a license for ModelSim PE. Lattice surprised a lot of people by releasing the low-cost ECP2/M series when Xilinx and Altera only offered similar features in their higher end products. That is no longer the case, and I would expect both Xilinx and Altera to beef up their low-cost offerings if they see erosion in their customer base due to Lattice. For many designs also realize that the I/O options are becoming the limiting design criteria rather than the FPGA fabric. Lattice parts have some nice features for using DDR I/O, but again you need to look at the quirks to see if it does what you want for your design. HTH, GaborArticle: 122336
Tonico wrote: > Another problem (less serious), while programming the device, > if I leave the oscillator connected the programmer fails, whereas > if I revice the oscillator it works. (funny?) > Ummm, this STRONGLY suggests a noisy power supply, insufficient bypass caps, too much lead/trace inductance on that one sole cap, or something like that. > Another clue, I use the power supply from my usb port as I haven't > got a dedicated 5V supply, measuring the voltage near the device > reads 4.75v and current through device is 70mA without oscillator > and 85mA with oscillator. Something horrible I just found out is that the current consumption equation in the XC95xx datasheets are wildly wrong. It depends on how much combinatorial logic you have implemented in the macrocells, I just did a very dense CPLD. Xilinx has admitted that the current consumption can be 2-3 times higher than that equation gives! With the macrocells in high-power mode, I was getting about 112 mA on a 9536! With all of them in low-power (my clock is 10 MHz, so I can get away with that) it drops to "ONLY" 72 mA, while the equation gives 30! If the operation of FF and logic on chip prevents programming, then it is almost certain that either the switching is creating noise due to insufficient capacitance, or the increased current draw is pulling the supply voltage too low. I suspect the former, the voltage tolerance seems to be pretty wide. JonArticle: 122337
On Jul 25, 4:22 pm, Siva Velusamy <siva.velus...@xilinx.com> wrote: > JD Newcomb wrote: > > Hi, all. > > > Is it known to be possible to create a Microblaze system without the > > OPB? > > > For example, say I have 1 MicroBlaze with 16KB of d&i BRAM, but I > > don't necessarily need the off-chip SDRAM or UART (or any OPB slave > > peripheral at all), so I don't include the OPB. And say it's part of a > > larger network to justify not needing the OPB for any peripherals. > > > Currently, my 8.2 version has an issue with the BRAM when I don't > > include the OPB, and gives me an error (ERROR:Mablib:482). I was > > wondering if this is a problem with my particular system, or if it's a > > universal requirement for MicroBlaze projects to include at least one > > OPB slave. Or if it's a legitimate bug. > > It should be possible to create such a system. I've seen projects that > only have MicroBlaze + LMB + a peripheral on FSL. > > -Siva You don't need an OPB connection for the MicroBlaze to operate properly. It's possible that the MicroBlaze can be connected only via LMB (or XCL) and FSL. One possible system is using multiple MicroBlazes as stream processors where data is pushed in via the FSL to one MicroBlaze. This MB then performs some data calculation/ manipulation/etc then passes it to another MB via the FSL. This MB could perform data repackaging, DMA chain creation, etc and then push the data to another piece of hardware (internal or external), once again via FSL.Article: 122338
Thank you all for your input. To sum it up: Altera and Xilinx are indeed the major brands to look at. Lattice has some nice stuff, but is smaller and does not support VHDL (at least not in the low-end tools). There are no real advantages of one over the other (maybe there is for some specific designs). So the choice should be made based on the less technical stuff like distributors, support, prices. I've asked purchasing to get some indication qoutes of the low-end devices, eval kits and tools from both. The Xilinx distributor got back the next day, still waiting for Altera. :-( Xilinx seems to have a bit nicer eval kits, especially if we need ethernet. This is not available on the low-end Altera eval kits. On the other hand, the sales rep for our altera distributor used to come in for a cup af coffee on a regular basis in the old days, and he's still there. As my most current and extensive experience is with Xilinx (CPLD), I am currently leaning to Xilinx, but no disicion yet. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)Article: 122339
"Gabor" <gabor@alacron.com> wrote in message news:1185389927.265918.274300@o61g2000hsh.googlegroups.com... > > O.K. I went to NXP.com and found a link to this page: > > http://www.semiconductors.philips.com/buses/i2c/licensing/index.html > > which pretty much says they're not charging royalties for licenses > although it doesn't go so far as to say you don't need a license... > > There's no mention of high-speed I2C licensing. Is this under a > different patent holder (i.e. not Philips)? I'm not sure. I only know the caveats that were communicated to us about the 400 kHz and 10-bit address limits.Article: 122340
Tonico wrote: > Dear Group, > > I am using xilinx ise8.2i , xc9536, and I have some questions > > One of the documentation files leds.pdf exaplains how much > current will be available when the anode is connected to 5V > and the cathode to the device. However, my situation is > reverse, I want to connect the cathode to 0V and the anode > to the device. Why is this not mentioned? CPLD's normally drive better to GND, than to Vcc, so that is why most designs use the Sinking Drive. You CAN source drive, but you get more voltage drop across the PLD In both cases, you use a series resistor to define the LED current. -jgArticle: 122341
Mike Treseler <mike_treseler@comcast.net> writes: > Petter Gustad wrote: > > pbFJKD@ludd.invalid writes: > >> Xilinx (and Actel?) have free *linux* version of their programming tool. > >> Which Altera doesn't. > > > You can download the Altera Quartus II Programmer for free. > > The download page says: > > "Quartus® II Stand-Alone Programmer Version 7.1 Service Pack 1 > Windows XP and Windows 2000 > (Note: Solaris, Linux, and HP-UX are not supported)" Sorry, I missed the Linux part. As a Linux user I should have noticed... Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 122342
I would like to know how to have easy access to the internal state machines and registers in its ennitrity while doing the timing simulation. The timing simulation verilog output generated by the software removes the state machine bits and thus it becomes very difficult to debug the issues while doing the timing simulation. Any ideas will be great. Thanks. EddieArticle: 122343
Stef wrote:
> As my most current and extensive experience is with Xilinx (CPLD),
> I am currently leaning to Xilinx, but no disicion yet.
Consider running a known-good design through both
sets of tools and getting quotes from both vendors
for 5000 pieces of the most likely device for delivery one
year from now.
-- Mike Treseler
Article: 122344<Tonico> wrote in message news:46a72647$1_2@mk-nntp-2.news.uk.tiscali.com... > Dear Group, > > I have a xilinx xc9536 , a 22 bit counter, and a 5 bit counter. > The 22 bit counter is used as a 48mhz clock divider for the > other 5 bit counter, hence bit 22 is used as humanly visible > clock. The counter stops when it reaches 11111. > The problem I am having is that when I apply my digital > multi meter to the pins of the counter to check if the count > has finished, then the counter seems to suddenly start > counting again. I also noticed that if before applying the > multimeter I disconnect the oscillator from the chip this will > not happen, so it seems the oscillator is making the design > unstable. Any ideas? <snip> Are you using flying leads with a breadboard? PC layoud with solid ground planes? Even though you may be using a 5V device with a 5V oscillator, you may be getting severe overshoot and undershoot on the clock. If you have a long, flying lead, consider substituting a twisted pair with the clock and ground on the two wires from the oscillator to the CPLD's clock input. Adding a series resistor at the oscillator output around 100 ohms may make the destination clock look even prettier. You only have the one clock destination, correct? Please verify that you have some bulk capacitance (10uF or larger) somewhere on this side of the USB "power supply" entry to your circuit.Article: 122345
On Wed, 25 Jul 2007 21:35:39 +0200, John Oyler <john.m.oyler@gmail.com> wrote: > I don't know that my fpga is capable (spartan 3e 100k), but I thought > I might like to try to do ethernet first. I remember finding a > tutorial weeks ago but forgot to bookmark it, where the instructions > had you hook up two io pins directly to an ethernet cable, and you > could hardcode an IP address into the chip and ping it. Does anyone > know of any like this, or even of the one I speak? (Might even have > been verilog, I forget). Tutorial is there. http://www.fpga4fun.com/10BASE-T0.html > Also, at the risk of sounding stupid, can an fpga hook up directly to > ethernet? 10 Mbps, maybe, if you violate most of the ethernet spec ;) You'll most likely get a toy system, though. > Supposing it is clocked at the right speed, the only > consideration is the voltage of utp/ethernet, right? What other sort > of hardware would I need to make all that work? Is it anything I can > salvage off an old nic? If you just want to play and learn stuff, you could try putting in an Ethernet PHY. You won't be able to use anything from an old LAN board as those all use highly integrated PCI chipsets (unless very, very old). Or you could download the Ethernet MAC core at OpenCores.org and have a look. If you just want to send a few packets for messaging, though, and not high throughput data, an ethernet enabled microcontroller is a much better bet. I have an Ethernet + FPGA module in the works ; I have selected a complete and easy to use MAC+PHY chip from SMSC, the LAN9117.Article: 122346
Eddie H wrote:
> I would like to know how to have easy access to the internal state machines
> and registers in its ennitrity while doing the timing simulation.
> The timing simulation verilog output generated by the software removes
> the state machine bits and thus it becomes very difficult to debug
> the issues while doing the timing simulation.
>
> Any ideas will be great.
In that case, *this* idea will be great:
I would synchronize the design
and run static timing analysis
to verify Fmax. I would use
simulation only to verify function.
-- Mike Treseler
Article: 122347Stef wrote: > Thank you all for your input. To sum it up: > > Altera and Xilinx are indeed the major brands to look at. Lattice has > some nice stuff, but is smaller and does not support VHDL (at least > not in the low-end tools). Are you sure ? The web page states this : [Supported HDL languages include; VHDL, Verilog 1995, Verilog 2001.] and they release the Mico8/Mico32 in both Verilog and VHDL. You can download their Starter for free, and try a design. -jgArticle: 122348
Mike, Does this mean that I do not perform timing simulation and only perform functional simulation? Functional simulation will verify the function and I have successfully done that but when I perform the timing simulation then I am having some problems to check out the functionality. I do have period consntarints on the clocks and I am meeting this constraint. EddieArticle: 122349
On Jul 25, 2:50 pm, Stef <stef...@yahooI-N-V-A-L-I-D.com.invalid> wrote: > Thank you all for your input. To sum it up: > > Altera and Xilinx are indeed the major brands to look at. Lattice has > some nice stuff, but is smaller and does not support VHDL (at least > not in the low-end tools). > > There are no real advantages of one over the other (maybe there is for > some specific designs). > This really irks me...."no real advantages"... I will not get into a propaganda tirade, but rest assured that there are significant technical differences between the two competitors. I am of course biased, and much more familiar with the Xilinx devices and their special advantages. And -as promised- I will not elaborate them here. There are differences, for better or worse, between Obama and Clinton, between the US and Canada, between BMW and Mercedes, between Apple and Microsoft, and also between Xilinx and Altera. You may prefer one brand over the other, but don't call it a toss-up! We worked hard to make them different. It is only when you ignore all the interesting and important fine details that everything looks the same grey mush. "Once you have seen one lake or one mountain, you have seen then all. California is just like Ohio with some mountains and beaches thrown in!" Nonsense! Peter Alfke
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