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Messages from 122000

Article: 122000
Subject: Xilinx S3 Starterkit, how hot it is supposed to be?
From: Antti <Antti.Lukats@googlemail.com>
Date: Tue, 17 Jul 2007 04:21:54 -0700
Links: << >>  << T >>  << A >>
Hi

I just burnt my fingers trying to lift off the Xilinx Spartan 3A
Starterkit
the all corner with power supplies is extremly hot - I wonder if that
is
normal or not.

I already own 3 FPGA boards designed by Digilent with burned in Power
supplies
so I am little worried that I may get a 4th one into my collection of
"dead digilent garbage" :(

The board was powered maybe 3 minutes and FPGA was configured with
original bitstream
for the dataflash programming, and yes incoming power is 5V not 9

Any ideas? Should I be worry? The power supply IC are so tiny that it
is defenetly not possible
to mount any heat sink on them :(

Antti


Article: 122001
Subject: Unisim versus Virtex2 Xilinx Library
From: Pablo <pbantunez@gmail.com>
Date: Tue, 17 Jul 2007 04:29:56 -0700
Links: << >>  << T >>  << A >>
Hi,

  I have seen a piece of code in which there is elements such as FDP,
BUFG and DCM. This code is to get different clocks from internal
reference clock. I have simulated this but I cannot. These elements
uses virtex2.FDP, virtex2.BUFG, ... so library virtex2 is used. My
board is Virtex II Pro, so could I use this library?. I suppose that
yes.

My question is about unisim and virtex2. Are these libraries similar?.
Virtex2 is obsolete and now everyone use unisim.

Best Regards

Pablo


Article: 122002
Subject: Re: Xilinx System generator vs Simulink HDL Coder
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Tue, 17 Jul 2007 12:39:10 +0100
Links: << >>  << T >>  << A >>
richng01@gmail.com writes:

> Hi all,
> Anyone know the differences between Xilinx System Generator and
> Simulink HDL Coder?

About 10,000 UK pounds :-) Sysgen is fairly cheap, HDL coder is
expensive.

I've used sysgen, and you have to use a load of Xilinx blocks to do
everything.  Not having used it, I assume that HDL Coder is "standard"
Simulink blocks with bit widths on them, using the fixed-point toolbox
(which costs more money).

HTH!

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

Article: 122003
Subject: Sending large amount of data with lwIP...
From: Marco Albero <periket2000@ya.com>
Date: Tue, 17 Jul 2007 13:54:51 +0200
Links: << >>  << T >>  << A >>
Hello, I'm trying to send an image with lwIP, the problem is that I 
can't XD, y read the image from the CF card, so suposse it takes 10000 
bytes, but my sendbuf is only 8192, how can I send data larger than the 
send buffer. I've tried to do it with two pass but it doesn't work.

The code for a normal page (fits in 8192 bytes) is:

	CF_read( filename, destBuff, tam_max );

	ws->returnwebpageamttoackstill = sprintf( sendbuf, "%s%s\r\n%s", 
HTTP200OK, PNGHEADER, destBuffer);

	ws->returnwebpage = sendbuf;

	send_data( pcb, ws );

Thanks everybody.

Article: 122004
Subject: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
From: John_H <newsgroup@johnhandwork.com>
Date: Tue, 17 Jul 2007 13:07:49 GMT
Links: << >>  << T >>  << A >>
Eric Smith wrote:
> "John_H" <newsgroup@johnhandwork.com> writes:
>> My ohmmeter walked away at work, besides - I'd need an ohmmeter to check my 
>> ohmmeter.  Don't they have high impedance outputs even when the resistance 
>> measurement goes to the 0-20 ohm range?
> 
> No.

So every time I check for a connection (sub-ohm) you think I'm shorting 
the battery?

Article: 122005
Subject: Re: Xilinx S3 Starterkit, how hot it is supposed to be?
From: "Tim (one of many)" <tim@nooospam.roockyloogic.com>
Date: Tue, 17 Jul 2007 14:09:58 +0100
Links: << >>  << T >>  << A >>
Antti wrote:

> Any ideas? Should I be worry? The power supply IC are so tiny that it
> is defenetly not possible
> to mount any heat sink on them :(

What sort of regulator did they use? Current drawn?

Article: 122006
Subject: Re: Newbie's first FPGA board !
From: PFC <lists@peufeu.com>
Date: Tue, 17 Jul 2007 15:10:08 +0200
Links: << >>  << T >>  << A >>

>> Your schematic shows a JTAG header and an external programming interface
>> header for the ATMEL flash.  If you're suggesting that Impact will reach
>> out of the FPGA on the passive serial lines and program the flash there,
>> I don't know the tools like I thought I did.
>
> I don't know if Xilinx can do that, but there's an Altera megafunction
> called "Serial Flash Loader" (SFL) which can do that with the Quartus II
> programming tool.  That means you can have just one external header  
> (JTAG)
> and have access to do direct bitstream loads, signaltap and flash
> programming.
>
> (to the OP:  doesn't apply to you, obviously!)

	Actually, I possibly skrewed up ;) in my datasheet reading...
	XPS can load a parallel flash if your design contains an opb_emc memory  
controller though.
	
	So for safety I put a JTAG Platform Flash  to configure the FPGA. SPI  
flash will just store software (or maybe even not be populated).

	http://home.peufeu.com/nik/fpga/board_v03/schema.pdf

	I think I'll order the stuff at DigiKey tomorrow. Yes !!

	Have a nice day !

Article: 122007
Subject: Re: chipscope PLB IBA - how to get meaningful labels on signals?
From: Jeff Cunningham <jcc@sover.net>
Date: Tue, 17 Jul 2007 10:03:49 -0400
Links: << >>  << T >>  << A >>
adam.taylor@selex-sas.com wrote:
> On 17 Jul, 05:28, Jeff Cunningham <j...@sover.net> wrote:
>> I have been trying chipscope from within XPS 9.1.03i on a ML403. I can
>> connect up the ILA sucessfully and can capture and display signals. I
>> can also instantiate and build and run the PLB IBA core. But when I run
>> chipscope analyzer, it just displays DataPort[0]...DataPort[N]. Can
>> someone clue me in on how to get lables like "address bus", "data bus"
>> and various control signal names displayed when using the PLB IBA?
>>
>> thanks,
>> -Jeff
> 
> Jeff,
> 
> I know if you have used the chip scope core inserter you can import
> the project file (*.cdc) into chipscope analyser and the signal names
> will be imported into the analyser. I have not used the chip scope
> core generator in a long time but I beleive there is a similar option
> to "generate bus / signal name example File (*.cdc) " which you can
> modify to include the signal names as connected and then import it in
> the a similar way.
> 
> Hope this helps
> 
> Adam
> 

Thanks for replying Adam. I use chipscope directly within XPS, i.e. I 
just add the PLB IBA and ICON the design like any other IP core. I set 
the chipscope parameters, wire up blocks, then build it and download the 
bitstream all within XPS. Then I start the chipscope analyzer from 
outside of XPS and it finds the core and seems to work, except for no 
meaningful waveform names. I tried running the standalone versions of 
chipscope generator and inserter, but it's not clear how to get that 
into my xps framework. Since they supply the chipscope IP cores within 
XPS there must be a way to use them in that context?

-Jeff

Article: 122008
Subject: Re: Xilinx XC9536 current draw ?
From: lb.edc@telenet.be
Date: Tue, 17 Jul 2007 14:26:02 GMT
Links: << >>  << T >>  << A >>
On Tue, 17 Jul 2007 00:52:09 -0500, Jon Elson <elson@pico-systems.com>
wrote:

>Hello,
>
>I have been trying to figure out why the current draw of an 
>XC9536 (not -XL) chip is so high.  Xilinx has been of some help, 
>but can't explain why the current I'm seeing (now 70 - 95 mA) is 
>wildly higher than predicted by their formula in the data sheet. 
>  I have used these chips before in several products, although I 
>only used a small part of the available logic.  In this 
>application I am using practically all of the available logic 
>(all registers and all macrocells).  I have set the default to 
>all macrocells at low power, and enable feedback to macrocells 
>and I/O, and this has helped bring it down from 112 mA to
>70 - 95 mA (varies from chip to chip and with different configs).
>The chip is doing exactly the logic I have coded for it, I can 
>find no loads on any outputs, I have even made up a board with 
>only the CPLD on it to read the current accurately.  I have all 
>unused I/O pads set to use ground by default to avoid floating 
>inputs.
>
>I am using a 5 V chip here because the FET driver this feeds 
>signals to is a TTL-level device and the 3.3 V levels would 
>leave logic margins pretty thin.  I could use an XC9536XL, but 
>the current draw on those (by formula) is not much less than the 
>5 V 9536, so I can't assume much reduction there, and I'd need 
>an extra regulator.
>
>Does anybody have any experience with the 5 V 95xx line, and how 
>the data sheet formula compares to actual current consumption? 
>(Oh, the formula predicts about 30 mA current draw, practically 
>all static as the clock is 10 MHz.)  My results show it is all 
>static, if I stop the clock current drops by about 3 mA.  And, I 
>have no static loads on the outputs, just CMOS inputs to the FET 
>driver, so it has to be all static draw in the CPLD logic core. 
>  (When I erase the part, the current draw goes down to ~20 mA.)
>
>Thanks in advance for any experience with this,
>
>Jon

Jon,

Have you seen the design drawing lower current in another batch? Also,
you're saying you are using pretty much all of the device's resources.
Is this all registered? Are you using latches in the design? I ask
this because I have had similar problem in the past with a 128MC
design, consuming almost 300mA of current @5V. 
The main reason was a failure in the netlist generation, resulting in
all the flipflops behaving as a latch. Manually editing the netlist
resolved the issue.

Good luck,

Luc

Article: 122009
Subject: Re: Xilinx S3 Starterkit, how hot it is supposed to be?
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 17 Jul 2007 15:32:47 +0100
Links: << >>  << T >>  << A >>
"Antti" <Antti.Lukats@googlemail.com> wrote in message 
news:1184671314.268484.185600@i38g2000prf.googlegroups.com...
> Hi
>
> I just burnt my fingers trying to lift off the Xilinx Spartan 3A
> Starterkit
> the all corner with power supplies is extremly hot - I wonder if that
> is
> normal or not.
>
> Any ideas? Should I be worry? The power supply IC are so tiny that it
> is defenetly not possible
> to mount any heat sink on them :(
>
> Antti
>
Antti,

Which regulator gets hot? IC12, IC3 or IC5? All these ICs have thermal 
protection, so you shouldn't have to worry about this causing it to fail. 
They'll turn off if they get too hot.

However, that's no help to your burnt fingers, is it? I hope you learnt a 
lesson here. I notice that a lot of your work seems to be on the software 
side of the FPGA world. Complex and challenging it may be, but perhaps you 
should leave the real engineering (such as handling the boards) to us 
hardware guys whose fingers are so much more used to abuse than yours? ;-)

Cheers, Syms.

p.s. Maybe this would help?
http://www.amazon.com/Aveda-Hand-Relief-4-2-oz/dp/B000FAMUIU
I went into an Aveda store somewhere in silicon valley once and demanded 
this product. I half expected to be arrested, but apparently the UK meaning 
hasn't travelled the Atlantic yet. My mates back in the UK were delighted to 
have gifts of 'Hand Relief' for xmas! 



Article: 122010
Subject: BD
From: fazulu deen <fazulu.vlsi@gmail.com>
Date: Tue, 17 Jul 2007 07:34:04 -0700
Links: << >>  << T >>  << A >>
Hai,

I need to know how to generate buffer descriptor file?

regards,
fazal


Article: 122011
Subject: Re: BD
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 17 Jul 2007 15:42:23 +0100
Links: << >>  << T >>  << A >>
"fazulu deen" <fazulu.vlsi@gmail.com> wrote in message 
news:1184682844.113055.232750@g37g2000prf.googlegroups.com...
> Hai,
>
> I need to know how to generate buffer descriptor file?
>
> regards,
> fazal
>
Easy cut and paste the below into a file, and you're all set with 13 buffer 
descriptors.
HTH, Syms.

      1. an apparatus at the end of a railroad car, railroad track, etc., 
for absorbing shock during coupling, collisions, etc.
      2. any device, material, or apparatus used as a shield, cushion, or 
bumper, esp. on machinery.
      3. any intermediate or intervening shield or device reducing the 
danger of interaction between two machines, chemicals, electronic 
components, etc.
      4. a person or thing that shields and protects against annoyance, 
harm, hostile forces, etc., or that lessens the impact of a shock or 
reversal.
      5. any reserve moneys, negotiable securities, legal procedures, etc., 
that protect a person, organization, or country against financial ruin.
      6. buffer state.
     a nation lying between potentially hostile larger nations.7. Ecology. 
an animal population that becomes the prey of a predator that usually feeds 
on a different species.
      8. Computers. a storage device for temporarily holding data until the 
computer is ready to receive or process the data, as when a receiving unit 
has an operating speed lower than that of the unit feeding data to it.
      9. Electronics. a circuit with a single output activated by one or 
more of several inputs.
      10. Chemistry. a. any substance or mixture of compounds that, added to 
a solution, is capable of neutralizing both acids and bases without 
appreciably changing the original acidity or alkalinity of the solution.
            b. Also called buffer solution. a solution containing such a 
substance.

-verb (used with object) 11. Chemistry. to treat with a buffer.
      12. to cushion, shield, or protect.
      13. to lessen the adverse effect of; ease: The drug buffered his pain.



Article: 122012
Subject: Re: BD
From: "John_H" <newsgroup@johnhandwork.com>
Date: Tue, 17 Jul 2007 08:51:41 -0700
Links: << >>  << T >>  << A >>
"fazulu deen" <fazulu.vlsi@gmail.com> wrote in message 
news:1184682844.113055.232750@g37g2000prf.googlegroups.com...
> Hai,
>
> I need to know how to generate buffer descriptor file?
>
> regards,
> fazal

The question "I need to know something?" is usually accompanied by a 
surprised look, often before an exam.

Do you know what a buffer descriptor file is?
Do you know what it's used for.
I sure don't.

A register map, on the other hand, could be called a register description 
file or a port map and describes the details of the registers within a 
system typically hooked up to one bus (processor bus perhaps) and describes 
the controllability and observability of the design.

1) get a clue, 2) clue us in on your needs if they ARE needs that should be 
addressed by people who work regularly with FPGAs.

Ask a good question and you'll get actual answers.
- John_H 



Article: 122013
Subject: XC9572XL bus hold - Cant be disabled
From: Peter Wallace <pcw@karpy.com>
Date: Tue, 17 Jul 2007 09:37:19 -0700
Links: << >>  << T >>  << A >>
No matter what options I use, the bus hold circuits are enabled on the
inputs of a XC9572XL (same problem with 95144XL) in a design of ours. I've tried
ISE6.3 and WEBPack 9.1, no difference.  

The reason I want high impedance inputs is that they are used with a high
value series resistor (and clamp diodes) as part of a power MOSFET
out-of-saturation short circuit protection.

If anyone has experience with this or especially how to solve it I would
be very grateful...

Peter Wallace

Article: 122014
Subject: Actel. Libero. Synplify
From: dorama2@gmail.com
Date: Tue, 17 Jul 2007 16:44:26 -0000
Links: << >>  << T >>  << A >>
when I synthesize the FPGA (ProASIC PLUS) in Synplify of Libero I have
got a lot of warnings: "Unbound component (DFF or AND2...) mapped to
black box". It seems that don't recognize the basic components, =BFdo I
need any library?

thanks


Article: 122015
Subject: Re: Xilinx XC9536 current draw ?
From: Jon Elson <elson@pico-systems.com>
Date: Tue, 17 Jul 2007 11:57:11 -0500
Links: << >>  << T >>  << A >>
Jim Granville wrote:
> 
> So you are saying the device is 100% functional, when programmed ?
> How many devices have you checked ?
About 4-5.
> The symptoms suggest a shorted pin, or bad drive (not Vdd, or Vss)
No, I really don't think so.  I have gone over it very 
carefully, and also checked it by loading the same program into 
a chip on a different board that I have used before.  I just put 
the CPLD on that board, nothing else.
> you could try the same code, but with all outputs connected to an OE
> on one of your spare IOs, and see if the Icc changes on OE.
> It it does, there is output contetion somewhere.
I'm pretty sure it isn't external output contention.  This 
design only has 3 inputs and 7 outputs, although the internal 
logic is full (first time I've ever used all of a CPLD).  Now 
that I go back over things, I don't think Xilinx's formula for 
95xx current draw has EVER been correct, within a factor of 2 or 
3, this is just the first time it really mattered, as this board
runs off 12 V, and I put a tiny regulator on the board to get 5 
V.  I have had to change to a larger regulator (both 
current-wise and physically) and put more copper on the board as 
a heat dissipator.

Thanks,

Jon

Article: 122016
Subject: Re: Actel. Libero. Synplify
From: "John_H" <newsgroup@johnhandwork.com>
Date: Tue, 17 Jul 2007 10:19:44 -0700
Links: << >>  << T >>  << A >>
(top posting due to bad quote)

If you're not using the FPGA primitives defined by the FPGA vendor which 
typically don't include DFF or AND2, you must include a library.  Long ago 
Synplify required the unisims.v file for the Xilinx devices I worked with 
was added to the project.  Thay have since changed the tool to imply the 
library directly from the use of the device.

Check what your FPGA supports to figure out what primitives are supported by 
the chip.  Since Actel isn't as mainstream as Altera and Xilinx, there may 
still be a need to manually attach the library to your project.

- John_H


<dorama2@gmail.com> wrote in message 
news:1184690666.682978.42620@e16g2000pri.googlegroups.com...
when I synthesize the FPGA (ProASIC PLUS) in Synplify [or] Libero I have
got a lot of warnings: "Unbound component (DFF or AND2...) mapped to
black box". It seems that don't recognize the basic components, żdo I
need any library?

thanks



Article: 122017
Subject: Re: Actel. Libero. Synplify
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 17 Jul 2007 18:24:08 +0100
Links: << >>  << T >>  << A >>

<dorama2@gmail.com> wrote in message 
news:1184690666.682978.42620@e16g2000pri.googlegroups.com...
when I synthesize the FPGA (ProASIC PLUS) in Synplify of Libero I have
got a lot of warnings: "Unbound component (DFF or AND2...) mapped to
black box". It seems that don't recognize the basic components, żdo I
need any library?

thanks

Maybe not. The placement tool may recognise the names of the black boxes in 
the synthesis results as primitives and insert the appropriate parts. Try a 
place and route and see what happens!
Cheers, Syms.



Article: 122018
Subject: Re: Xilinx XC9536 current draw ?
From: Jon Elson <elson@pico-systems.com>
Date: Tue, 17 Jul 2007 12:25:05 -0500
Links: << >>  << T >>  << A >>
lb.edc@telenet.be wrote:
> 
> Have you seen the design drawing lower current in another batch? Also,
> you're saying you are using pretty much all of the device's resources.
> Is this all registered? Are you using latches in the design? I ask
> this because I have had similar problem in the past with a 128MC
> design, consuming almost 300mA of current @5V. 
> The main reason was a failure in the netlist generation, resulting in
> all the flipflops behaving as a latch. Manually editing the netlist
> resolved the issue.
WOW!  First, I don't see why the latches should increase power 
consumption, but there must be some reason.  I have some doubt 
that all my FFs could be latches, as I have some multi-stage 
counters in there, I don't see how that could be implemented 
with latches.  300 mA is not a shocker with a 128 macrocells.
I don't know what family you are referring to, the 95xx comes in
108, 144 and 180 MCs in that range.  I've used some of the 144 
and 216 MC versions, and I'm sure they drew close to 200 mA, and 
that is within sight of the datasheet figures, anyway.  Xilinx's 
formula for all MCs in low-power, and no clock is Icc = 0.9*#MC.
For 36 macrocells, all in low power, then the current should be
0.9 * 36  = 32.4 mA.  Turning the clock on or off makes only a 
small and reasonable difference, about 3 mA.  So, it is static 
power draw that seems to be the problem.

Can you describe the netlist problem a little more, and tell me 
what family it was?  I'm using Xilinx ise 4.2i, which is one of 
the last versions that supported the 5 V chips.  I entered my 
design as a single VHDL file,  I have used the boilerplate

  if (clock'event and clock='1') then

in most of my processes, I think that is supposed to map to a 
type-D FF for all sequential assignments.  A quick scan of the
xxx.rpt file shows a whole bunch of lines like :

/a_hi  :=  enable_out * apol * apolold * adrive
     a_hi.CLKF  =  /clock_in
     a_hi.PRLD  =  GND

That appears to me to be the typical definition of a D FF.
There is a fair amount of combinatorial logic in the design, the 
web case consultant from Xilinx said that could raise power 
consumption, but he didn't elaborate on that.

Thanks much for the info,

Jon

Article: 122019
Subject: Re: Xilinx XC9536 current draw ?
From: lb.edc@telenet.be
Date: Tue, 17 Jul 2007 17:56:57 GMT
Links: << >>  << T >>  << A >>
On Tue, 17 Jul 2007 12:25:05 -0500, Jon Elson <elson@pico-systems.com>
wrote:

>lb.edc@telenet.be wrote:
>> 
>> Have you seen the design drawing lower current in another batch? Also,
>> you're saying you are using pretty much all of the device's resources.
>> Is this all registered? Are you using latches in the design? I ask
>> this because I have had similar problem in the past with a 128MC
>> design, consuming almost 300mA of current @5V. 
>> The main reason was a failure in the netlist generation, resulting in
>> all the flipflops behaving as a latch. Manually editing the netlist
>> resolved the issue.
>WOW!  First, I don't see why the latches should increase power 
>consumption, but there must be some reason.  I have some doubt 
>that all my FFs could be latches, as I have some multi-stage 
>counters in there, I don't see how that could be implemented 
>with latches.  300 mA is not a shocker with a 128 macrocells.
>I don't know what family you are referring to, the 95xx comes in
>108, 144 and 180 MCs in that range.  I've used some of the 144 
>and 216 MC versions, and I'm sure they drew close to 200 mA, and 
>that is within sight of the datasheet figures, anyway.  Xilinx's 
>formula for all MCs in low-power, and no clock is Icc = 0.9*#MC.
>For 36 macrocells, all in low power, then the current should be
>0.9 * 36  = 32.4 mA.  Turning the clock on or off makes only a 
>small and reasonable difference, about 3 mA.  So, it is static 
>power draw that seems to be the problem.
>
>Can you describe the netlist problem a little more, and tell me 
>what family it was?  I'm using Xilinx ise 4.2i, which is one of 
>the last versions that supported the 5 V chips.  I entered my 
>design as a single VHDL file,  I have used the boilerplate
>
>  if (clock'event and clock='1') then
>
>in most of my processes, I think that is supposed to map to a 
>type-D FF for all sequential assignments.  A quick scan of the
>xxx.rpt file shows a whole bunch of lines like :
>
>/a_hi  :=  enable_out * apol * apolold * adrive
>     a_hi.CLKF  =  /clock_in
>     a_hi.PRLD  =  GND
>
>That appears to me to be the typical definition of a D FF.
>There is a fair amount of combinatorial logic in the design, the 
>web case consultant from Xilinx said that could raise power 
>consumption, but he didn't elaborate on that.
>
>Thanks much for the info,
>
>Jon

Jon,

This design is almost 6 years ago - and was a lattice ispLSI1032
normal currents were something like 200..220mA, so 300mA was almost
50% increase. I must admit that the original design was done in
schematic entry and maybe some conversion problem may have risen.

To elaborate on your doubt on latch power - this is/was done by a
couple of OR or XOR ports (I don't remember all the details anymore).

By examining the netlist, one particular part was repeated a lot of
times (the latches) of which there were quite some in the design. This
design was amongst other things an interface to a 8051 µC so there is
always at least one latch to split address and data.
Then I built a single latch using VHDL and schematic and comparing the
two netlists. I found that this was done a different way. So I then
edited the original netlist with the VHDL generated netlist part. This
way I cound reduce the current consumption to normal values.

Like you tell you are using an older version of ISE it can well be
that there are some minor bugs in the netlist generation that causes
the problems.
As the design is 'only' 36MC's you should be able to scan for possible
issues with what you had in mind, don't you think?

Good luck,

Luc

Article: 122020
Subject: Re: Xilinx XC9536 current draw ?
From: Andy Botterill <andy@plymouth2.demon.co.uk>
Date: Tue, 17 Jul 2007 19:08:32 +0100
Links: << >>  << T >>  << A >>
If you can measure Idd in the positive supply line you could try the 
following.

Turn all 7 outputs high. Measure Idd.
Turn one output low. Measure Idd.

Increase the number of outputs low until all are off. Measure Idd each time.

The changes of Idd should be comparable to the output IOH.

Drive all inputs high. Measure Idd.

Turn each output off and note the change in Idd. Unless you have low 
value pullups/pulldowns you may have to measure all high then all low.

The will give you an indication of the input current taken by all of 
your input cells. Does it compare with your datasheet?

Ideally you can do this without changing the output state. Your design 
may not ket you do this.

Take you original Idd and subtract the output current and input current. 
This gives you the active supply current+plus any static pin clashes.

It's worth running a dvm over pins which you think are inactive just to 
make sure that they are floating.

Good luck. Andy

Article: 122021
Subject: Re: XC9572XL bus hold - Cant be disabled
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Tue, 17 Jul 2007 19:12:24 +0000 (UTC)
Links: << >>  << T >>  << A >>
Peter Wallace <pcw@karpy.com> wrote:
> No matter what options I use, the bus hold circuits are enabled on the
> inputs of a XC9572XL (same problem with 95144XL) in a design 
> of ours. I've tried
> ISE6.3 and WEBPack 9.1, no difference.  

> The reason I want high impedance inputs is that they are used with a high
> value series resistor (and clamp diodes) as part of a power MOSFET
> out-of-saturation short circuit protection.

> If anyone has experience with this or especially how to solve it I would
> be very grateful...

Look for UG445
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 122022
Subject: Re: Xilinx XC9536 current draw ?
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Wed, 18 Jul 2007 08:42:03 +1200
Links: << >>  << T >>  << A >>
Jon Elson wrote:

> Jim Granville wrote:
> 
>>
>> So you are saying the device is 100% functional, when programmed ?
>> How many devices have you checked ?
> 
> About 4-5.
> 
>> The symptoms suggest a shorted pin, or bad drive (not Vdd, or Vss)
> 
> No, I really don't think so.  I have gone over it very carefully, and 
> also checked it by loading the same program into a chip on a different 
> board that I have used before.  I just put the CPLD on that board, 
> nothing else.
> 
>> you could try the same code, but with all outputs connected to an OE
>> on one of your spare IOs, and see if the Icc changes on OE.
>> It it does, there is output contetion somewhere.
> 
> I'm pretty sure it isn't external output contention.  This design only 
> has 3 inputs and 7 outputs, although the internal logic is full (first 
> time I've ever used all of a CPLD).  Now that I go back over things, I 
> don't think Xilinx's formula for 95xx current draw has EVER been 
> correct, within a factor of 2 or 3, this is just the first time it 
> really mattered, as this board

There will be a Product term OR collector current adder, and that
WILL hike with usage. Each wide-and  product term, uses an open drain
sense amp scheme in these older devices.

As a simple test, you could set up the same FF usage, same power flags, 
  but design a simple shift register - single D FF's. That will have the 
same qty of MACROCELLs enabled, but a fraction of the OR channels.
If Icc plummets, then that is your problem.


> runs off 12 V, and I put a tiny regulator on the board to get 5 V.  I 
> have had to change to a larger regulator (both current-wise and 
> physically) and put more copper on the board as a heat dissipator.

Ouch.
You could look at the Atmel ATF1502ASL and ATF1504ASL.
that have 5V operation, and low Static Icc.

-jg






Article: 122023
Subject: Re: Which embedded O/S for a 32-bit RISC microcontroller?
From: Sean Durkin <news_jul07@durkin.de>
Date: Tue, 17 Jul 2007 23:40:37 +0200
Links: << >>  << T >>  << A >>
Cla wrote:
> The target hardware would most likely be one of the Tensilica 32-bit
> cores, or an ARM/922 (probably not an ARM7 TDMI.)
> 
eCos might be worth a look as well. It's free, supports a lot of
different uCs, and you can buy professional support from several companies.

cu,
Sean

-- 
My email address is only valid until the end of the month.
Try figuring out what the address is going to be after that...

Article: 122024
Subject: 8B/10B decoding after serial transmission problem?
From: damc4 <damc4@gmx.de>
Date: Tue, 17 Jul 2007 14:52:08 -0700
Links: << >>  << T >>  << A >>
Hello,

I run into a problem/bug where I currently don't see a solution,
probably somebody can give me some hints.

I encoded data frames with 8B/10B, filled the gaps between the data
with K28.5 characters and then transmitted the data stream via a
serial line.
On the receiver side I did the same backwards and run their into a
problem:
The serial data stream of the following bytes (0x6E, 0x74, 0x77, 0x65
or D14.3, D20.3, D23.3, D5.3) contains a bit sequence that is
identical to the K28.5 character and therefore my receiver recognises
also this K char instead of the intended data byte.

What is going wrong here or what kind of mechanism do I forgot to
implement?
Any ideas or help is very welcome!

Best Regards,

Damc




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