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On Jun 8, 2:42 am, "Ben Jones" <ben.jo...@xilinx.com> wrote: > Maybe you can share some details of why exactly you need such a macro? The application requires one processed data point per clock, pipelined ... some 17 multiplies and 6 squarings, per point. Not even close to enough multiplier blocks in the XC3S2000 FPGA (just 40), but nearly enough LUTs (just under 41K). The LUT squarers are simpler, as many terms fall out. The application's data has some specific relationships, which also allow some optimizations of the multipliers, with an estimated savings in area of about 20%. Plus a few multiplies are with scaled integers, allowing a few LSB's to be ommitted in the results.Article: 120526
John I just have had bad experience with Xilinx. And having a small company, I was left alone 'in the dark'. Even disty didn't bother. One of the Lattice FAE's came in and het converted my design, and got it working. Therefore... On your comment, I'm still waiting for the ideal FPGA. One power supply, a couple of inputs, a couple of outputs - that's it. Of course then the discussion starts all over again. How many in- and outputs... That said, I like the Lattice products, the feature set serves me well. And the capabilities of the 'PureSpeed I/O's' (2Gbps) are far beyond what Xilinx can offer today - even on their 'high speed' 65nm process. Luc On Thu, 7 Jun 2007 13:42:35 -0700, "John_H" <newsgroup@johnhandwork.com> wrote: ><lb.edc@telenet.be> wrote in message >news:mjog63ljl67eee204pt3e0o2mcvmsqmra1@4ax.com... >> Austin, >> >> And that's why the big X can't still offer a high end V5 with MGT's on >> a low cost small footprint (like 256fpBGA), isn't it? >> Some customers are not so happy anymore with the model that the big >> ones dictate the law. This is probably the biggest reason why there >> will always be a place for companies like Lattice and Actel. >> >> "...but is so small, they can't compete on IP, services, software, and >> all the other ..." is this your personal opinion, or is this the way >> that Xilinx masks that you are not capable of achieving the same >> performance out of a high speed process...? >> >> And what I see (and hear) is that Lattice FAE's deliver at least the >> same or sometimes even better support than Xilinx's (for normal >> companies, not the Alcatel's and Cisco's of this world of course). I >> can't comment on Altera because I never used it before. >> >> Regards, >> >> Luc > >Luc, > >Do you simply have a Xilinx thorn in your side that's making you a little >grumpy? > >The MGTs *are* dedicated I/O standards without the "baggage" of supplying >every standard known to Marketing. > >There are devices that have very high speed I/O in wireframe parts. There >are devices that have high speed transceivers on tiny BGAs. But how many >designers - what percentage of the market - need a cutting-edge family with >enormous bandwidth to be in a tiny package that rivals the size of the die? > >I was in telecom years ago where the ideal chip might have 8 I/O for the >system and a little more for control. They're just not made because the >number of people that could use them are so small. > >Since most designers can simply not use some of the many I/O available on >the hyper-performance devices, how many people are truly affected by the >absence of the "convenient" 256 bin BGA? > >I'm also left wondering: what's the smallest flip-chip package Xilinx >produces for any family? > >- John_H >Article: 120527
Lattice's online store now offers silicon devices. The store can be accessed at http://www.latticesemi.com/store The silicon store is powered by one of our distribution partners, Mouser Electronics. The online store is particularly helpful for customers looking for programmable logic devices that are readily available and do not require a minimum order quantity. Customers also can use a credit card, which makes the purchase process both quick and convenient. The store's shelves offer programmable logic devices, including selected 90nm FPGAs, as well as its ispLEVER software design tool suite, a wide variety of FPGA and CPLD development boards, and download cables. Shipping is available worldwide, frequently on the same day the order is received. ~Bart Borosky, LatticeArticle: 120528
Ed McGettigan schrieb: > Antti wrote: > > http://www.zylogic.com.cn/english/products04.htm > > > > I wonder what that is? > > it looks like the product Triscend never announced, but maybe its a > > hoax, > > still funny at least the spec are known now what Triscend was about to > > announce > > just before it was purchased by Xilinx > > > > Antti > > > > Zylogic and Rochester were handling the end-of-life commitments > that were in place for the Triscend parts. I would be a bit > shocked if they would even take an order at this point unless > they still had some parts in stock. > > Ed McGettigan > -- > Xilinx Inc. me too :) was just surprised those pages are still online!! maybe its some "time freeze zone" ;) AnttiArticle: 120529
bart schrieb: > Lattice's online store now offers silicon devices. The store can be > accessed at http://www.latticesemi.com/store > > The silicon store is powered by one of our distribution partners, > Mouser Electronics. The online store is particularly helpful for > customers looking for programmable logic devices that are readily > available and do not require a minimum order quantity. Customers also > can use a credit card, which makes the purchase process both quick and > convenient. > > The store's shelves offer programmable logic devices, including > selected 90nm FPGAs, as well as its ispLEVER software design tool > suite, a wide variety of FPGA and CPLD development boards, and > download cables. Shipping is available worldwide, frequently on the > same day the order is received. > > ~Bart Borosky, Lattice gosh, this online store is just doing database query into mouser ! so there is no such thing as "lattice online store", it just means that lattice is not selling anything (same as Xilinx) but instead redirects to mouser and whats even worse - there are NO XP2 devices, not in stock, not orderable. And NO XP2 development boards etiher. when lattice web says (for development kits) contact lattice sales, then this usually measn "NOT AVAILABLE for purchasing.." :( Antti who has been waiting for XP2 since August 2006, and is still waiting...Article: 120530
This is a very basic question. I would appreciate your help. I have a
Xilinx FPGA Verilog project that containts several files. I would like
to use an include file for some definitions that I would like to use
in several files.
I addeded the line:
`include "definitions.v"
to one of the .v modules containing the FPGA code.
definitions.h contains the following:
//definitions.h
parameter NO_SELECT = 16'h00,
REG1_ADDRESS = 16'h01,
REG2_ADDRESS = 16'h02,
REG3_ADDRESS = 16'h03,
REG4_ADDRESS = 16'h04,
REG5_ADDRESS = 16'h05,
BLOCK1_ADDRESS = 16'h06,
REG1_SELECT = 16'h01,
REG2_SELECT = 16'h02,
REG3_SELECT = 16'h04,
REG4_SELECT = 16'h08,
REG5_SELECT = 16'h10,
BLOCK1_SELECT = 16'h20;
>From Xilinx ISE I get the following error:
ERROR:HDLCompilers:26 - "rtl/definitions.v" line 2 expecting 'EOF',
found 'parameter'
When I compile in ModelSim I get the following error:
** Error: D:/rtl/rf_board_top.v(23): Cannot open `include file
"definitions.v".
What am i doing wrong?
How to get ModelSim to find the include file (it is in the same
directory as the Verilog modules)?
Thanks for your help.
Article: 120531For ISE, the parameter only applies within a module so the include statement would be after the port list. If you want "global parameters" you need to figure another method; this is not how Verilog works. For Modelsim, the tool needs to have an appropriate path specified to the file. I don't know the option to add the path but I'd try -y as a stab if I didn't want to check for "path" in the help. <freeagent.20.oracle@xoxy.net> wrote in message news:cpaj63h4r5oe2kiotf3oknjau3a5g6iu5o@4ax.com... > This is a very basic question. I would appreciate your help. I have a > Xilinx FPGA Verilog project that containts several files. I would like > to use an include file for some definitions that I would like to use > in several files. > > I addeded the line: > > `include "definitions.v" > > to one of the .v modules containing the FPGA code. > > definitions.h contains the following: > > > //definitions.h > > parameter NO_SELECT = 16'h00, > REG1_ADDRESS = 16'h01, > REG2_ADDRESS = 16'h02, > REG3_ADDRESS = 16'h03, > REG4_ADDRESS = 16'h04, > REG5_ADDRESS = 16'h05, > BLOCK1_ADDRESS = 16'h06, > > REG1_SELECT = 16'h01, > REG2_SELECT = 16'h02, > REG3_SELECT = 16'h04, > REG4_SELECT = 16'h08, > REG5_SELECT = 16'h10, > BLOCK1_SELECT = 16'h20; > > > From Xilinx ISE I get the following error: > > ERROR:HDLCompilers:26 - "rtl/definitions.v" line 2 expecting 'EOF', > found 'parameter' > > When I compile in ModelSim I get the following error: > ** Error: D:/rtl/rf_board_top.v(23): Cannot open `include file > "definitions.v". > > What am i doing wrong? > How to get ModelSim to find the include file (it is in the same > directory as the Verilog modules)? > > Thanks for your help. >Article: 120532
On Fri, 08 Jun 2007 19:24:28 GMT, freeagent.20.oracle@xoxy.net wrote: <snip> >//definitions.h > >parameter NO_SELECT = 16'h00, > REG1_ADDRESS = 16'h01, > REG2_ADDRESS = 16'h02, > REG3_ADDRESS = 16'h03, > REG4_ADDRESS = 16'h04, > REG5_ADDRESS = 16'h05, > BLOCK1_ADDRESS = 16'h06, > > REG1_SELECT = 16'h01, > REG2_SELECT = 16'h02, > REG3_SELECT = 16'h04, > REG4_SELECT = 16'h08, > REG5_SELECT = 16'h10, > BLOCK1_SELECT = 16'h20; > > <snip> I believe that the syntax of your definitions.h file is wrong. `define NO_SELECT 16'h00 `define REG1_ADDRESS 16'h01 (and so on) should work, to judge from my experience with a comparable situation. Hope that helps. -- Per ardua ad nauseamArticle: 120533
On Fri, 08 Jun 2007 19:24:28 GMT, freeagent.20.oracle@xoxy.net wrote: Thanks for the help. That enabled me to get it working. I moved the `include after the port definitions and that fixed ISE problem. I changed the properties on each .V source file to include the directory where the include file was located (even though it was the same directory as the source .v files). This fixed the ModelSim problem.Article: 120534
On Jun 7, 11:07 pm, "jtw" <wrightjt @hotmail.invalid> wrote: > Eric asked 'how' you would do it with logic gates. Once you know that, then > the question is to how to describe that behavior in VHDL, verilog, c, c++... > > If you can write behavioral descriptions for your FFs and logic gates in > VHDL (etc.), you have a solution to your problem. > > If you can abstract the sequence to a state machine, and code that in VHDL > (etc.), you have another solution to your problem. > > If you understand what it is you really want to do, and appropriately > describe and code it, you are likely to have a better solution to your > problem. A better solution, because it will respond to other sequences the > way you intend, rather than just matching the small set of stimulus-response > vectors described. There will be many solutions that will pass the test > vectors, but will not 'do the right thing' in general. > > JTW > > <willwestw...@gmail.com> wrote in message > > news:1181261769.985939.84080@x35g2000prf.googlegroups.com... > > > > > On Jun 7, 3:54 pm, Eric Smith <e...@brouhaha.com> wrote: > >> willwestw...@gmail.com writes: > >> > I hope I explained ok here. I'm having trouble putting this behavior > >> > into codes in VHDL. Someone has any idea? > > >> How would you design it with logic gates (and flip-flops, if required)? > > >> Once you know that, you can just do the same thing in VHDL. > > > Yes you can do it in logic gates, but I want behavior modeling. If > > using FF and logic gates, it would make this totally a netlist > > coding. > > > Here is the Requset, Reset, and Acknowledge again: > > > Request(0 to 3): 0000 1010 0110 1101 0010 1001 0001 1000 1011 1011 > > 1000 0101 1001 > > Reset: > > HHHHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHHHHLLLLLLLLLLLLLLLLLLLLL > > Ack(0 to 3): 0000 1000 0010 0100 0010 1000 0001 1000 0000 1000 > > 1000 0100 0001 > > > I also plan to convert this code into Verilog, C or C++ later on, so > > if you have algorithm or codes in those languages, it's fine too.- Hide quoted text - > > - Show quoted text - I will describle the behavior again and hopefully someone can help. The arbiter is 4 bits input and output but it can only allow 1 bit to go high at a time on the ouput (i.e. 0010). It compares the input, current request (C_R) with previous request (P_R) in memory to generate output, acknowledge (ACK). If a bit on P_R is also on the C_R, the acknowledge is not changed because it thinks the P_R is requested on C_R again. If the C_R bit was also in the P_R and that bit didn't get the acknowledge bit last time, it will get it this time. There's also a reset line which sets all the output to 0000 when it's high. Here is a sample input and output when reset is low. C_R(0 to 3): 0000 1010 0110 1101 0010 1001 0001 1000 1011 1011 ACK(0 to 3): 0000 1000 0010 0100 0010 1000 0001 1000 0000 1000 I understand the behavior but just can't seem to figure out the coding style.Article: 120535
In article <1181337745.613125.274670@r19g2000prf.googlegroups.com>, <willwestward@gmail.com> wrote: >I will describle the behavior again and hopefully someone can help. >The arbiter is 4 bits input and output but it can only allow 1 bit to >go high at a time on the ouput (i.e. 0010). It compares the input, >current request (C_R) with previous request (P_R) in memory to >generate output, acknowledge (ACK). If a bit on P_R is also on the >C_R, the acknowledge is not changed because it thinks the P_R is >requested on C_R again. If the C_R bit was also in the P_R and that >bit didn't get the acknowledge bit last time, it will get it this >time. There's a problem in that specification. If there are three simultaneous requests, one of them will be granted the first time, leaving two bits in P_R that are still present in the next cycle's C_R. The first sentance allowed only one output to go high (be acknowledged), but the last sentance I quoted above, about "and that bit didn't get the acknowledge bit last time", requires that -both- of the two old requests be acknowledged in the current cycle. To resolve this, the spec would have to be rewritten to something similar to, "If there are C_R bits that were also in the P_R and those bits did not get the acknowledge bit last time, one of them will get it this time." But even this has problems, because it allows for indefinite postponement. Suppose A, B, C have simultaneous requests. One of them is granted, say A. Suppose A re-requests before the next sampling, so at the time of the next sampling A is active because of the re-request and B and C are still active because they have not been acknowledged. This time, A will not be the one serviced because of the "and that bit didn't get the acknowledge bit last time" clause (which imparts some fairness), so one of B or C will be served, say B, leaving A and C active. The next cycle, A and C (at least) are still waiting from and were waiting in the previous cycle, and neither were granted in the previous cycle, so by the clause above, both of them are eligable for service this time. Which one will be chosen? The specs don't say, so although serving C would be fairest because it has been waiting longest, it could be A that is served this time. If B had re-requested as well during the same cycle, then again the next cycle around you have two requests that hadn't been served the previous time, and again it might not be C that you choose to serve. Repeat indefinitely and you can see that C might never be served if the ACKs toggle between A and B. -- If you lie to the compiler, it will get its revenge. -- Henry SpencerArticle: 120536
OK, It seems that bufio skew specification of 50ps clock tree skew is not part of the equation. 10ps skew is something per load is how it works. Thus having 40 clock load on a given buiio will have 400ps skew. This just takes care of the clock skew. But I would imagine that there will be package skew. I am assuming that 10ps skew per load does not include this. Is that correct? MaverickArticle: 120537
Maverick, Flight time or package trace, is not included. You need that, as well. The IBIS file has RLC values that give an estimate when they are used to create a t-line. We also have support information for actual time per IO. AustinArticle: 120538
Thanks Mike, I got it working. I used the EDK to start the compilation process and it put those extra files....modelsim.ini, _info, etc. that weren't in there before. Compilation errored out, but I went the manual route and it works now.Article: 120539
Sorry about multiple posts, but I am just trying to migrate a project that was once working in sim over to 9.1 tools. I got all libraries compiled, EDK sim files generated, etc. By the way, the testfixture example file in 9.1 is pretty handy. Anyways, I am looking at primary signals in sim and it's not working as expected. The clocks and resets are all OK. Even one of my hardware IP cores is working as expected. However, the program counter signal 'pc_exe' starts at 0 and just increments continuously every microblaze clock. It is like the processor isn't simulating correctly. I haven't dug too deeply into this. I am just not sure if the problem I am seeing is in software or hardware. The SW compiles fine. I am leaning towards hardware but I am not sure what exactly would cause microblaze to just start and never really work correctly. Thanks for any help! MottyArticle: 120540
Mark McDougall wrote: > I've actually implemented a read-only (state machine) emulation of the > WDC-1793 in an FPGA which sources data from a serial flash device. Cool! Have you made that publicly available? > IIUC the WDC 1793 did actually have a (purpose-built?) microprocessor. It had a state machine. EricArticle: 120541
Wojtek, Analyzing all clock transfers by default is consistent with what other SDC based, ASIC strength Timing Analyzers (e.g. PrimeTime) do, and that is the main reason why we did it this way. The warning you got is intended to tell you that the fitter is seing hold violations that look too high to be normal. This is basically the waring you are asking for, but maybe the text is not that clear. Basically, a number of issues with the SDC can create this. Most common ones are 1) not cutting transfers between unrelated clocks (what seems to be your case) and 2) Not adding "set_multicycle_path - hold" when adding a "set_multicycle_path -setup" (Another difference with Classic). In your case, I recommend you use the report_clock_transfers command to review all your clock transfers, and then add a false path or clock group as needed. Also, please note that we improved the Quartus II V7.1 QSF2SDC utility to automatically add the set_clock_groups to match Classic Timing Analyzer behavior. We also automatically add the hold multicycles to match Classic behavior. Hope this helps. -David Karchmer AlteraArticle: 120542
"cutemonster" <ckh827@hotmail.com> wrote in message news:RoGdndnLdPZkYvXb4p2dnAA@giganews.com... > > My question is, do I need a adaptive filter Nobody will tell you what you need unless you explain what you are trying to do. What is your application? If you are measuring DC why are you sampling at 50 MHz? /MikhailArticle: 120543
Hi, I have here my brand new Spartan 3e starter kit, therefore I could test my vhdl code in real, could ... Anyway, I'm using ISE 9.1 Sp3 Webpack for Linux and usr-driver.so from http://www.rmdir.de/~michael/xilinx. As mentioned in the README udev is configured right. Plugging the USB got in /var/log/dmesg: usb 4-5.4: new high speed USB device using ehci_hcd and address 4 usb 4-5.4: configuration #1 chosen from 1 choice usb 4-5.4: USB disconnect, address 4 usb 4-5.4: new full speed USB device using ehci_hcd and address 5 usb 4-5.4: not running at top speed; connect to a high speed hub usb 4-5.4: configuration #3 chosen from 1 choice The green LED is on. lsubs got: Bus 004 Device 002: ID 04b4:6560 Cypress Semiconductor Corp. CY7C65640 USB-2.0 "TetraHub" Bus 004 Device 001: ID 0000:0000 Bus 003 Device 004: ID 046d:abd0 Logitech, Inc. Bus 003 Device 003: ID 046d:c50c Logitech, Inc. Bus 003 Device 002: ID 0451:2036 Texas Instruments, Inc. TUSB2036 Hub Bus 003 Device 001: ID 0000:0000 Bus 002 Device 001: ID 0000:0000 Bus 001 Device 001: ID 0000:0000 There is nothing new. Calling impact using as root: LD_PRELOAD=/opt/Xilinx91i/bin/lin/libusb-driver.so /opt/Xilinx91i/bin/lin/impact got: Connecting to cable (Usb Port - USB21). Checking cable driver. File version of /opt/Xilinx91i/bin/lin/xusbdfwu.hex = 1025(dec), 0x0401. File version of /etc/hotplug/usb/xusbdfwu.fw/xusbdfwu.hex = 1025(dec), 0x0401. libusb-driver.so version: 2007-05-27 00:37:02. Cable connection failed. Reusing B4020002 key. Reusing 38020002 key. Reusing B5020002 key. Reusing 39020002 key. Reusing B6020002 key. Reusing 3A020002 key. Reusing B7020002 key. Reusing 3B020002 key. PROGRESS_END - End Operation. Elapsed time = 2 sec. Cable autodetection failed. After plug off and plug in again, the green LED is off. Kernel is 2.6.21 (debian/testing), Impact 9.1.03i. Compiling the xilinx stuff suffers/fails from wrong kernel version depency. Thanks OlafArticle: 120544
I am after a pcie card where the ip doesn't cost an arm and a leg unlike that for xilinx's s3 pcie starter kit Got quoted > $15,000 for the pcie core(End point pipe) by the local distributor who was trying to push us towards Virtex-5 ML555 PCI Express Board HW-V5-ML555-G which is overkill for what we need. Looking for a card that has drivers and examples for windows and linux and includes the ipcores needed(board license is fine) Basically uni research project to prove a design concept (one off) 1x is fine. Doesn't have to be xilinx based even though that would be easier as we have all the software.. Has any here used the Lattice pcie cards and cores ? AlexArticle: 120545
Antti wrote: > when lattice web says (for development kits) contact lattice sales, > then this usually measn "NOT AVAILABLE for purchasing.." :( Contact them anyway :) At least MSC told us that there are in fact XP2-parts available right now as engineering samples. Unfortunately not the tiny 8x8mm csBGA-package that would be the most interesting at the moment... Maybe Mouser doesn't stock engineering samples, and that's why they don't have XP2 parts available. cu, Sean -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 120546
On Fri, 08 Jun 2007 14:27:23 GMT, David Tweed <dtweed@acm.org> wrote: >It turns out that XST had assigned >the reset of one of the flip-flops to a different copy of the global >reset signal, which presumably had been created because the fanout >of the reset signal had reached some threshold. Apparently, the >assignment of loads to specific copies of replicated nets occurs >at an earlier step, and doesn't take into account directed packing >constraints. > >So, my question is this: Is there an easy way, in my VHDL source >file, to insure that all of my flip-flops are connected to the >*same* copy of the reset signal, without introducing additional >logic into the path? The file is attached below for reference. Split the resets up yourself, before XST gets to them? Assign the main reset to a second signal, and apply that to the critical ones ONLY (or all within this localised block) - you may have to apply a KEEP attribute to the second reset signal. - BrianArticle: 120547
On Sat, 9 Jun 2007 17:41:41 +1000, "Alex Gibson" <news@alxx.org> wrote: >I am after a pcie card where the ip doesn't cost an arm and a leg >unlike that for xilinx's s3 pcie starter kit > >Got quoted > $15,000 for the pcie core(End point pipe) by the local >distributor >who was trying to push us towards >Virtex-5 ML555 PCI Express Board HW-V5-ML555-G >which is overkill for what we need. ML505 is about half the price, if that helps... - BrianArticle: 120548
Sean Durkin schrieb: > Antti wrote: > > when lattice web says (for development kits) contact lattice sales, > > then this usually measn "NOT AVAILABLE for purchasing.." :( > Contact them anyway :) At least MSC told us that there are in fact > XP2-parts available right now as engineering samples. Unfortunately not > the tiny 8x8mm csBGA-package that would be the most interesting at the > moment... > > Maybe Mouser doesn't stock engineering samples, and that's why they > don't have XP2 parts available. > > cu, > Sean > ok, thanks, yes I am sure silicon samples are available, I was more refereffing to those lattice evaluation kits that are "contact lattice" those are usually not for sale, but only to lease.. this is STUPID STUPID... i have tried to purchase some lattice boards, only to get offer to lease the board. :( AnttiArticle: 120549
Alex Gibson wrote: > I am after a pcie card where the ip doesn't cost an arm and a leg > unlike that for xilinx's s3 pcie starter kit > > Got quoted > $15,000 for the pcie core(End point pipe) by the local > distributor > who was trying to push us towards > Virtex-5 ML555 PCI Express Board HW-V5-ML555-G > which is overkill for what we need. > > Looking for a card that has drivers and examples for windows and linux > and includes the ipcores needed(board license is fine) > > Basically uni research project to prove a design concept (one off) > 1x is fine. > > Doesn't have to be xilinx based even though that would be easier as we have > all the software.. > > Has any here used the Lattice pcie cards and cores ? > > Alex The Lattice hardware is a chunk to swallow to start off with. Perhaps there's some better consideration for the core than with Xilinx but I wouldn't guarantee it. I just got advertising email at work from PLDA for their PCIe x8 core "Starting from $5995" or some similar number between $5k and $6k. The ad was announcing the new Altera version though PLDA supports Xilinx as well. Bottom line: maybe it's good to check out PLDA and NW Logic in addition to the FPGA vendors. - John_H
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