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Actually, to solve the problem mentioned above, before closing chipscope Analyzer save your settings it will be a .cpj extension file then when you download your new configuration file open that cpj file that you had saved. Sics On Jul 12, 1:53 pm, Ben Jackson <b...@ben.com> wrote: > On 2007-07-12, Zara <me_z...@dea.spamcon.org> wrote: > > > > > Take a look at .cdc files (they are importd or exported from > > Chipscope) They contain a list of signals and aliases that you may > > create/edit with a text editor. > > But how do you name busses? Naming signals is easy... > > -- > Ben Jackson AD7GD > <b...@ben.com>http://www.ben.com/Article: 121726
"Yao Sics" <yao.sics@gmail.com> wrote in message news:1184227210.767021.171810@57g2000hsv.googlegroups.com... > Actually, to solve the problem mentioned above, before closing > chipscope Analyzer save your settings it will be a .cpj extension file > then when you download your new configuration file open that cpj file > that you had saved. > > Sics > > > Yeah, but what a dog's breakfast that file is. If you delete busses, they persist forever in the file but with zero size. <rant follows>I'm convinced that whoever wrote chipscope never uses it on a proper heirachical design. The viewer needs to have the signal name window justified to the right, otherwise I just see the pathname of the signal I'm trying to look at. (It's not rocket science, just look at how ModelSIM does it) Come to think of it, perhaps the GUI guy comes from a place where they write from right to left? So, you can rename the signals to something shorter with either an editor on the cpj file or a lot of right-clicks. But add another bunch of signals and re-import the cdc file: all the edits disappear. Way to go, GUI writer guy. The chipscope could be so much better, with a little forethought and effort. It should be a crime to take such a good idea and hobble it like that. The underlying engine is pretty good. (But it needs a clock enable input for the clock. That would probably double it's useful frequency range) Cheers, Syms.Article: 121727
On Jul 11, 7:38 pm, ML402 <> wrote: > I am starting with the easiest way to test according to ug086.pdf, I chose the DDR SDRAM design with DCM and testbench. So I'll check the ERROR and init_done signals via a LED. > > Do I need to interconnect 3 symbols, interface, testbench and controller? Or are there more? I thought that making a symbol out of the top VHDL module was sufficient. Thanks. No creating a symbol out of the top level is not sufficient if you want to simulate the controller. Think about it. Only the memory controller is good if you just want to implement the design because the memory device is then in hardware and your testbench will be real signals interacting with your design and in this case you will use the trl in the without_tb folder. If you want to simulate, you need to connect the memory controller (with the rtl from the wtih_tb folder) with the memory device. MIG produces a sample top level testbench that shows this to you, note that it does not initialize the correct number of devices etc. . For example if you have a 36bit wide interface, and your memory model is only 18bits wide, you need to instantiate 2 of your 18bit models and connect them up with your 36 bit wide interface. The error you get in NGDBuild is probably because the rest of the HDL files are not in your project (work) directory or added to the project. Add them to the project as well and the error should go away. CheersArticle: 121728
In article <f733on$cl61@cnn.xilinx.com>, austin <austin@xilinx.com> writes: |> opencores is up for sale, and there is no one who cares to "take it." |> |> What does that say? That it is not profitable to give free hosting, especially not to a high-traffic site? I don't see how you relate the *site* opencores.org to the open cores on that site. The site might change to closedip.com through the sale, but the open cores (as in GPL, BSD or whatever "open" license) wouldn't vanish and most likely reappear e.g. on Sourceforge or somewhere else. RainerArticle: 121729
Antti wrote: > On Jul 11, 10:27 pm, Jim Granville <no.s...@designtools.maps.co.nz> > wrote: > >> Does anyone know the status of the promised Altera MAX III CPLDs ? >>These were supposed to roll out early in 2007, but they are >>now not even registering on any Altera road-maps ? >> Has Altera pruned plans for this line ? - or has it gone back for >>'re-work' ? >>-jg > > > Actually Altera's statement was that C-3 comes first (before APR07), > then S-3 and M-3 as last one..So it really looks like this schedule. > Also the status of M-3 was never firmly confirmed, so maybe it is even > cancelled what would be a pity of course. > > surprisingly the current low cost leader is: A3P060 - it kills all > "cross-over FPGA-CPLD" machXO-MAX-II What price points are you seeing for the P060, and the equivalent MachXO and MAX-II's ? > A3/IGLOO 030 devices are not yet shipping, but when they will they > should kill every CPLD above 64/72 > macrocell as well. (price wise at least) > > but I also hope MAX-III comes, with nice packages and single voltage > option, and user flash mem, and... ... SRAM that can be initialised, and buried OSC... -jgArticle: 121730
In news:f72otn$cm32@cnn.xilinx.com timestamped Wed, 11 Jul 2007 07:19:34 -0700, austin <austin@xilinx.com> posted: |------------------------------------------------------------------------| |"[..] | | | |Additionally, a massive amount of work goes into testing and | |re-optimizing every core when the technology node changes. Who will pay| |for that? Who will warrant or guarantee operation? Who supplies the | |test bench vectors to verify proper operation? | | | |Austin" | |------------------------------------------------------------------------| Hello, Testing does not guarantee correctness. Regards, Colin Paul GlosterArticle: 121731
Yao Sics <yao.sics@gmail.com> writes: > Hi Xilinx Killers, > > It is really annoying to rename and group all the signals everytime > when design is modified and new bit file is used to configure the > fpga. Anybody knows how to avoid renaming and regrouping signals in > the analyzer when new bit file is loaded to FPGA? No, it's a pain.. As Symon as pointed out, there's a bunch of flaws in the Chipscope UI.. It's only if I have to that I ever use Chipscope. > For Altera signaltapII, it is very easy to use for on-chip debugging. > And it is very easy to learn too. > Miss those days when using Quartus. Ditto. An interface done right. You can add extra signals from the waveform window and then have it recompile and get on with it. No faffing around in another separate tool. Why should I care about the chipscope core inserter? Just give me some waveforms. Grrr. Sorry, I'll stop ranting now :-) Maybe if we *all* shout loudly enough about chipscope it'll get sorted. Or Xilinx could open the protocol and at least we could write our own front end that would work properly.... Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 121732
Jim, Yes, Antti is correct. Altera moved MaxIII behiind CycloneIII and StratixIII. Regards, Rob "Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message news:46954ac5$1@clear.net.nz... > Does anyone know the status of the promised Altera MAX III CPLDs ? > These were supposed to roll out early in 2007, but they are > now not even registering on any Altera road-maps ? > Has Altera pruned plans for this line ? - or has it gone back for > 're-work' ? > -jg >Article: 121733
Hello,
I would like to know how to put ASM instructions in a C code.
With a G5 you can do that kind of functions:
asm long MyFunct(int a, int b, *pt)
{
fralloc
mr r6, a //r6 has a
mr r7,b //r7 has b
stbu r6,1(pt)
frfree
blr
}
Can I can the same thing in a PPC405 ?
Tanks !
Article: 121734
You can use inline assembly with the tools provided by Xilinx since they
are basically GCC. You have to use the GCC inline assembly format because
inline assembly is compiler, not processor specific. Although, the assembly
commands are processor specific. IBM DeveloperWorks has two good articles
on assembly programming for the PowerPC family of processors. You can find
the instruction set reference doc on both the Xilinx and IBM sites.
---Matthew Hicks
> Hello,
>
> I would like to know how to put ASM instructions in a C code.
>
> With a G5 you can do that kind of functions:
>
> asm long MyFunct(int a, int b, *pt)
> {
> fralloc
> mr r6, a //r6 has a
> mr r7,b //r7 has b
> stbu r6,1(pt)
> frfree
> blr
> }
> Can I can the same thing in a PPC405 ?
>
> Tanks !
>
Article: 121735
Thank you John.
The voltages are configured for
3.3V.All the circuitry seems to be O.k. The download cable does
support the FLEX device.With a similar board we are able to detect the
devices through this cable.
Article: 121736Rainer, The way I read the articles is different from how you read them(?): http://www.eetimes.com/rss/showArticle.jhtml?articleID=200000302&cid=RSSfeed_eetimes_newsRSS http://edageek.com/2007/06/26/opencores-for-sale/ Sounds like they will "go away" unless they find someone to buy them. AustinArticle: 121737
But it helps.... AustinArticle: 121738
Noah, You should sell your agnostic IP. I am sure Ken is flattered to hear how "elegant" you think his soft processor is. My example was just to illustrate that changing your "standard uP" is a non-trivial, and expensive thing to do. AustinArticle: 121739
On a sunny day (Thu, 12 Jul 2007 08:21:15 -0700) it happened austin <austin@xilinx.com> wrote in <f75gtb$fkp1@cnn.xilinx.com>: >Rainer, > >The way I read the articles is different from how you read them(?): > >http://www.eetimes.com/rss/showArticle.jhtml?articleID=200000302&cid=RSSfeed_eetimes_newsRSS > >http://edageek.com/2007/06/26/opencores-for-sale/ > >Sounds like they will "go away" unless they find someone to buy them. > >Austin So, the only 'value' is the Verilog and VHDL code, not so much the 'open cores' label. The correct place where to put it is on a large archive such as ftp://sunsite.unc.edu if it is released under GPL, a simple email to the maintainer would probably solve that. Lost of people make money of open source Redhat, Suse, etc... If they try to cash in on 'open cores' as a label it will be a really disappointing experience. It only costs money to run a server without irritating ads:-)Article: 121740
Hi folks, I am planning to design a PCB featuring three Virtex-4 FX60 FPGAs and some periphery. The three FPGAs are needed due to the data processing complexity and the amount of high-speed IOs (MGTs). What I am most concerned about right now is to find an appropriate clocking solution. In my opinion, there are mainly three alternatives to design the clocking scheme: a) connection of the clock in a star-like topology, feeding each of the three FPGAs with the same clock signal (which has to be possibly duplicated by a clock buffer to generate three out of one clock reference signal, thereby introducing additional jitter) b) clock in daisy-chain, feeding each of the three FPGAs with the identical clock signal which is routed from one device to another (in terms of jitter this is also not an optimal solution) c) each FPGA device is supplied with its own clock (which than can be optimally routed to the device in short distances), but synchronization is a major issue then Does anyone have sufficient experience in designing clock trees and is willing to share his experience, comments, hints and suggestions with me? Thanks in advance GeroArticle: 121741
austin <austin@xilinx.com> wrote: >Nico, > >I don't make things up. I just read about it in eetimes. > >opencores is up for sale, and there is no one who cares to "take it." > >What does that say? That nobody is interested in the brand 'Opencores'. But according to the magazine articles you refer to, they attract a lot of engineers working with programmable logic and ASIC. SO the content of the website is attractive enough. It would be a great buy for an FPGA vendor to push their own products. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 121742
On Jul 11, 7:24 pm, austin <aus...@xilinx.com> wrote: > ... > I don't make things up. I just read about it in eetimes. > opencores is up for sale, and there is no one who cares to "take it." > What does that say? > Austin All, I don't know if we (whether user or contributor to opencores project) and You (FPGA/ASIC company) can live better with or without opencores site. I only hope, if really the opencores site will go off, the contributors will put their project to other open-source sites (i.e. sourceforge but any other will be ok). Just a little remind... once upon a time there were few commercial C/C++ compilers. Today many commercial compilers doesn't exist more and many firms use gnu C/C++ and gnu assembler/linker [maybe/surely You too (FPGA companies) use it]. GNU C/C++ seems to be a clear example of good open source product that has more chance to have a very long life. Is there any other project that can boast 22 year of life without being obsolete ? Yes maybe yes but in IT is a very good target both for commercial and free projects! How this happen ? I don't know... maybe/surely company having interest in it give him money because so they (the company) can use it and so they can build product to sell. And yes, there are a lot of opensource projects that disappear after few monthis. I don't want to state all the cores/software should be free/opensurce, but the I think that we all needs both kind of cores/software (both open and commercial). Maybe in the future companies that today strongly defend the commercial licenses could make more money because more users of open cores are available to buy their product or because using open source they build more product to sell. And Maybe in the future peoples that strongly defend open source could decide to buy commercial product because had good experience with other related free products. Then the problem is not whether are better commercial or open sourced product but if are better good or bad product (both opensource and commercial). Sandro P.S. Sorry for my poor english. I hope concepts were clear anywayArticle: 121743
> Noah, > You should sell your agnostic IP. thanks for your kind words :) But you know i can't really expect it to sell without support of decent tools, application examples, etc. I'm positive about i have in mind and the early work on automation tools (even made a custom instruction/functional-unit generator prototype: http://electronics.physics.auth.gr/people/nkavv/yardstick), but i'm far from delivering the IP with tools. The IP (platform) should complete by December (part of my Ph.D.) but not most of the tools... > I am sure Ken is flattered to hear how "elegant" you think his soft > processor is. PicoBlaze is a great 8-bit processor architecture! I never liked 8x51, 68xx (but i like the 16-bit 68k series and 6502 of course with the extra index register if i recall this correctly, it's been some time), z80 (sorry!) and most 8-bit architectures. Certainly, these COTS were meant to be stable for wide adoption and stability and long (everlasting) life cycles were mandatory for everyone back then. But now low-volume production and ease of differentiation/customization are really meaningful for a good number of cases. > My example was just to illustrate that changing your "standard uP" is a > non-trivial, and expensive thing to do. OK, I guess. > > Austin Nikolaos KavvadiasArticle: 121744
Hello, designing a motherboard featuring a Virtex-4 FX140 FPGA with 24 integrated RocketIOs (Gigabit SerDes IOs) I am now facing the problem of how to get the signals off the board in a most space-saving and elegant way? All 24 differential signals will be connected to some DACs outside the motherboard to convert the signals into the analog signal domain. In the definition of the interface I have nearly all effective degrees of freedom. I once learned that coaxial connections are the most appropriate way to do so in terms of signal integrity, but with 24 differential signals and bidirectional connections that would mean at least 96 SMA connectors (that takes very large board space and implies some skew problems due to the differences in the line lengths). I once used the Tyco ZDOK system (plug + receptacle) for board-to-board connections with up to 80 parallel signals but unfortunately the performance was not satisfactory, so I won't be using them again. Are there any other interface systems for the above described purpose or ways to build a highly-parallel highspeed connection between two boards? I appreciate every kind of suggestion and help. Thanks a lot in advance. Regards, MauriceArticle: 121745
Hi - Can you tell us a bit more about your requirements? In particular: - What clock frequency are you distributing? - What are your synchronization requirements? - Do you plan to have synchronous buses or signals running between the FPGAs? What frequency are they running at? Bob Perlman Cambrian Design Works http://www.cambriandesign.com On Thu, 12 Jul 2007 17:56:19 +0200, "Geronimo Stempovski" <geronimo.stempovski@arcor.de> wrote: >Hi folks, > >I am planning to design a PCB featuring three Virtex-4 FX60 FPGAs and some >periphery. The three FPGAs are needed due to the data processing complexity >and the amount of high-speed IOs (MGTs). What I am most concerned about >right now is to find an appropriate clocking solution. > >In my opinion, there are mainly three alternatives to design the clocking >scheme: > >a) connection of the clock in a star-like topology, feeding each of the >three FPGAs with the same clock signal (which has to be possibly duplicated >by a clock buffer to generate three out of one clock reference signal, >thereby introducing additional jitter) > >b) clock in daisy-chain, feeding each of the three FPGAs with the identical >clock signal which is routed from one device to another (in terms of jitter >this is also not an optimal solution) > >c) each FPGA device is supplied with its own clock (which than can be >optimally routed to the device in short distances), but synchronization is a >major issue then > >Does anyone have sufficient experience in designing clock trees and is >willing to share his experience, comments, hints and suggestions with me? > >Thanks in advance > >Gero >Article: 121746
I am trying to implement the MiG design without a DCM, but with a testbench so I can see through a LED if the initialisation of the physical DDR SDRAM suceeds. I fixed the NGDBuild errors, it was a simple hierarchy consideration in the UCF file. Now I am getting errors concercning buffers and DCM. With a DCM, I am giving the necessary clk_0, clk_200 and the shifted clk_90 to the memory interface. I changed the outputs of the DCM from global clock buffers to local routing and now I only have 2 errors : ERROR:NgdBuild:455 - logical net 'N0' has multiple driver(s): pin G on block XST_GND with type GND, pin PAD on block N0 with type PAD ERROR:NgdBuild:924 - input pad net 'N0' is driving non-buffer primitives: pin G on block XST_GND with type GND How can I locate these errors? What part of ISE do I use to get more information? By the way, this is my first project on FPGA prototyping board, so yes I am learning all at once, hehe. It is great to see that this forum is very active, thanks again!Article: 121747
"Maurice Branson" <traubenuss@arcor.de> wrote in message news:469653f8$0$3834$9b4e6d93@newsspool4.arcor-online.net... > > designing a motherboard featuring a Virtex-4 FX140 FPGA with 24 integrated > RocketIOs (Gigabit SerDes IOs) I am now facing the problem of how to get > the > signals off the board in a most space-saving and elegant way? > Do you really need all 24 pairs? What is the DACs' sampling rate? > All 24 differential signals will be connected to some DACs outside the > motherboard What does "outside" mean precisely? /MikhailArticle: 121748
You're seriously overthinking your problem. Please indicate the data speeds you're encountering to help bound the problems in peoples' minds. Consider the lowly HDMI interface. These are ~1.8 Gbit/s signals that go over flimsy, mass-produced cables with flawless digital performance to get 1080p signals. Twisted pairs will get you to where you need to be. The speed will dictate the eye closure over distance and you *probably* are well within the appropriate operating range. For the truely demanding applications, twinax may be necessary but is probably overkill. If the eye closure is a problem for your chosen transmission media and distance, preemphasis or receiver compensation can allow your twisted pair cables to provide an open eye to the A/Ds. There are several products on the market that provide the transmit and/or recieve functions to allow multi-gigabit transmission over very cheap lines. "Maurice Branson" <traubenuss@arcor.de> wrote in message news:469653f8$0$3834$9b4e6d93@newsspool4.arcor-online.net... > Hello, > > designing a motherboard featuring a Virtex-4 FX140 FPGA with 24 integrated > RocketIOs (Gigabit SerDes IOs) I am now facing the problem of how to get > the > signals off the board in a most space-saving and elegant way? > > All 24 differential signals will be connected to some DACs outside the > motherboard to convert the signals into the analog signal domain. > > In the definition of the interface I have nearly all effective degrees of > freedom. I once learned that coaxial connections are the most appropriate > way to do so in terms of signal integrity, but with 24 differential > signals > and bidirectional connections that would mean at least 96 SMA connectors > (that takes very large board space and implies some skew problems due to > the > differences in the line lengths). > > I once used the Tyco ZDOK system (plug + receptacle) for board-to-board > connections with up to 80 parallel signals but unfortunately the > performance was not satisfactory, so I won't be using them again. Are > there > any other interface systems for the above described purpose or ways to > build > a highly-parallel highspeed connection between two boards? > > I appreciate every kind of suggestion and help. Thanks a lot in advance. > > Regards, Maurice > > >Article: 121749
Totally_Lost wrote:
>> I expect Mr Tease forgot about thousands of FPGA student boards and
>> ISE educational licenses that became worthless without VHDL/Verilog
>> support in ISE. I know more than a few students that took that hit.
>
> And I should also note, thousands of Spartan student boards and
> products. Just so Xilinx could force their obsolence and jump start
> it's new product sales following the 2002 down turn off the backs of
> students and universities. There was probably a few $M in product in
> the educational market that Xilinx killed, and didn't need to other
> than to save a few hundred thousand by omitting XC4K/Spartan support
> from XST.
> So tell me, why don't those few count?
I feel your pain, but the
fpga manufacturers would have caused
more pain by going out business.
When the synthesis vendors realized
that they weren't getting many leads
from their oem tools, they pulled the plug.
Both brands A and X handled the transition
to in-house synthesis poorly, but both have
acceptable tools today.
I believe that digital design students
would be better off not having a board at all
until they are fully competent with hdl language,
simulation and synthesis.
To learn those basics, all I need is an editor,
simulator and RTL viewer.
-- Mike Treseler
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