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"vt2001cpe" <vt2001cpe@gmail.com> wrote in message > I think you are right. However, the FIR compiler does not allow you to > use 18-bit coefficients along with 18-bit data. It doesn't seem to mind it here... Might depend on other settings though... /MikhailArticle: 121576
Hi,
kislo wrote:
> Hi i am debuggin a simple program running on the Spartan3e starter
> kit :
>
> int main()
> {
> int k = 3;
> int i = 2;
> int j = 4;
>
> i = k;
> i = j+j+k;
> while(i < 15)
> {
> j--;
> i++;
> }
> return 0;
> }
>
> The problem is that the value "k" after i step the first time is
> initialised to -1 and not 3 !! if i swap "int i = 2" with "int k = 3"
> then i = -1 and not 2 !! .. the rest of the code can be stepped thourg
> with no weird behaviour .. what can be the problem?
Make sure you compile the application with debugging symbols on (-g) and
no optimisations (-O0).
Regards,
John
Article: 121577As I think the previous posters have alluded to, designing your own fifo using the blkrams is pretty straight forward. The reason is that the blkrams are synchronous dual port memories ... pretty easy to implement fifo structures. Keep a separate word_depth_counter .... increment on writes ... decrement on reads ... leave alone on cycles with both occurring. Within the directory path /xilinx/doc/usenglish/books/docs is the document lib.pdf. Under the component for RAMB16_SN_SM is a pretty good description of the blkrams. Anyway ... good luck. -- Regards, John Retta Owner and Designer Retta Technical Consulting Inc. Colorado based Xilinx design consultant email : jretta@rtc-inc.com web : www.rtc-inc.com <bjzhangwn@gmail.com> wrote in message news:1183906196.799048.35950@z28g2000prd.googlegroups.com... >I use ise9.1 and synplify8.4.2,I use the core generator to generate a > fifo,the parameters as follow,different clock and different data bus > widths,write 16 bits and read 128 bits,now I want to use the fifo data > counts to control my logic,the fifo depths is 256 for read,and I don't > use the all fifo,if the fifo data conter reach 200,the logic must stop > writing,the logic can't write one more or less,so i need the accurate > fifo data conter,but from the datasheet I know that near empty and > full the fifo counter will be not accurate but I dno't know if the > fifo counts is accurate near 200(write and read will be not at the > same time near 200),also under reset or power on,the fifo counts is > 2(but now there are no datas in fifo,I don't know why?) >Article: 121578
On Jul 6, 12:07 pm, evansam...@charter.net wrote: > On 25-Jun-2007, "h...@hit.edu.cn" <h...@hit.edu.cn> wrote: > > > double a,b,c,d; > > int i,j,m; > > for (i=1;i<ii;i++) > > for (j=1;j<jj;j++) > > for (k=1;k<kk;k++) > > c = (a * b + c) / d; > > Depending on the accuracy and bit size. You can get upto > 160ns per calculation of 'c' using 16 bits. '(a*b+c)/d' is performed > in one clock cycle. The division operation requires a higher rate clock > to complete the operation within the aloted time. Worst case is > 2.4us for 64bit. This varies depending whether pipelining can > be used. After exchanging side emails with the OP, this is a roughly a giga- pixel plus 3D medical imaging problem. Unfortunately, the loop above is only one of a half dozen intermediate loops that must be calculated per dataset for the users application. The OPs existing algorithm requires processing the data in one particular loop order, and then different loop orders to scale, smooth and extract features from the raw 3D pixel data. Some of the OPs loops can be combined with minor changes in loop order that should be transparent, others clearly can not ... requiring the complete processing of one pass, before the next can begin. The different loop orders require different "relatively random" accesses to the memory array holding the data, forcing the application to be dependent on up to a half dozen memory read cycles per write cycle (depending on memory width and ability to cache in the FPGA). This requirement comes from the 3D image algorithm processing each pixel based on each of the nearby pixels in the 3D space ... F(x,y,x) + F(x+1,y,z) + F(x,y+1,z) + F(x,y,z+1) + ... + etc some half dozen or so memory references per resulting pixel, per pass. The algorithm specification from their sponsor is in MatLab, with implied iteration and function references in the inner loop, so some of these operations are significantly more complex than the OPs 3 variable MAC loop above. So the limiting performance of this application is the sum of some significant memory latencies, plus FP multply/square/divide/sqrt (plus a few trig) operation latencies, constrained by some hard serializations in the data sequencing. The problem probably is solvable in FPGAs with some significant risks, and is an excellent fit for SIMD/MIMD cpu architectures, such as a GPU/CELL application, with multiple independent memory arrays to obtain the needed memory bandwidth. The OP would like to do this with an off the shelf FPGA board/system with a very small budget (about 3 months of a senior designers burdened salary at western labor rates), including hardware. In a traditional commercial setting the available budget would cover neither the labor or the hardware prototype, so the students involved are looking for a solution inside this tiny budget using student labor rates and off the shelf hardware. The project sponsor will get a super bargain if these kids can pull it off. Not impossible, but certainly an interesting tough nut, and a dream real life research project for the kids either way.Article: 121579
Hi all,
We have made a bram controller connected to opb bus now we
have to connect a bram block to this controller
but there is no port to do so.Please tell us how can we achieve this?
Article: 121580On Jul 5, 6:00 am, "Jarod2...@gmail.com" <Jarod2...@gmail.com> wrote: > Recently, I download a reference design from Xilinx. Then implementate > in EDK9.1.02i, while checking the timing report,I find some fails,such > as: > > ------------------------------------------------------------------------------------ > Constraint|Check| Worst Case | Best Case | Timing | Timing > | | Slack | Achievable | Errors > | Score > ------------------------------------------------------------------------------------ > * TS_dc | SET | -0.598ns | 6.196ns | 300 | 59028 > m_1_dcm | UP | > _1_CLK0 | > _BUF = | > PERIOD | HOLD| 0.410ns | | 0 > | 0 > TIMEGRP| > "dcm_1_ | > dcm_1_CL| > K0_BUF" | > TS_dcm | > _0_dcm_0 | > _CLK2X_B| > UF HIGH | > 50% | > ///////////////////////////////////////////////////////////////////////////////////////////////////// > * TS_dcm |SET | -0.197ns | 5.262ns | 6 | 848 > _1_dcm_ |UP | > 1_CLK90_ | > BUF = P | > ERIOD |HOLD| 0.446ns | | 0 > | 0 > TIMEGRP | > "dcm_1 | > _dcm_1_ | > CLK90_B | > UF" | > TS_dcm | > _0_dcm_ | > 0_CLK2X | > _BUF P | > HASE | > 1.25 ns | > HIGH | > 50% | > ///////////////////////////////////////////////////////////////////////////////////////////////////// > during this report the best case has enough slack,but the worst case > fail the constraints.Has anybody encounter this case,and how to solve > it,any advices are welcome,thanks. Try using -timing for placer or even xplorer script. Cheers, GuruArticle: 121581
On Jul 5, 12:18 pm, Pablo <pbantu...@gmail.com> wrote: > On 5 jul, 11:36, Guru <ales.gor...@email.si> wrote: > > > > > On Jul 4, 11:13 am, Pablo <pbantu...@gmail.com> wrote: > > > > Hi everyone. > > > > I have a core to control a I/O peripheral. This core is based on a > > > FIFO to get words from a I/O bus (32 bits). But now, I want to read > > > from the FIFO and copy the words to the BRAM. I know this core runs ok > > > but I need to map the packets from FIFO to the memory so I could > > > access whenever I want. > > > > I have though in DMA to implement it. But at the moment I am not > > > sure if this solution is the best. I am using "Create and Import > > > Peripheral Wizard" from Xilinx to add this funtionality to the PowerPC > > > proccessor and access the words by a pointer. Another solution is to > > > implement the DMA manually but I am not any idea. > > > > Any suggestion. > > > > Regards Pablo > > > Pablo, > > > You probably want to make a PLB master/slave peripheral with SGDMA > > capability. Try with the wizard you mentioned, run the demo > > test_peripheral.c code. Take a look at created hw peripheral > > repository and inspect all VHDL files for included libraries versions. > > The next step is to read all the datasheets related to this peripheral > > (particulary SGDMA which is located under %EDK%\hw\XilinxProcessorIPLib > > \pcores\dma_sg_vX_XX_X\doc ). When you get the idea what it is all > > about try experimenting with a SW for a start by putting DMA engine to > > work. Then mess up with user_logic.vhd - the konwledge of VHDL is > > essential. When you get this far, you will start asking serious > > questions. > > > Cheers, > > > Guru > > Thanks. What's mean SG? SG - Scatter and Gather is a sophisticated DMA function which enables the DMA engine to run continuously by reading buffer descriptor from memory (not from registers). You probably cannot enable this function in cores created by the wizard (only simple DMA is available). Cheers, GuruArticle: 121582
On Jul 8, 10:02 pm, sfield...@base2designs.com wrote: > On Jul 6, 11:49 pm, vasile <picli...@gmail.com> wrote: > > > > > > > On Jul 2, 2:05 pm, "jjlind...@hotmail.com" <jjlind...@hotmail.com> > > wrote: > > > > Hello, I'm trying to decide to use an EPC16 or EPCS64 to program the > > > Stratix II EP2S601020C3 on my board. Can any comment which method is > > > better/faster? Altera's development kits are using the EPCS64 so I > > > leaning that direction. > > > > Thanks, > > > joe > > > The better methode looks M25P64 without any compressed code inside and > > fastest serial solution. > > Using another microcontroller just for configuration (and not other > > purposes) > > seems to me a weird option even if harware cost less than $2 and > > programming/debugging/PCB design another $20. > > > Vasile > > No more weird than using a dedicated CPLD, which is a popular option > for configuring an FPGA from parallel NOR flash memory. There is no > way to directly configure an Altera FPGA from an M25P64 Strange. I believed the EPCS64 and M25P64 are pin to pin and programming algorithm compatible... (unlike some > Xilinx FPGAs), so I assume that the proposed solution assumes a > microprocessor with a spare SPI port, or having the microprocessor bit > bang the flash SPI port. > Steve- Hide quoted text - > > - Show quoted text -Article: 121583
On Fri, 06 Jul 2007 11:25:05 -0700, kislo <kislo02@student.sdu.dk>
wrote:
>Hi i am debuggin a simple program running on the Spartan3e starter
>kit :
>
>int main()
>{
> int k = 3;
> int i = 2;
> int j = 4;
>
> i = k;
> i = j+j+k;
[...]
>The problem is that the value "k" after i step the first time is
>initialised to -1 and not 3 !! if i swap "int i = 2" with "int k = 3"
>then i = -1 and not 2 !! .. the rest of the code can be stepped thourg
>with no weird behaviour .. what can be the problem?
No problem: the compiler knows the value of the constants in "k" or "i",
and uses the very basic "constant folding" optimisation, so it never
needs to load "k" or "i" with the initial values.
The other post suggested turning the optimisations off; or it may be
worth declaring "i" or "k" to be "volatile" to force the to use them (in
case they were actually registers in hardware devices)
- Brian
Article: 121584On 9 jul, 11:24, Guru <ales.gor...@email.si> wrote: > On Jul 5, 12:18 pm, Pablo <pbantu...@gmail.com> wrote: > > > > > On 5 jul, 11:36, Guru <ales.gor...@email.si> wrote: > > > > On Jul 4, 11:13 am, Pablo <pbantu...@gmail.com> wrote: > > > > > Hi everyone. > > > > > I have a core to control a I/O peripheral. This core is based on a > > > > FIFO to get words from a I/O bus (32 bits). But now, I want to read > > > > from the FIFO and copy the words to the BRAM. I know this core runs ok > > > > but I need to map the packets from FIFO to the memory so I could > > > > access whenever I want. > > > > > I have though in DMA to implement it. But at the moment I am not > > > > sure if this solution is the best. I am using "Create and Import > > > > Peripheral Wizard" from Xilinx to add this funtionality to the PowerPC > > > > proccessor and access the words by a pointer. Another solution is to > > > > implement the DMA manually but I am not any idea. > > > > > Any suggestion. > > > > > Regards Pablo > > > > Pablo, > > > > You probably want to make a PLB master/slave peripheral with SGDMA > > > capability. Try with the wizard you mentioned, run the demo > > > test_peripheral.c code. Take a look at created hw peripheral > > > repository and inspect all VHDL files for included libraries versions. > > > The next step is to read all the datasheets related to this peripheral > > > (particulary SGDMA which is located under %EDK%\hw\XilinxProcessorIPLib > > > \pcores\dma_sg_vX_XX_X\doc ). When you get the idea what it is all > > > about try experimenting with a SW for a start by putting DMA engine to > > > work. Then mess up with user_logic.vhd - the konwledge of VHDL is > > > essential. When you get this far, you will start asking serious > > > questions. > > > > Cheers, > > > > Guru > > > Thanks. What's mean SG? > > SG - Scatter and Gather is a sophisticated DMA function which enables > the DMA engine to run continuously by reading buffer descriptor from > memory (not from registers). You probably cannot enable this function > in cores created by the wizard (only simple DMA is available). > > Cheers, > > Guru Thanks again. Regards PabloArticle: 121585
"Hofjue" <hofjue@googlemail.com> wrote in message news:1183468984.304426.183320@o61g2000hsh.googlegroups.com... > On 3 Jul., 15:11, Zara <me_z...@dea.spamcon.org> wrote: >> On Tue, 03 Jul 2007 05:07:28 -0700, hofmann.juer...@pc-future.de >> wrote: >> >> >> >> >Hi all, >> >> >I'm developing a multicore system with up to four Microblaze cores. >> >Now I'm searching for a solution to inform the cores about e.g. >> >messages with a software interrupt. That means, one core writes a >> >message in the shared memory and after that it informs the other cores >> >to read the message. >> >My first idea was to use a GPIO element with interrupts switched on. I >> >tried to write to the element when the message was posted . But there >> >is the problem, that the interrupt is only activated when the data >> >will be changed from outside the microblaze core. >> >So my new idea is to use two GPIO elements and link them together. But >> >it doesn't run and I think, that the problem is the linking of the >> >ports. >> >Has anybody an idea, which ports I have to link (GPIO_d_out or GPIO_IO >> >with GPIO_in or something else) or an idea how to implement software >> >interrupts in such a combination? >> >> >I've got a Xilinx ML410 evaluation board. >> >> >Thank you for your help. >> >> What abiout using FSLs to communicate between processors? They have a >> FIFO with somne capacity, they generate interrupts... it is the >> firmware implem,entation of a queue. >> >> Zara > > The problem is, that I have to link every core with each other. A > Microblaze core only have eight FSL ports so I could only combine > three cores. > But I have to check the interrupt idea, perhaps I can use the > interrupt signal in my global interrupt controller and all cores react > to the interrupt. > Hi, Each FSL port has one input connection (slave) and one output connection (master). So with 8 FSL ports, you can connect from one MicroBlaze to eight other MicroBlazes. This should be enough for your system. Göran BilskiArticle: 121586
I am using the coregen multiplier. I pre-set the parameters to make the o output latency is 0. Why I simulate it in Modelsim, the output delay time is quite long. Thanks.Article: 121587
Hi, I think it would be hard to find an ARM core that isn't harvard architecture. Harvard architecture means that the pathways from the CPU are seperate for instruction and data. It doesn't mean that the actual memory needs to be two seperate memories. In fact the common usage is that the memory is the same. What Austin was referring to was that Altera went from a different architecture/ISA when they moved from NIOS-I to NIOS-II. All programs needed to be recompiled for NIOS-II and assembler code had to manually be translated to NIOS-II assembler instructions. MicroBlaze has stayed with the same ISA and all new features are optional. You can take object-code from the first version of MicroBlaze and run it the latest version (and in the future versions). Göran Bilski "Nico Coesel" <nico@puntnl.niks> wrote in message news:468e6c92.72808603@news.planet.nl... > austin <austin@xilinx.com> wrote: > >>Mike, >> >>Easy. Just introduce a "new and improved" incompatible version, and >>remove support for the old one. >> >>Another way of saying "the original soft processor was so bad, that we >>redesigned it..." >> >>Thankfully, MicroBlaze(tm) soft processors followed the Harvard RISC >>architecture, and we got it right the first time. > > Where I live harvard architecture means exit... Having a seperated > code and data area causes a lot of overhead in software because each > pointer needs to be extended with the memory type it is pointing to. > > It also makes the CPU more complicated because you need twice the > amount of memory move instructions which wastes opcode combinations > which could have been used for other usefull instructions for > functions that usually take several instructions (like bit set, clear, > and, or, xor). > > And why not use an ARM core? That would have made a lot more sense > than creating something completely new. > > -- > Reply to nico@nctdevpuntnl (punt=.) > Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 121588
Hi Folks, have the following problem and couldn't found out yet how to solve it: I have a clock input CLK_A and a DCM. I use CLKO and CLKFX outputs of DCM. CLKFX is configured for 4X CLK_A. I define period constraint on CLK_A input port. And I see this constraint will be translated to both outputs CLK0 and CLKFX respectively. But timing analyzer does not analyze CLKFX output and its fanout logic. It just shows something like: " 0 items analyzed, 0 timing errors". I thought it should be enough to specify input clock frequency with TNM_NET and so on like: NET "CLK_A" TNM_NET = "CLK_A"; TIMESPEC "TS_CLK_A" = PERIOD "TN_CLK_A" xx ns; Any hint is appreciated. Thanx MetinArticle: 121589
hi all, i wanted to do the post place and route timing simulation in modelsim. i have got the files form the xilinx ise and i copied both *_timesim.sdf and *_timesim.vho file into the RTL folder for my simulation. what else i need to have for the post place and route timing simulation. i have written a test bench for my design. do i need to edit it for the post p&r timing simulation. when i need to select *.sdf file (i think during the simulation). i need to know what files i need for the timing simulation and steps that are followd for the simulation. i have gone through the appilcation notes but still i feel i am lost some where. regards srikArticle: 121590
On Jul 8, 4:08 am, "cwoodring" <cwoodr...@cox.net> wrote: > Hi, > I've been working on a simulink model built using the Xilinx Blockset to > try to verify the function of an interplation filter made from the MacFir > Core. The full working VHDL version of the complete data path where the > input data goes into a fifo and is read out to the filter as it is ready for > data. The filter does a simple up by 2 interpolation and the output data is > written to another fifo for eventual output. This filter actually handles 64 > channels. The input rate for the data is 100KHz and the Output rate is to be > 200KHz. > In my simulink model I read the data for a input signal consisting of 2 > sine waves, one well within the filters passband and one in the stop band, > from the MATLAB workspace. I then multiplex that same data to 28 channels > and feed the filter which is intantiated in the Simulink model as a black > box as per Matlab's help file for inserting a Xilinx core into a model. > I've had a lot of confusion about sample rates and how to deal with them > in Simulink, but I think I'm finally getting the hang of them. The output > rate is 2x the input rate for the complete system - fifo in to fifo out but > the filter runs very fast compared to the actual data rate in and out. > The Modelsim simulation of the whole VHDL coded system seems to be > working- I get 2 samples out for every one in on all the channels and the > data is written to the output fifos ok. Since the data is fixed point I > wanted to verify my output values with what I get in the Simulink model > which uses the fixed point blockset etc. The biggest issue I have is that > the Modelsim simulation goes very fast and outputs data from the filter > every usec or less while the Simulink model using the Modelsim output block > takes milliseconds to produce an output data. It does give me 2 values for > every one in and the filter model appears to be working ok, but the clocking > of the whole model is running at a sample rate of 100KHz. . I use modelsim > under the control of Simulink to run the simulation and the fastest clock in > the simulation is 200KHz. The system clock in the "real" VHDL system is > 80MHz. When I try to increase the system clock in the SystemGenerator block > to anything faster than 1MHz I get some error about an unresolved Boolean > value and the simulation doesn't run. > Has anyone matched what an actual synthesizable system to a Simulink > model at the actual clock rates used in the VHDL simulation? When I look at > all the example files for simulink it seems they always use sample rates of > 1sec which seems ridiculous when trying to match clock rates in an FPGA > system. Am I really off the mark here or to I just have to run my Simulink > model for 45 minutes to match what the VHDL model gives me in 2 seconds? > > Totally dazed and confused, > > CTW There are different ways to handle the clocks in System Generator. It can be confusing. If your real clock is going to be 80MHz, create a variable T_system_clock = 1/80e6 in your Matlab workspace. Use this variable in your System Generator token. Now make sure that the clock rates in your system are all integer multiples of this clock. For example, if your FIR input runs at 100kHz, set the sample period of the filter = (1/100e3)/T_system_clock. This will be an integer multiple of the system clock. Now in the Simulink 'Simulation Stop Time' you put N*T_system_clock where N is the number of clock cycles which you want to run the simulation for. The times shown in a scope window for example will match the actual time related to the 80MHz clock in hardware. Basically the clock that is specified in the System Generator token must be equal to the fastest clock in your system, the slower clocks will all be generated with CE's by System Generator and you will not get errors about clocks that are not integer clock cycles of the system clock. One more thing, use the FIR Compiler and not the MAC FIR as it will be replaced by the FIR Compiler. Hope this helpsArticle: 121591
Does anyone know what the following error in ModelSIM means?
# Loading work.dsss_modem_cosim(structural)
# Loading work.prbs(behavioral)
# ** Error: bad arg: "48522
# Executing ONERROR command at macro ./dsss_modem_cosim_cw.tcl line
128
Below are lines 116-134 of the TCL script which the error refers to:
if {$xlcosim_stat==0} {
onerror { global xlcosim_stat ; set xlcosim_stat 9; resume }
onElabError { global xlcosim_stat ; set xlcosim_stat 9; resume }
vsim -t ps work.dsss_modem_cosim_cw -title {System Generator Co-
Simulation (from block "ModelSim")}
update
if {$xlcosim_stat==0} {
onerror { global xlcosim_stat ; set xlcosim_stat 9; resume }
if [llength [find signal black_box_clk]] {} else {global
xlcosim_stat ; set xlcosim_stat 9 }
}
if {$xlcosim_stat==0} {
openWave
}
}
puts $cid $xlcosim_stat
flush $cid
if {$xlcosim_stat!=0} {
close $cid
}
Any help would be appreciated...
Article: 121592o.k solved.....no botherArticle: 121593
ekavirsrikanth@gmail.com wrote:
> i wanted to do the post place and route timing simulation in modelsim.
I would defer learning how to do this until
I had a working functional simulation
and static timing analysis.
These are much more useful skills.
The odds of my new code having a bug are high.
The odds that synthesis made a mistake are low.
-- Mike Treseler
Article: 121594Metin wrote: > o.k solved.....no bother And the solution was ...?Article: 121595
I'm trying to get some files of the CF in a XUP board with a
VirtexII-pro FPGA, the problem is that I use 'opb_sysace' with xilfatfs
library. When I compile the libraries I get the next error:
Running DRCs for OSes, Drivers and Libraries ...
LWIP DRC...
XEmac Instances : 1
ERROR:MDT - ERROR FROM TCL:- xilfatfs () - Sysace HW module not present
or not
accessible from this processor. FATfs cannot be used without this module
ERROR:MDT - Error while running DRC for processor ppc405_0...
make: *** [ppc405_0/lib/libxil.a] Error 2
Nevertheless in software platform settings I have checked xilfatfs for
ppc405_0 processor and the core opb_sysace is present. I don't know what
to do. Thanks in advance.
Article: 121596
>Does anyone know what the following error in ModelSIM means?
>
># Loading work.dsss_modem_cosim(structural)
># Loading work.prbs(behavioral)
># ** Error: bad arg: "48522
># Executing ONERROR command at macro ./dsss_modem_cosim_cw.tcl line
>128
>
>Below are lines 116-134 of the TCL script which the error refers to:
>
>if {$xlcosim_stat==0} {
> onerror { global xlcosim_stat ; set xlcosim_stat 9; resume }
> onElabError { global xlcosim_stat ; set xlcosim_stat 9; resume }
> vsim -t ps work.dsss_modem_cosim_cw -title {System Generator Co-
>Simulation (from block "ModelSim")}
> update
> if {$xlcosim_stat==0} {
> onerror { global xlcosim_stat ; set xlcosim_stat 9; resume }
> if [llength [find signal black_box_clk]] {} else {global
>xlcosim_stat ; set xlcosim_stat 9 }
>}
> if {$xlcosim_stat==0} {
> openWave
> }
>}
>
>puts $cid $xlcosim_stat
>flush $cid
>if {$xlcosim_stat!=0} {
> close $cid
>}
>
>Any help would be appreciated...
>
>
Try:
puts $cid "$xlcosim_stat"
If that doesn't work, you need to be sure that 'cid' is the ChannelId of a
correctly opened file.
The error might refer to the 'flush' command, which is probably not needed
as the preceeding 'puts' should emit a newline satisfactorily.
Article: 121597
naude.jaco@gmail.com wrote:
> # Loading work.dsss_modem_cosim(structural)
> # Loading work.prbs(behavioral)
> # ** Error: bad arg: "48522
> # Executing ONERROR command at macro ./dsss_modem_cosim_cw.tcl line
> Any help would be appreciated...
Talk to the author of
"dsss_modem_cosim_cw.tcl"
or work manually from the vsim command line.
-- Mike Treseler
Article: 121598Jarek Rozanski wrote: > Hi, > > Does anyone have experience with Altium LiveDesign (Xilinx Spartan-3 > XC3S1000) ? How does it perform with ISE WebPack, are there any odd > issues with it? Any comment will be appreciated. > > I would like to use it for my CPU project. Size of FPGA is more than I > need currently but I don't mind getting bigger device :) The Altium tools are all very well in principle, but as soon as you start working out of their box things can get difficult. I presume their IP should plug and play as advertised, but as soon as you design some custom logic of your own it's a different ball game. If you get timing/routing/constraint problems you're going to have to dig into the Altera/Xilinx tools that are running in the background. IMHO. Nial.Article: 121599
Hi, my setup is as follows: 1) DSP ADSP-21065L 2) Xilinx xc3s250 3) Intel JS2BF320J3D Flash I am able to have the DSP load itself from flash but after it's done loading, I would like the DSP to tell the FPGA to load itself from the same flash. They will be sharing address and data lines and cannot operate at the same time. I am wondering if there is a way for the DSP to tell the FPGA to load itself from Flash. Is there a special pin on the FPGA for that. Thanks. Amish
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