Messages from 121625

Article: 121625
Subject: Re: DDR SDRAM simulation model, ML300, Infineon
From: Sean Durkin <news_jul07@durkin.de>
Date: Tue, 10 Jul 2007 07:33:55 +0200
Links: << >> << T >> << A >>

chakra wrote:
> Also i have a similar DDR SDRAM simulation model. this part is
> manufactured by Micron MT46V32M8TG-75 and similar 256Mb 8bits*32mil =
> 32 MB. is it advisable to use this simulation model in the place of
> the infineon? the DQ, DQS, DM, ADDR, col are all same for the two.
The basic behaviour of DRAM is specified in a JEDEC-standard, so
theoretically all the chips, regardless of manufacturer, should behave
the same (as long as they have the same size, speed grade and so on).

So yes, you can use the Micron model for your simulations. Micron's
models are the best anyway, very detailed, very verbose and available as
Veerilog source. Samsung only offers precompiled models, I haven't used
those so can't comment on how how they are.

HTH,
Sean

-- 
My email address is only valid until the end of the month.
Try figuring out what the address is going to be after that...

Article: 121626
Subject: configuring vertex4 FPGA
From: archana <ramaarchana@gmail.com>
Date: Tue, 10 Jul 2007 00:14:54 -0700
Links: << >> << T >> << A >>

hi

i want to configure a XC4 series of  vertex 4 FPGA using a micro
controller. which bitgen file is to be ussed for default
configuration.


Is a title declaration generation for the verterx bitgen files.

Article: 121627
Subject: Re: Here you have the 'system.hms'
From: Marco Albero <periket2000@ya.com>
Date: Tue, 10 Jul 2007 10:14:55 +0200
Links: << >> << T >> << A >>

Marco Albero wrote:
> I'm trying to get some files of the CF in a XUP board with a 
> VirtexII-pro FPGA, the problem is that I use 'opb_sysace' with xilfatfs 
> library. When I compile the libraries I get the next error:
> 
> Running DRCs for OSes, Drivers and Libraries ...
> LWIP DRC...
> XEmac Instances : 1
> ERROR:MDT - ERROR FROM TCL:- xilfatfs () - Sysace HW module not present 
> or not
>    accessible from this processor. FATfs cannot be used without this module
> 
> ERROR:MDT - Error while running DRC for processor ppc405_0...
> 
> make: *** [ppc405_0/lib/libxil.a] Error 2
> 
> Nevertheless in software platform settings I have checked xilfatfs for 
> ppc405_0 processor and the core opb_sysace is present. I don't know what 
> to do. Thanks in advance.

  PARAMETER VERSION = 2.1.0


  PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I
  PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O
  PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = 
fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I
  PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = 
fpga_0_SysACE_CompactFlash_SysACE_MPA, VEC = [6:0], DIR = O
  PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = 
fpga_0_SysACE_CompactFlash_SysACE_MPD, VEC = [15:0], DIR = IO
  PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = 
fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O
  PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = 
fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O
  PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = 
fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O
  PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = 
fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I
  PORT fpga_0_Ethernet_MAC_slew1_pin = net_vcc, DIR = O
  PORT fpga_0_Ethernet_MAC_slew2_pin = net_vcc, DIR = O
  PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = 
fpga_0_Ethernet_MAC_PHY_rst_n, DIR = O
  PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs, 
DIR = I
  PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col, 
DIR = I
  PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = 
fpga_0_Ethernet_MAC_PHY_tx_data, DIR = O, VEC = [3:0]
  PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = 
fpga_0_Ethernet_MAC_PHY_tx_en, DIR = O
  PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = 
fpga_0_Ethernet_MAC_PHY_tx_clk, DIR = I
  PORT fpga_0_Ethernet_MAC_PHY_tx_er_pin = 
fpga_0_Ethernet_MAC_PHY_tx_er, DIR = O
  PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = 
fpga_0_Ethernet_MAC_PHY_rx_er, DIR = I
  PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = 
fpga_0_Ethernet_MAC_PHY_rx_clk, DIR = I
  PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv, DIR = I
  PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = 
fpga_0_Ethernet_MAC_PHY_rx_data, DIR = I, VEC = [3:0]
  PORT fpga_0_Ethernet_MAC_PHY_Mii_clk_pin = 
fpga_0_Ethernet_MAC_PHY_Mii_clk, DIR = IO
  PORT fpga_0_Ethernet_MAC_PHY_Mii_data_pin = 
fpga_0_Ethernet_MAC_PHY_Mii_data, DIR = IO
  PORT fpga_0_DDR_SDRAM_64Mx64_DDR_Clk_pin = 
fpga_0_DDR_SDRAM_64Mx64_DDR_Clk, DIR = O, VEC = [0:3]
  PORT fpga_0_DDR_SDRAM_64Mx64_DDR_Clkn_pin = 
fpga_0_DDR_SDRAM_64Mx64_DDR_Clkn, DIR = O, VEC = [0:2]
  PORT fpga_0_DDR_SDRAM_64Mx64_DDR_Addr_pin = 
fpga_0_DDR_SDRAM_64Mx64_DDR_Addr, DIR = O, VEC = [0:12]
  PORT fpga_0_DDR_SDRAM_64Mx64_DDR_BankAddr_pin = 
fpga_0_DDR_SDRAM_64Mx64_DDR_BankAddr, DIR = O, VEC = [0:1]
  PORT fpga_0_DDR_SDRAM_64Mx64_DDR_CASn_pin = 
fpga_0_DDR_SDRAM_64Mx64_DDR_CASn, DIR = O
  PORT fpga_0_DDR_SDRAM_64Mx64_DDR_CKE_pin = 
fpga_0_DDR_SDRAM_64Mx64_DDR_CKE, DIR = O, VEC = [0:0]
  PORT fpga_0_DDR_SDRAM_64Mx64_DDR_CSn_pin = 
fpga_0_DDR_SDRAM_64Mx64_DDR_CSn, DIR = O, VEC = [0:0]
# PORT fpga_0_DDR_SDRAM_64Mx64_DDR_CKE_pin = 
fpga_0_DDR_SDRAM_64Mx64_DDR_CKE, DIR = OUT, VEC = [0:1]
# PORT fpga_0_DDR_SDRAM_64Mx64_DDR_CSn_pin = 
fpga_0_DDR_SDRAM_64Mx64_DDR_CSn, DIR = OUT, VEC = [0:1]
  PORT fpga_0_DDR_SDRAM_64Mx64_DDR_RASn_pin = 
fpga_0_DDR_SDRAM_64Mx64_DDR_RASn, DIR = O
  PORT fpga_0_DDR_SDRAM_64Mx64_DDR_WEn_pin = 
fpga_0_DDR_SDRAM_64Mx64_DDR_WEn, DIR = O
  PORT fpga_0_DDR_SDRAM_64Mx64_DDR_DM_pin = 
fpga_0_DDR_SDRAM_64Mx64_DDR_DM, DIR = O, VEC = [0:7]
  PORT fpga_0_DDR_SDRAM_64Mx64_DDR_DQS_pin = 
fpga_0_DDR_SDRAM_64Mx64_DDR_DQS, DIR = IO, VEC = [0:7]
  PORT fpga_0_DDR_SDRAM_64Mx64_DDR_DQ_pin = 
fpga_0_DDR_SDRAM_64Mx64_DDR_DQ, DIR = IO, VEC = [0:63]
  PORT sys_clk_pin = dcm_clk_s, DIR = I
  PORT sys_rst_pin = sys_rst_s, DIR = I
# tie unsued pins
  PORT fpga_0_DDR_SDRAM_64Mx64_DDR_ADDR13_pin = net_gnd, DIR = O
  PORT FORCE_VREF_IN = vref_fix, DIR = I, VEC = [3:0]
  PORT FORCE_VREF_OUT = vref_fix, DIR = O, VEC = [3:0]

BEGIN ppc405
  PARAMETER INSTANCE = ppc405_0
  PARAMETER HW_VER = 2.00.c
  BUS_INTERFACE DPLB = plb
  BUS_INTERFACE IPLB = plb
  BUS_INTERFACE JTAGPPC = jtagppc_0_0
  PORT PLBCLK = sys_clk_s
  PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ
  PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ
  PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ
  PORT RSTC405RESETCHIP = RSTC405RESETCHIP
  PORT RSTC405RESETCORE = RSTC405RESETCORE
  PORT RSTC405RESETSYS = RSTC405RESETSYS
  PORT CPMC405CLOCK = sys_clk_s
END

BEGIN ppc405
  PARAMETER INSTANCE = ppc405_1
  PARAMETER HW_VER = 2.00.c
  BUS_INTERFACE JTAGPPC = jtagppc_0_1
END

BEGIN jtagppc_cntlr
  PARAMETER INSTANCE = jtagppc_0
  PARAMETER HW_VER = 2.00.a
  BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
  BUS_INTERFACE JTAGPPC1 = jtagppc_0_1
END

BEGIN proc_sys_reset
  PARAMETER INSTANCE = reset_block
  PARAMETER HW_VER = 1.00.a
  PARAMETER C_EXT_RESET_HIGH = 0
  PORT Ext_Reset_In = sys_rst_s
  PORT Slowest_sync_clk = sys_clk_s
  PORT Chip_Reset_Req = C405RSTCHIPRESETREQ
  PORT Core_Reset_Req = C405RSTCORERESETREQ
  PORT System_Reset_Req = C405RSTSYSRESETREQ
  PORT Rstc405resetchip = RSTC405RESETCHIP
  PORT Rstc405resetcore = RSTC405RESETCORE
  PORT Rstc405resetsys = RSTC405RESETSYS
  PORT Bus_Struct_Reset = sys_bus_reset
  PORT Dcm_locked = dcm_1_lock
END

BEGIN plb_v34
  PARAMETER INSTANCE = plb
  PARAMETER HW_VER = 1.02.a
  PARAMETER C_DCR_INTFCE = 0
  PARAMETER C_EXT_RESET_HIGH = 1
  PORT SYS_Rst = sys_bus_reset
  PORT PLB_Clk = sys_clk_s
END

BEGIN opb_sysace
  PARAMETER INSTANCE = SysACE_CompactFlash
  PARAMETER HW_VER = 1.00.b
  PARAMETER C_MEM_WIDTH = 16
  PARAMETER C_BASEADDR = 0x78060000
  PARAMETER C_HIGHADDR = 0x7806ffff
  BUS_INTERFACE SOPB = opb
  PORT OPB_Clk = sys_clk_s
  PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK
  PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA
  PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD
  PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN
  PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN
  PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN
  PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
END

BEGIN opb_v20
  PARAMETER INSTANCE = opb
  PARAMETER HW_VER = 1.10.b
  PARAMETER C_EXT_RESET_HIGH = 1
  PORT SYS_Rst = sys_bus_reset
  PORT OPB_Clk = sys_clk_s
END

BEGIN plb2opb_bridge
  PARAMETER INSTANCE = plb2opb
  PARAMETER HW_VER = 1.01.a
  PARAMETER C_DCR_INTFCE = 0
  PARAMETER C_NUM_ADDR_RNG = 1
  PARAMETER C_RNG0_BASEADDR = 0x84000000
  PARAMETER C_RNG0_HIGHADDR = 0x8400ffff
  BUS_INTERFACE SPLB = plb
  BUS_INTERFACE MOPB = opb
  PORT PLB_Clk = sys_clk_s
  PORT OPB_Clk = sys_clk_s
END

BEGIN opb_uartlite
  PARAMETER INSTANCE = RS232_Uart_1
  PARAMETER HW_VER = 1.00.b
  PARAMETER C_BAUDRATE = 9600
  PARAMETER C_DATA_BITS = 8
  PARAMETER C_ODD_PARITY = 0
  PARAMETER C_USE_PARITY = 0
  PARAMETER C_CLK_FREQ = 100000000
  PARAMETER C_BASEADDR = 0x84000000
  PARAMETER C_HIGHADDR = 0x84000fff
  BUS_INTERFACE SOPB = opb
  PORT OPB_Clk = sys_clk_s
  PORT RX = fpga_0_RS232_Uart_1_RX
  PORT TX = fpga_0_RS232_Uart_1_TX
END

BEGIN plb_ethernet
  PARAMETER INSTANCE = Ethernet_MAC
  PARAMETER HW_VER = 1.01.a
  PARAMETER C_DMA_PRESENT = 1
  PARAMETER C_IPIF_FIFO_DEPTH = 32768
  PARAMETER C_PLB_CLK_PERIOD_PS = 10000
  PARAMETER C_BASEADDR = 0x84010000
  PARAMETER C_HIGHADDR = 0x8401ffff
  BUS_INTERFACE SPLB = plb
  PORT PLB_Clk = sys_clk_s
  PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n
  PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs
  PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col
  PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data
  PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en
  PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk
  PORT PHY_tx_er = fpga_0_Ethernet_MAC_PHY_tx_er
  PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er
  PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk
  PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv
  PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data
  PORT PHY_Mii_clk = fpga_0_Ethernet_MAC_PHY_Mii_clk
  PORT PHY_Mii_data = fpga_0_Ethernet_MAC_PHY_Mii_data
END

BEGIN plb_ddr
  PARAMETER INSTANCE = DDR_SDRAM_64Mx64
  PARAMETER HW_VER = 1.11.a
  PARAMETER C_PLB_CLK_PERIOD_PS = 10000
  PARAMETER C_INCLUDE_BURST_CACHELN_SUPPORT = 0
# For the single Rank parts, only use a single bank.
# You also need to change the sdram_cke,_csn to a single
# bit wide and remove the extra pin from the .ucf file
# (remove the (1) pin)
  PARAMETER C_NUM_BANKS_MEM = 1
# PARAMETER C_NUM_BANKS_MEM = 2
  PARAMETER C_ECC_DEFAULT_ON = 0
  PARAMETER C_REG_DIMM = 0
  PARAMETER C_DDR_TMRD = 10000
  PARAMETER C_DDR_TWR = 15000
  PARAMETER C_DDR_TRAS = 60000
  PARAMETER C_DDR_TRC = 90000
  PARAMETER C_DDR_TRFC = 100000
  PARAMETER C_DDR_TRCD = 30000
  PARAMETER C_DDR_TRRD = 20000
  PARAMETER C_DDR_TRP = 30000
  PARAMETER C_DDR_TREFC = 70300000
  PARAMETER C_DDR_AWIDTH = 13
  PARAMETER C_DDR_COL_AWIDTH = 9
# PARAMETER C_DDR_COL_AWIDTH = 10
  PARAMETER C_DDR_BANK_AWIDTH = 2
  PARAMETER C_NUM_CLK_PAIRS = 4
# Cas latency of 3 of smaller DDRs
  PARAMETER C_DDR_CAS_LAT = 2
# For a single rank, there is only one memory
# space
  PARAMETER C_MEM0_BASEADDR = 0x00000000
  PARAMETER C_MEM0_HIGHADDR = 0x07ffffff
# PARAMETER C_MEM0_BASEADDR = 0x00000000
# PARAMETER C_MEM0_HIGHADDR = 0x0fffffff
# PARAMETER C_MEM1_BASEADDR = 0x10000000
# PARAMETER C_MEM1_HIGHADDR = 0x1fffffff
  PARAMETER C_DDR_DWIDTH = 64
  BUS_INTERFACE SPLB = plb
  PORT PLB_Clk = sys_clk_s
  PORT DDR_Addr = fpga_0_DDR_SDRAM_64Mx64_DDR_Addr
  PORT DDR_BankAddr = fpga_0_DDR_SDRAM_64Mx64_DDR_BankAddr
  PORT DDR_CASn = fpga_0_DDR_SDRAM_64Mx64_DDR_CASn
  PORT DDR_CKE = fpga_0_DDR_SDRAM_64Mx64_DDR_CKE
  PORT DDR_CSn = fpga_0_DDR_SDRAM_64Mx64_DDR_CSn
  PORT DDR_RASn = fpga_0_DDR_SDRAM_64Mx64_DDR_RASn
  PORT DDR_WEn = fpga_0_DDR_SDRAM_64Mx64_DDR_WEn
  PORT DDR_DM = fpga_0_DDR_SDRAM_64Mx64_DDR_DM
  PORT DDR_DQS = fpga_0_DDR_SDRAM_64Mx64_DDR_DQS
  PORT DDR_DQ = fpga_0_DDR_SDRAM_64Mx64_DDR_DQ
  PORT DDR_Clk = fpga_0_DDR_SDRAM_64Mx64_DDR_Clk
  PORT DDR_Clkn = fpga_0_DDR_SDRAM_64Mx64_DDR_Clkn
  PORT Clk90_in = clk_90_s
  PORT Clk90_in_n = clk_90_n_s
  PORT PLB_Clk_n = sys_clk_n_s
  PORT DDR_Clk90_in = ddr_clk_90_s
  PORT DDR_Clk90_in_n = ddr_clk_90_n_s
END

BEGIN plb_bram_if_cntlr
  PARAMETER INSTANCE = plb_bram_if_cntlr_1
  PARAMETER HW_VER = 1.00.b
  PARAMETER c_plb_clk_period_ps = 10000
  PARAMETER c_baseaddr = 0xfffe0000
  PARAMETER c_highaddr = 0xffffffff
  BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
  BUS_INTERFACE SPLB = plb
  PORT PLB_Clk = sys_clk_s
END

BEGIN bram_block
  PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
  PARAMETER HW_VER = 1.00.a
  PARAMETER C_MEMSIZE = 131072
  PARAMETER C_PORT_DWIDTH = 64
  PARAMETER C_NUM_WE = 8
  PARAMETER C_PORT_AWIDTH = 13
  BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
END

BEGIN dcm_module
  PARAMETER INSTANCE = dcm_0
  PARAMETER HW_VER = 1.00.a
  PARAMETER C_CLK0_BUF = TRUE
  PARAMETER C_CLK180_BUF = TRUE
  PARAMETER C_CLK270_BUF = TRUE
  PARAMETER C_CLK90_BUF = TRUE
  PARAMETER C_CLKIN_PERIOD = 10.000
  PARAMETER C_CLK_FEEDBACK = 1X
  PARAMETER C_EXT_RESET_HIGH = 1
  PORT CLKIN = dcm_clk_s
  PORT CLK0 = sys_clk_s
  PORT CLK90 = clk_90_s
  PORT CLK180 = sys_clk_n_s
  PORT CLK270 = clk_90_n_s
  PORT CLKFB = sys_clk_s
  PORT RST = net_gnd
  PORT LOCKED = dcm_0_lock
END

BEGIN dcm_module
  PARAMETER INSTANCE = dcm_1
  PARAMETER HW_VER = 1.00.a
  PARAMETER C_CLK0_BUF = TRUE
  PARAMETER C_CLK270_BUF = TRUE
  PARAMETER C_CLK90_BUF = TRUE
  PARAMETER C_CLKIN_PERIOD = 10.000000
  PARAMETER C_CLK_FEEDBACK = 1X
  PARAMETER C_EXT_RESET_HIGH = 0
  PORT CLKIN = clk_90_s
  PORT CLK90 = ddr_clk_90_s
  PORT CLK270 = ddr_clk_90_n_s
  PORT CLK0 = dcm_1_FB
  PORT CLKFB = dcm_1_FB
  PORT RST = dcm_0_lock
  PORT LOCKED = dcm_1_lock
END

Article: 121628
Subject: Re: And here the 'system.mss'
From: Marco Albero <periket2000@ya.com>
Date: Tue, 10 Jul 2007 10:15:56 +0200
Links: << >> << T >> << A >>

Marco Albero wrote:
> I'm trying to get some files of the CF in a XUP board with a 
> VirtexII-pro FPGA, the problem is that I use 'opb_sysace' with xilfatfs 
> library. When I compile the libraries I get the next error:
> 
> Running DRCs for OSes, Drivers and Libraries ...
> LWIP DRC...
> XEmac Instances : 1
> ERROR:MDT - ERROR FROM TCL:- xilfatfs () - Sysace HW module not present 
> or not
>    accessible from this processor. FATfs cannot be used without this module
> 
> ERROR:MDT - Error while running DRC for processor ppc405_0...
> 
> make: *** [ppc405_0/lib/libxil.a] Error 2
> 
> Nevertheless in software platform settings I have checked xilfatfs for 
> ppc405_0 processor and the core opb_sysace is present. I don't know what 
> to do. Thanks in advance.

  PARAMETER VERSION = 2.2.0


BEGIN OS
  PARAMETER OS_NAME = standalone
  PARAMETER OS_VER = 1.00.a
  PARAMETER PROC_INSTANCE = ppc405_0
  PARAMETER STDIN = RS232_Uart_1
  PARAMETER STDOUT = RS232_Uart_1
END

BEGIN OS
  PARAMETER OS_NAME = standalone
  PARAMETER OS_VER = 1.00.a
  PARAMETER PROC_INSTANCE = ppc405_1
END


BEGIN PROCESSOR
  PARAMETER DRIVER_NAME = cpu_ppc405
  PARAMETER DRIVER_VER = 1.00.a
  PARAMETER HW_INSTANCE = ppc405_0
  PARAMETER COMPILER = powerpc-eabi-gcc
  PARAMETER ARCHIVER = powerpc-eabi-ar
  PARAMETER CORE_CLOCK_FREQ_HZ = 100000000
END

BEGIN PROCESSOR
  PARAMETER DRIVER_NAME = cpu_ppc405
  PARAMETER DRIVER_VER = 1.00.a
  PARAMETER HW_INSTANCE = ppc405_1
  PARAMETER COMPILER = powerpc-eabi-gcc
  PARAMETER ARCHIVER = powerpc-eabi-ar
END


BEGIN DRIVER
  PARAMETER DRIVER_NAME = sysace
  PARAMETER DRIVER_VER = 1.00.a
  PARAMETER HW_INSTANCE = SysACE_CompactFlash
END

BEGIN DRIVER
  PARAMETER DRIVER_NAME = plbarb
  PARAMETER DRIVER_VER = 1.01.a
  PARAMETER HW_INSTANCE = plb
END

BEGIN DRIVER
  PARAMETER DRIVER_NAME = plb2opb
  PARAMETER DRIVER_VER = 1.00.a
  PARAMETER HW_INSTANCE = plb2opb
END

BEGIN DRIVER
  PARAMETER DRIVER_NAME = opbarb
  PARAMETER DRIVER_VER = 1.02.a
  PARAMETER HW_INSTANCE = opb
END

BEGIN DRIVER
  PARAMETER DRIVER_NAME = uartlite
  PARAMETER DRIVER_VER = 1.01.a
  PARAMETER HW_INSTANCE = RS232_Uart_1
END

BEGIN DRIVER
  PARAMETER DRIVER_NAME = ddr
  PARAMETER DRIVER_VER = 1.00.b
  PARAMETER HW_INSTANCE = DDR_SDRAM_64Mx64
END

BEGIN DRIVER
  PARAMETER DRIVER_NAME = generic
  PARAMETER DRIVER_VER = 1.00.a
  PARAMETER HW_INSTANCE = jtagppc_0
END

BEGIN DRIVER
  PARAMETER DRIVER_NAME = bram
  PARAMETER DRIVER_VER = 1.00.a
  PARAMETER HW_INSTANCE = plb_bram_if_cntlr_1
END

BEGIN DRIVER
  PARAMETER DRIVER_NAME = emac
  PARAMETER DRIVER_VER = 1.00.e
  PARAMETER HW_INSTANCE = Ethernet_MAC
END


BEGIN LIBRARY
  PARAMETER LIBRARY_NAME = lwip
  PARAMETER LIBRARY_VER = 2.00.a
  PARAMETER PROC_INSTANCE = ppc405_0
  PARAMETER EMAC_INSTANCES = ((Ethernet_MAC,0x00,0x11,0x22,0x33,0x44,0x55))
END

BEGIN LIBRARY
  PARAMETER LIBRARY_NAME = xilfatfs
  PARAMETER LIBRARY_VER = 1.00.a
  PARAMETER PROC_INSTANCE = ppc405_0
END

Article: 121629
Subject: slave serial configuration of Vertex FPGA using a microcontroller
From: archana <ramaarchana@gmail.com>
Date: Tue, 10 Jul 2007 02:13:14 -0700
Links: << >> << T >> << A >>

hi

I want to configure a vertex FPGA using a PIC microcontroller in the
slave serial mode .

I am simply doing the following steps while configuring.
1.Hold prog_b pin low for some time to clear the configuration memory
2.Release prog_b pin
3.Send a high on init_b pin
4.Send the data serially bit by bit at the rising edge of each clock
pulse
5.Once the done pin high release the din pin

Is it the correct procedure

Article: 121630
Subject: Re: slave serial configuration of Vertex FPGA using a microcontroller
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 10 Jul 2007 11:47:51 +0100
Links: << >> << T >> << A >>

"archana" <ramaarchana@gmail.com> wrote in message 
news:1184058794.575549.212970@j4g2000prf.googlegroups.com...
> hi
>
> I want to configure a vertex FPGA using a PIC microcontroller in the
> slave serial mode .
>
> I am simply doing the following steps while configuring.
> 1.Hold prog_b pin low for some time to clear the configuration memory
> 2.Release prog_b pin
> 3.Send a high on init_b pin
> 4.Send the data serially bit by bit at the rising edge of each clock
> pulse
> 5.Once the done pin high release the din pin
>
> Is it the correct procedure
>
Check the data sheet, but I think INIT is an output from the FPGA.
HTH, Syms.

Article: 121631
Subject: Re: DDR SDRAM simulation model, ML300, Infineon
From: Jim Wu <jimwu88NOOOSPAM@yahoo.com>
Date: Tue, 10 Jul 2007 04:27:47 -0700
Links: << >> << T >> << A >>

On Jul 9, 8:03 pm, chakra <narashim...@gmail.com> wrote:
> Hello all,
>
> I m working on an application using DDR SDRAM and i want to simulate
> (timing simulation) the DDR SDRAM working along with the module i have
> created.  the DDR SDRAM which is implemented on my board (ML300) is
> Infineon HYB25D256800AT-7. it is implemented as 4 discrete parts each
> 256Mbit as 8bits*32million = 32MB thus totalling 4*32MB= 128MB. if
> someone has the model/know a place where i can download VHDL/Verilog
> simulation model of the above part that will be very useful for my
> project.
>
> Also i have a similar DDR SDRAM simulation model. this part is
> manufactured by Micron MT46V32M8TG-75 and similar 256Mb 8bits*32mil =
> 32 MB. is it advisable to use this simulation model in the place of
> the infineon? the DQ, DQS, DM, ADDR, col are all same for the two.
>
> any help in this regard will be very useful.
>
> with warm regards,
> Chakra.

You can get simulation models from http://www.qimonda.com (a spin-off
of Infineon).

Cheers,
Jim
http://home.comcast.net/~jimwu88/tools/

Article: 121632
Subject: Re: slave serial configuration of Vertex FPGA using a microcontroller
From: Gabor <gabor@alacron.com>
Date: Tue, 10 Jul 2007 05:27:24 -0700
Links: << >> << T >> << A >>

On Jul 10, 6:47 am, "Symon" <symon_bre...@hotmail.com> wrote:
> "archana" <ramaarch...@gmail.com> wrote in message
>
> news:1184058794.575549.212970@j4g2000prf.googlegroups.com...> hi
>
> > I want to configure a vertex FPGA using a PIC microcontroller in the
> > slave serial mode .
>
> > I am simply doing the following steps while configuring.
> > 1.Hold prog_b pin low for some time to clear the configuration memory
> > 2.Release prog_b pin
> > 3.Send a high on init_b pin
> > 4.Send the data serially bit by bit at the rising edge of each clock
> > pulse
> > 5.Once the done pin high release the din pin
>
> > Is it the correct procedure
>
> Check the data sheet, but I think INIT is an output from the FPGA.
> HTH, Syms.

INIT (active low) is indeed an I/O, normally considered open drain
during configuration.  Depending on the part, it may be a dedicated
pin or turn into user I/O after config.  During config, the FPGA
drives INIT low from the time prog_b is asserted until it has
finished initialization.  You must wait for INIT to go "high"
(requires a pullup) before starting to clock the bitstream in.
INIT may also be driven low by the FPGA when it detects a CRC
error in the bitstream.  It is good to periodically check for
this while sending the bitstream.

INIT can also be an input to the FPGA, although this mostly
applies to master configuration modes.  Holding INIT low
externally will prevent the FPGA from self-configuration
when the mode pins are set for one of the master modes.  This
is useful when you want to load the part by JTAG, or force
the part to wait for some other reason after power up.

Last point.  Unless you change the default settings for bitstream
generation, you usually need at least 2 CCLK cycles after DONE
goes high to ensure startup of the FPGA.  Often you get these
for free if you send to the end of the generated bitstream data,
which is stored as bytes, however it is not guaranteed.  If you
run out of data from the .bit file, continue sending 1's on the
DIN pin.

HTH,
Gabor

Article: 121633
Subject: Re: A Way for a DSP to tell an FPGA to load itself from Flash
From: axr0284 <axr0284@yahoo.com>
Date: Tue, 10 Jul 2007 13:18:25 -0000
Links: << >> << T >> << A >>

On Jul 9, 6:11 pm, PFC <l...@peufeu.com> wrote:
> > My concern would be what do the DSP and FPGA pins output when they are
> > in reset mode or while programing. It would be an issue if both are
> > driving the address line of the FLASH while one is trying to program
> > itself.
> > Amish
>
>         Actually, you're concerned about preventing the FPGA from configuring  
> itself and becoming active too early...
>
>         Maybe you can have the DSP configure the FPGA : once it has loaded its  
> program from the flash, the DSP can read (at a specific flash address) the  
> FPGA bitstream and send it to the FPGA (via SPI, parallel, whatever). This  
> way you specify where your bitstream is stored in the flash...

This is how it is currently done but then we become dependent on the
DSP to load the code introducing a single point of failure. I would
like to be able to load the code from Flash independently of the DSP
if the DSP stops working.
Amish

Article: 121634
Subject: Re: configuring vertex4 FPGA
From: Matthew Hicks <mdhicks2@uiuc.edu>
Date: Tue, 10 Jul 2007 13:30:44 +0000 (UTC)
Links: << >> << T >> << A >>

Refer to XAPP 058 for all the basic information on how this can be done.


---Matthew Hicks


> hi
> 
> i want to configure a XC4 series of  vertex 4 FPGA using a micro
> controller. which bitgen file is to be ussed for default
> configuration.
> 
> Is a title declaration generation for the verterx bitgen files.
>

Article: 121635
Subject: Re: Spartan3A : timing Constraints / DCM Outputs
From: Metin <metinnn@gmx.de>
Date: Tue, 10 Jul 2007 06:40:59 -0700
Links: << >> << T >> << A >>

I replaced BUFGMUX with BUFG....than it started to analyze fanout logic timing. BUFGMUX was configured correct that desired clock went thru & arrived registers(verified with fpgaedit).

Strange...

Anybody any idea?

Article: 121636
Subject: Re: DDR SDRAM simulation model, ML300, Infineon
From: chakra <narashimanc@gmail.com>
Date: Tue, 10 Jul 2007 07:57:13 -0700
Links: << >> << T >> << A >>

Thanks all for ur valubel information.

regards,
Chakra.

On Jul 10, 6:27 am, Jim Wu <jimwu88NOOOS...@yahoo.com> wrote:
> On Jul 9, 8:03 pm, chakra <narashim...@gmail.com> wrote:
>
>
>
>
>
> > Hello all,
>
> > I m working on an application using DDR SDRAM and i want to simulate
> > (timing simulation) the DDR SDRAM working along with the module i have
> > created.  the DDR SDRAM which is implemented on my board (ML300) is
> > Infineon HYB25D256800AT-7. it is implemented as 4 discrete parts each
> > 256Mbit as 8bits*32million = 32MB thus totalling 4*32MB= 128MB. if
> > someone has the model/know a place where i can download VHDL/Verilog
> > simulation model of the above part that will be very useful for my
> > project.
>
> > Also i have a similar DDR SDRAM simulation model. this part is
> > manufactured by Micron MT46V32M8TG-75 and similar 256Mb 8bits*32mil =
> > 32 MB. is it advisable to use this simulation model in the place of
> > the infineon? the DQ, DQS, DM, ADDR, col are all same for the two.
>
> > any help in this regard will be very useful.
>
> > with warm regards,
> > Chakra.
>
> You can get simulation models fromhttp://www.qimonda.com(a spin-off
> of Infineon).
>
> Cheers,
> Jimhttp://home.comcast.net/~jimwu88/tools/- Hide quoted text -
>
> - Show quoted text -

From dont@email.me Tue Jul 10 09:44:59 2007
Path: newsdbm02.news.prodigy.net!newsdst02.news.prodigy.net!prodigy.com!newscon02.news.prodigy.net!prodigy.net!news.glorb.com!nntpserver.com!zeus.nntpserver.com!10.1.1.41.MISMATCH!pfilter-v0.1!not-for-mail
From: Berk Birand <dont@email.me>
Subject: Virtex-II Pro Flip-Flop Setup time
Date: Tue, 10 Jul 2007 12:44:59 -0400
User-Agent: Pan/0.14.2 (This is not a psychotic episode. It's a cleansing moment of clarity.)
Message-Id: <pan.2007.07.10.16.44.58.878045@email.me>
Newsgroups: comp.arch.fpga
MIME-Version: 1.0
Content-Type: text/plain; charset=ISO-8859-1
Content-Transfer-Encoding: 8bit
Lines: 17
NNTP-Posting-Date: 10 Jul 2007 15:52:58 GMT
X-Complaints-To: abuse@teranews.com
Xref: prodigy.net comp.arch.fpga:133526
X-Received-Date: Wed, 11 Jul 2007 08:53:37 EDT (newsdbm02.news.prodigy.net)

Hi,

For our VHDL design, we are using an evaluation board that has a Xilinx
Virtex-II Pro chip on it. The design calls for sampling of a digital
signal at 100MHZ. The problem is that the signal contains very short
pulses, given at random intervals.
It's therefore necessary to make sure that the sampler (which is
implemented by the flip-flop found in the CLB) can register these pulses,
or at least to have an idea of which ones it can register.

So the question is, what is the setup and hold time constraints of those
flip-flops? I looked in the datasheet, but couldn't find these figures.
The clock to ouput times and so forth were listed, but not this specific
setup time. The timing analyzer also didn't give me a satisfying result.

Thanks a lot for your reply,
Berk Birand

-- 
Posted via a free Usenet account from http://www.teranews.com

Article: 121637
Subject: Re: DDR SDRAM simulation model, ML300, Infineon
From: Kevin Neilson <kevin_neilson@removethiscomcast.net>
Date: Tue, 10 Jul 2007 11:02:54 -0600
Links: << >> << T >> << A >>

chakra wrote:
> Hello all,
> 
> I m working on an application using DDR SDRAM and i want to simulate
> (timing simulation) the DDR SDRAM working along with the module i have
> created.  the DDR SDRAM which is implemented on my board (ML300) is
> Infineon HYB25D256800AT-7. it is implemented as 4 discrete parts each
> 256Mbit as 8bits*32million = 32MB thus totalling 4*32MB= 128MB. if
> someone has the model/know a place where i can download VHDL/Verilog
> simulation model of the above part that will be very useful for my
> project.
> 
> Also i have a similar DDR SDRAM simulation model. this part is
> manufactured by Micron MT46V32M8TG-75 and similar 256Mb 8bits*32mil =
> 32 MB. is it advisable to use this simulation model in the place of
> the infineon? the DQ, DQS, DM, ADDR, col are all same for the two.
> 
> any help in this regard will be very useful.
> 
> with warm regards,
> Chakra.
> 
I recommend the Micron model.  It is very detailed, albeit not terribly 
fast.  I should point out that some of the specs between the Infineon 
and the Micron parts are slightly different.  This caused me a problem 
once.  My memory controller was designed for a board that could use 
either part interchangeably and I used the smaller setup time in my 
design which caused it to fail for the other brand.  -Kevin

Article: 121638
Subject: ISE 9.1i - Process Map Fail without any Error messages
From: Naveen <vnaveen2383@gmail.com>
Date: Tue, 10 Jul 2007 20:06:49 -0000
Links: << >> << T >> << A >>

I am using ISE 9.1i. I am getting an error in the Map process which
says " Process MAP Fail" without showing any errors. There happens to
be bug which was solved in 8.2i Service Pack 1, but still I am facing
this bug.
Does anyone know how to fix this?

Thanks in advance.
Naveen

Article: 121639
Subject: Re: How to choose FPGA for a huge computation?
From: Totally_Lost <air_bits@yahoo.com>
Date: Tue, 10 Jul 2007 14:04:23 -0700
Links: << >> << T >> << A >>

On Jul 3, 11:11 pm, John_H <newsgr...@johnhandwork.com> wrote:
> Totally_Lost wrote:
> > On Jul 3, 5:22 pm, Matthew Hicks <mdhic...@uiuc.edu> wrote:
> >> Xilinx is much better served at using resources in making there existing
> >> toolset better as they still need to mature, lest they lose market share
> >> in areas that they dominate.
>
> > Ahhh .... exactly, losing existing market share that is the reason DSP
> > blocks are in FPGA's today.
>
> Why do people whine so mercilessly when their favorite niche application
> doesn't have the requisite multi-million dollar investment in tools?
>
> Reconfigurable computing is great.
>
> It's just not supported natively by general purpose hardware that has a
> huge, general market.
>
> Get over it.
>
> Unless you have many millions to spare to develop the technology to get
> the few reconfigurable computing folks up and running.  We'd welcome the
> addition!

BTW John ... thanks for completing the reality behind my point, which
hopefully with give some eager beavers some pause before picking the
up FPGA banner and running into hard limitations in the available
tools.

Article: 121640
Subject: Re: regarding post place and route timing simulation steps........
From: Duth <premduth@gmail.com>
Date: Tue, 10 Jul 2007 21:24:39 -0000
Links: << >> << T >> << A >>

On Jul 9, 5:35 am, "ekavirsrika...@gmail.com"
<ekavirsrika...@gmail.com> wrote:
> hi all,
>
> i wanted to do the post place and route timingsimulationin modelsim.
>
> i have got the files form thexilinxise and i copied both
> *_timesim.sdf and  *_timesim.vho file into the RTL folder for mysimulation. what else i need to have for the post place and route
> timingsimulation. i have written a test bench for my design. do i
> need to edit it for the post p&r timingsimulation. when i need to
> select *.sdf file (i think during thesimulation).
>
> i need to know what files i need for the timingsimulationand steps
> that are followd for thesimulation. i have gone through the
> appilcation notes but still i feel i am lost some where.
>
> regards
> srik

Hi Srik,

I would follow what Mike says first. After the RTL passes, to setup
for timing simulation out of PN, please see here

http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=18216

Thanks
Duth

Article: 121641
Subject: Re: ISE 9.1i - Process Map Fail without any Error messages
From: "John_H" <newsgroup@johnhandwork.com>
Date: Tue, 10 Jul 2007 14:50:26 -0700
Links: << >> << T >> << A >>

"Naveen" <vnaveen2383@gmail.com> wrote in message 
news:1184098009.564479.140190@o11g2000prd.googlegroups.com...
>I am using ISE 9.1i. I am getting an error in the Map process which
> says " Process MAP Fail" without showing any errors. There happens to
> be bug which was solved in 8.2i Service Pack 1, but still I am facing
> this bug.
> Does anyone know how to fix this?
>
> Thanks in advance.
> Naveen

Do any of your file names or directory paths used have spaces in their 
names?  If so, move to where the are no spaces.  As silly and annoying as 
this sounds, it's still showing up in too much EDA software.

Article: 121642
Subject: EDK and ecncrpted .bit, .nky, .mcs files
From: "Fred" <fred@n0spam.com>
Date: Tue, 10 Jul 2007 22:50:28 +0100
Links: << >> << T >> << A >>

I'm using EDK to try and produce a produce an encrypted bit file and using 
Impact an encrypted mcs file.

I've looked at the literature but can't find anything about how to do this 
within EDK.

Can anyone please point me in the right direction?

Article: 121643
Subject: lpm_constant function in Altera Quartus 7.1
From: drop669@gmail.com
Date: Tue, 10 Jul 2007 15:09:00 -0700
Links: << >> << T >> << A >>

Hi.
Is it buggy again, while using 32-bit hexdecimal number where most
significant bit is one?
What is the simplest workaround of this?

Article: 121644
Subject: Re: ISE 9.1i - Process Map Fail without any Error messages
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 10 Jul 2007 23:39:59 +0100
Links: << >> << T >> << A >>

"John_H" <newsgroup@johnhandwork.com> wrote in message 
news:1397vp67lj8hoeb@corp.supernews.com...
> "Naveen" <vnaveen2383@gmail.com> wrote in message 
> news:1184098009.564479.140190@o11g2000prd.googlegroups.com...
>>I am using ISE 9.1i. I am getting an error in the Map process which
>> says " Process MAP Fail" without showing any errors. There happens to
>> be bug which was solved in 8.2i Service Pack 1, but still I am facing
>> this bug.
>> Does anyone know how to fix this?
>>
>> Thanks in advance.
>> Naveen
>
> Do any of your file names or directory paths used have spaces in their 
> names?  If so, move to where the are no spaces.  As silly and annoying as 
> this sounds, it's still showing up in too much EDA software.
Hence..   John_H   ! :-)

Article: 121645
Subject: Re: lpm_constant function in Altera Quartus 7.1
From: Mike Treseler <mike_treseler@comcast.net>
Date: Tue, 10 Jul 2007 15:43:39 -0700
Links: << >> << T >> << A >>

drop669@gmail.com wrote:
> Hi.
> Is it buggy again, while using 32-bit hexdecimal number where most
> significant bit is one?
> What is the simplest workaround of this?

Use a vhdl constant instead of an lpm_constant:

   constant reg_len_c  : positive := 32;
   subtype  reg_t is unsigned(reg_len_c-1 downto 0);
   constant reg_init_c : reg_t    := x"87654321";

     -- Mike Treseler

Article: 121646
Subject: Re: EDK and ecncrpted .bit, .nky, .mcs files
From: austin <austin@xilinx.com>
Date: Tue, 10 Jul 2007 15:56:01 -0700
Links: << >> << T >> << A >>

Fred,

Not sure I understand what you are trying to do.

If you are running ISE 9.X software on an embedded processor (such as
running LINUX on the 405PPC in a Virtex 2 Pro, or a Virtex 4 FX), that
software should allow you to generate an encrypted bitstream for use
with the 3DES or AES256 decryptors in the V2P or V4 parts.  This is no
different than me sitting here and running ISE 9.2 on my LINUX desktop
machine.

EDK isn't going to tell you how to do anything but get an embedded
processor into the FPGA and get it to talk to your design...the software
and operating system it runs is up to you.

I need to know more to understand what it is you are trying to do.

If you need to know how to encrypt (generally) using an embedded
processor, I would refer you to the NIST website, where you may download
reference c programs to perform 3DES or AES256 encryption.

Austin

Fred wrote:
> I'm using EDK to try and produce a produce an encrypted bit file and using 
> Impact an encrypted mcs file.
> 
> I've looked at the literature but can't find anything about how to do this 
> within EDK.
> 
> Can anyone please point me in the right direction?
> 
>

Article: 121647
Subject: Re: Here you have the 'system.hms'
From: Siva Velusamy <siva.velusamy@xilinx.com>
Date: Tue, 10 Jul 2007 16:51:54 -0700
Links: << >> << T >> << A >>

If you look in your MHS, the plb2opb bridge only allows addresses 
0x8400_0000 to 0x8400_ffff through to the OPB. Since opb_sysace has a 
different address map, it will not be addressable by the processor.

-Siva

Marco Albero wrote:
> Marco Albero wrote:
>> I'm trying to get some files of the CF in a XUP board with a 
>> VirtexII-pro FPGA, the problem is that I use 'opb_sysace' with 
>> xilfatfs library. When I compile the libraries I get the next error:
>>
>> Running DRCs for OSes, Drivers and Libraries ...
>> LWIP DRC...
>> XEmac Instances : 1
>> ERROR:MDT - ERROR FROM TCL:- xilfatfs () - Sysace HW module not 
>> present or not
>>    accessible from this processor. FATfs cannot be used without this 
>> module
>>
>> ERROR:MDT - Error while running DRC for processor ppc405_0...
>>
> BEGIN plb2opb_bridge
>  PARAMETER INSTANCE = plb2opb
>  PARAMETER HW_VER = 1.01.a
>  PARAMETER C_DCR_INTFCE = 0
>  PARAMETER C_NUM_ADDR_RNG = 1
>  PARAMETER C_RNG0_BASEADDR = 0x84000000
>  PARAMETER C_RNG0_HIGHADDR = 0x8400ffff
>  BUS_INTERFACE SPLB = plb

Article: 121648
Subject: SystemC in modeling HW/SW
From: Ace <yasirmm@gmail.com>
Date: Tue, 10 Jul 2007 19:24:32 -0700
Links: << >> << T >> << A >>

Hi,

I was told by a friend that SystemC is currently the best to modeling
hw/sw design. I've read on the internet where people were saying that
SystemC is a more "complete model" which I don't quite understand.
I've look at several other tools for example Impulse C that gave a
very good description on how hw/sw  modeling can be done easily using
Impulse C.

Could anyone be kind to share why do you think systemC is the best
tool to model hw/sw and how? I'm open to any good source should you
wish to share.


Cheers!

Article: 121649
Subject: Re: regarding post place and route timing simulation steps........
From: "ekavirsrikanth@gmail.com" <ekavirsrikanth@gmail.com>
Date: Tue, 10 Jul 2007 21:16:21 -0700
Links: << >> << T >> << A >>

On Jul 11, 2:24 am, Duth <premd...@gmail.com> wrote:
> On Jul 9, 5:35 am, "ekavirsrika...@gmail.com"
>
>
>
>
>
> <ekavirsrika...@gmail.com> wrote:
> > hi all,
>
> > i wanted to do the post place and route timingsimulationin modelsim.
>
> > i have got the files form thexilinxise and i copied both
> > *_timesim.sdf and  *_timesim.vho file into the RTL folder for mysimulation. what else i need to have for the post place and route
> > timingsimulation. i have written a test bench for my design. do i
> > need to edit it for the post p&r timingsimulation. when i need to
> > select *.sdf file (i think during thesimulation).
>
> > i need to know what files i need for the timingsimulationand steps
> > that are followd for thesimulation. i have gone through the
> > appilcation notes but still i feel i am lost some where.
>
> > regards
> > srik
>
> Hi Srik,
>
> I would follow what Mike says first. After the RTL passes, to setup
> for timing simulation out of PN, please see here
>
> http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountry...
>
> Thanks
> Duth- Hide quoted text -
>
> - Show quoted text -

Thanks alot mike and duth...
i got it how it can be done. thank you ....

regards
srik

Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search