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Gang
I created a module, downloaded it to my dev board and ran it. The
LED's changed as I expected.
I decided to run a behavioral simulation to prove to myself that
signals were changing the way I
expected them to.
So I created a verilog test bench. Here is my code.
module tob_tb_v;
// Inputs
reg clk;
reg rst;
// Outputs
wire [7:0] leds;
// Instantiate the Unit Under Test (UUT)
Top uut (
.clk(clk),
.rst(rst),
.leds(leds)
);
initial begin
// Initialize Inputs
// Wait 100 ns for global reset to finish
#100;
$display("At time %t", $time);
#10;
$display("At time %t", $time);
// Add stimulus here
end
always @(posedge clk)
begin
end
endmodule
I am really confused. I have done simulations before on simple modules
that didn't have clock
inputs. This one as you can see does. When I go to simulation window,
I am not seeing a
periodic clock signal. Without it, I don't know how to evaluate the
state of my other signals.
What am I doing wrong?
Thanks for helping. I am running ISE 9.1 Webpack with SP3, under
Windows XP with SP2, 2GB of RAM, 200GB of free disk space.
Bob
Article: 122726
You have to drive the clk signal either in your code or by using a command
provided by your simulator.
---Matthew Hicks
> Gang
>
> I created a module, downloaded it to my dev board and ran it. The
> LED's changed as I expected.
>
> I decided to run a behavioral simulation to prove to myself that
> signals were changing the way I
> expected them to.
> So I created a verilog test bench. Here is my code.
>
> module tob_tb_v;
>
> // Inputs
> reg clk;
> reg rst;
> // Outputs
> wire [7:0] leds;
> // Instantiate the Unit Under Test (UUT)
> Top uut (
> .clk(clk),
> .rst(rst),
> .leds(leds)
> );
> initial begin
> // Initialize Inputs
> // Wait 100 ns for global reset to finish
> #100;
> $display("At time %t", $time);
> #10;
> $display("At time %t", $time);
>
> // Add stimulus here
>
> end
>
> always @(posedge clk)
> begin
> end
> endmodule
>
> I am really confused. I have done simulations before on simple modules
> that didn't have clock
> inputs. This one as you can see does. When I go to simulation window,
> I am not seeing a
> periodic clock signal. Without it, I don't know how to evaluate the
> state of my other signals.
> What am I doing wrong?
>
> Thanks for helping. I am running ISE 9.1 Webpack with SP3, under
> Windows XP with SP2, 2GB of RAM, 200GB of free disk space.
>
> Bob
>
Article: 122727
In particular ... add something like following :
parameter clk_100mhz_half_period = 5;
// regs and wires
reg clk_100mhz, cr_rst;
// clock
initial clk_100mhz = 1'b0;
initial cr_rst = 1'b1;
always #clk_100mhz_half_period clk_100mhz = ~clk_100mhz;
initial
begin
repeat(100) begin @(posedge clk_100mhz); end
cr_rst = 1'b0;
end
//
--
Regards,
John Retta
Owner and Designer
Retta Technical Consulting Inc.
email : jretta@rtc-inc.com
web : www.rtc-inc.com
"Matthew Hicks" <mdhicks2@uiuc.edu> wrote in message
news:b66e6524df908c9a4fc66a3f302@news.ks.uiuc.edu...
> You have to drive the clk signal either in your code or by using a command
> provided by your simulator.
>
>
> ---Matthew Hicks
>
>
>> Gang
>>
>> I created a module, downloaded it to my dev board and ran it. The
>> LED's changed as I expected.
>>
>> I decided to run a behavioral simulation to prove to myself that
>> signals were changing the way I
>> expected them to.
>> So I created a verilog test bench. Here is my code.
>>
>> module tob_tb_v;
>>
>> // Inputs
>> reg clk;
>> reg rst;
>> // Outputs
>> wire [7:0] leds;
>> // Instantiate the Unit Under Test (UUT)
>> Top uut (
>> .clk(clk),
>> .rst(rst),
>> .leds(leds)
>> );
>> initial begin
>> // Initialize Inputs
>> // Wait 100 ns for global reset to finish
>> #100;
>> $display("At time %t", $time);
>> #10;
>> $display("At time %t", $time);
>>
>> // Add stimulus here
>>
>> end
>>
>> always @(posedge clk)
>> begin
>> end
>> endmodule
>>
>> I am really confused. I have done simulations before on simple modules
>> that didn't have clock
>> inputs. This one as you can see does. When I go to simulation window,
>> I am not seeing a
>> periodic clock signal. Without it, I don't know how to evaluate the
>> state of my other signals.
>> What am I doing wrong?
>>
>> Thanks for helping. I am running ISE 9.1 Webpack with SP3, under
>> Windows XP with SP2, 2GB of RAM, 200GB of free disk space.
>>
>> Bob
>>
>
>
Article: 122728On Aug 5, 2:00 am, ZHI <threeinchn...@gmail.com> wrote: > I am reading some papers about algorthms implementation. I noticed > they like to compare the synthesis area of the fixed-point > implementation. I wander where they find the area report for the > implementation. I only see the slice percent report. I am using the > Xilinx ISE. I want to know where to generate the area report. Any > comment is welcome. Area report can be found in synthesis report and Map report. Look at FPGA design summary.Article: 122729
Do you need real time access, or more debug information? I would take a serial connection (open cores has them) and an intelligent PC COM software. There are several which are able to completely receive large data streams. So there is not much work to do. Possibly you need a level converter like the MAX x232. You may also want to transform the rams into dual port mems to easier access them.Article: 122730
I have a certain demand on processing digital data with a PC and thought about to do this with an FPGA/PC. What would be fine was a PCI compatible card with an FPGA on it which could be extended to my needs. Is there something out in the market ? I know about the FPGA card of NI, but found, one probably must program it with LABVIEW and there is no chance to fill it with own code. So what I need is a card + drivers so that I can write down into the FPGA adresses and read back the data. Any Idea? Thank in progressArticle: 122731
For the record, the problem was apparently the reset signal.
Changing from this:
PORT SYS_Rst = sys_rst_s
to this
PORT SYS_Rst = sys_bus_reset
solved the problem.
Article: 122732Hi. Does somebody have a real success with burning OpenSPARC to FPGA?Article: 122733
Hi. I'm looking for a company who implement various algorithms using FPGA accelerators. Who can take part of some software code and rework it completely to make working FPGA accelerator in form, maybe, PCI card or PC-card. If such information may be considered as advertising in this group, please email me: drop669@gmail.comArticle: 122734
On 5 Aug., 16:00, drop...@gmail.com wrote: > Hi. > Does somebody have a real success with burning OpenSPARC to FPGA? you mean making FPGA burning hot ? there are easier ways todo that then OpenSPARC AnttiArticle: 122735
> > Does somebody have a real success with burning OpenSPARC to FPGA? > > you mean making FPGA burning hot ? No, just to prepare OpenSPARC for Xilinx or Altera :)Article: 122736
On Sun, 05 Aug 2007 04:51:42 -0700, fpgauser wrote: > I have a certain demand on processing digital data with a PC and thought > about to do this with an FPGA/PC. What would be fine was a PCI > compatible card with an FPGA on it which could be extended to my needs. [...] > So what I need is a card + drivers so that I can write down into the > FPGA adresses and read back the data. > > Any Idea? http://vmetro.com Disclaimer: they pay my salary. - JeremyArticle: 122737
On Aug 4, 5:00 pm, ZHI <threeinchn...@gmail.com> wrote: > I am reading some papers about algorthms implementation. I noticed > they like to compare the synthesis area of the fixed-point > implementation. I wander where they find the area report for the > implementation. I only see the slice percent report. I am using the > Xilinx ISE. I want to know where to generate the area report. Any > comment is welcome. Are they giving the area in square mm? If so they are not talking about FPGAs, but ASICs or custom chips. The area group reports from ISE are still given in slices, etc, not in square mm. If they are talking about area group reports from ISE, you have to apply an area group constraint to the module/component you want to get the report for. See the constraint guide documentation for more information on how to do this. Regards, John McCaskill www.fastertechnology.comArticle: 122738
Hi, I start work on some project involving FPGA and I have to define port as bidirectional (inut-output). I know that in VHDL there is keyword "inout" when defining port, but I don't know what detirminats that this kind defined port would be input or output. Thanks for any kind of help ZoranArticle: 122739
If you do a Google search for OpenSparc and FPGA the first few links will give you plenty of info. ---Matthew Hicks >>> Does somebody have a real success with burning OpenSPARC to FPGA? >>> >> you mean making FPGA burning hot ? >> > No, just to prepare OpenSPARC for Xilinx or Altera :) >Article: 122740
If this is for a half-duplex bus application, I think it is prefered to have two signals, one input and one output and to combine them at the top level with the appropriate buffers, instead of a single input/output signal. That way, it is clear what is being sent out and that is being brought in. If the inout is just so you can read a value that you are outputting, then it is best to use an internal signal that holds the value to output. This means that you can both drive a value on the line and read the value at the same time. ---Matthew Hicks > Hi, > I start work on some project involving FPGA and I have to define port > as bidirectional (inut-output). > I know that in VHDL there is keyword "inout" when defining port, but I > don't know what detirminats that this kind defined port would be input > or output. > Thanks for any kind of help > ZoranArticle: 122741
I need to generate a signle ended signal possibly using the V5 Select I/O pin that is synchronous to one of the GTP output running at 400Mbps. The sigle ended signal needs to be 1.5V Push-pull type. I thought about using one of the GTP in doing this but the GTP output is CML and it does not quite match with 1.5V single ended signal (DDR3 type output). The fpga fabric will use the same fabric clock to generate the single ended signal and also to feed the data to the GTP. But GTP will be using internal PLL to transfer the data out. The single ended signal ONLY needs to go from logic low to high to determine the start of packet. And after that it needs to stay high. The rising of the very first clock after the deassetion (Logic high) of the signal ended signle determines the start of packet. I am thinking that the timing relationship between the fabric clock used to generate the single ended signal and the GTP output is going to be deterministic from power cycle to power cycle so if I can put a fixed ODELAY on the single ended output then it wlll be synchronous to the GTP output running at 400Mbps. Is that right assumption? The GTP output initially runs at 400MBps and then switched to higher data rate not supported by Xilinx select I/O so I can not use the Select I/O to replace the GTP functionality. Any ideas will be great. EddieArticle: 122742
On Aug 5, 7:34 am, fpgauser <fpgaengineerfrankf...@arcor.de> wrote: > Do you need real time access, or more debug information? > > I would take a serial connection (open cores has them) and an > intelligent PC COM software. There are several which are able to > completely receive large data streams. So there is not much work to > do. Possibly you need a level converter like the MAX x232. You may > also want to transform the rams into dual port mems to easier access > them. For now 115kbits/s would be OK for me as the design I am testing needs to send a content of 16Kb BRAM data at a time, transfer time of several seconds would be fine. But when I expand my design USB transfer would be much better but I am not sure yet how much more complicated would be to make use of the USB port on my FPGA. -DanArticle: 122743
On Aug 5, 4:06 pm, "Eddie H" <> wrote: [...] > I thought about using one of the GTP in doing this but the GTP output is CML and it does not quite match with 1.5V single ended signal (DDR3 type output) [...] > The single ended signal ONLY needs to go from logic low to high to determine the start of packet. And after that it needs to stay high. > > The rising of the very first clock after the deassetion (Logic high) of the signal ended signle determines the start of packet. > > I am thinking that the timing relationship between the fabric clock used to generate the single ended signal and the GTP output is going to be deterministic from power cycle to power cycle so if I can put a fixed ODELAY on the single ended output then it wlll be synchronous to the GTP output running at 400Mbps. Is that right assumption? > > The GTP output initially runs at 400MBps and then switched to higher data rate not supported by Xilinx select I/O so I can not use the Select I/O to replace the GTP functionality. > > Any ideas will be great. Howdy Eddie, I don't suppose suggesting the use of a more reasonable protocol would be of much help, would it? :-) There are FIFO's in the receive and transmit paths of the GTP's. I don't know about the V5's, but V2Pro receive FIFO wasn't completely deterministic on its own, although you could do some things to make the window quite small (within a few clock cycles). As for interfacing single ended to differential, there are a number of vendors which provide inexpensive popcorn logic to do that. At first I thought this was for DDR3, but I'm not sure how that fits in with this "start of packet" signal. What protocol is this? Good luck, MarcArticle: 122744
Marc, This protocol is defined by one of the university and I need to see if I can use the FPGA to support it. I understand that it is not slam dunk fpga solution but I am trying to make it work. The protocol command consists of 8 bittimes of the ddr clock. The single ended signal needs to lineup with the first bit time to indicate the start of the bit time. The first bittime starts at the deassertion of the single ended signal. The receiver will sample this at the first rising edge of the ddr clock. Here is a sequence of events: (1) DDR clock keeps toggling and the single ended signal is asserted. (2) Bit time 0 = single ended signal is sampled deasserted at the rising edge of the ddr clock (3) Bit time 1 = faling edge of ddr clock (4) Bit time 2 = rising edge of ddr clock (5) Bit time 3 = falling edge of ddr clock (6) bit time 4 = rising edge of ddr clock (7) bit time 5 = falling edge of ddr clock (8) bit time 6 = rising edge of ddr clock (9) bit time 7 = falling edge of ddr clock Then it starts back to bit time0 bit time 0 = rising edge of ddr clock, The GTPs send out meaningful command on this bit time0 window. This command lasts till bit time7 and then again there is bit time0 for idle bus or to generate another command. The single ended signal gets de-asserted first before the rising edge of the ddr clock in order to signify the bit time0 and then the gtp output can be generated as long as it is bit time0 aligned. If the fabric clock which generates both the single ended output and feeds the parallel data, has fixed timing relationship with the GTP circuit then this can possibly be achieved by initial board calibration. If the intenal fpga delay is deterministic from power cycle to power cycle then the board calibration will determine the required odelay value to align the single ended output with the bit time0 window. My main question is - timing relationship between the fabric and the gtp circuit is fixed? If fixed then there is a solution is that correct? Thanks. EddieArticle: 122745
hi all I have to test an fpga on a customised board could anybody suggest me the methods for this archanaArticle: 122746
On Aug 6, 9:16 am, archana <ramaarch...@gmail.com> wrote: > hi all > > I have to test an fpga on a customised board > > could anybody suggest me the methods for this > archana hello, there are a number of tests/things you should do/ensure to get the custom board up and working. Check the power supply from the regulators to ensure they are giving correct core/auxillary/internal voltages to the FPGA. You should have designed the board to have a jumper disconnecting the voltages to the fpga and only after checking their stability through oscilloscope (for rail noise etc), should you connect the jumpers for routing the power to the FPGA. After the power check, make sure the PROM you've connected also connects correctly to the power supplies as well as to the FPGA using the short circuit test through an amp meter. Next is to check whether the jtag chain is picking PROM and FPGA through Impact. If they are detected correctly, then see if the boundary scan can program the FPGA for say turning on/off LEDs. If you have general purpose i/os connected to an external header, then check the voltages there giving a 0xAA pattern to any 8 output pins. If PROM and FPGA are being programmed correctly, then its a matter of writing validation applications/codes for individual hardware and testing if each work independently/collectively fine with the FPGA. Hope this helps MakArticle: 122747
hi all.. Is it possible to import the design which is converted into a class.ptf file by Altera DSP builder into SOPC builder. i have converted it into a *.ptf file but was unable to import into the design. can anyone help me outArticle: 122748
On Aug 6, 7:43 am, EEngineer <mari...@gmail.com> wrote: > On Aug 5, 7:34 am, fpgauser <fpgaengineerfrankf...@arcor.de> wrote: > > > Do you need real time access, or more debug information? > > > I would take a serial connection (open cores has them) and an > > intelligent PC COM software. There are several which are able to > > completely receive large data streams. So there is not much work to > > do. Possibly you need a level converter like the MAX x232. You may > > also want to transform the rams into dual port mems to easier access > > them. > > For now 115kbits/s would be OK for me as the design I am testing needs > to send a content of 16Kb BRAM data at a time, transfer time of > several seconds would be fine. But when I expand my design USB > transfer would be much better but I am not sure yet how much more > complicated would be to make use of the USB port on my FPGA. > > -Dan Hi, You might want to consider using chipscope pro, provided if you have BRAMs for its storage. Chipscope will store your signals in real time (at FPGAs clock speed) and after capturing, display them on its analyser. You will be severly limited by the amount of BRAM though. Given enough block ram you can store upto 16k samples of a signal. If you insert single logic analyser core (ILA core), then you can store upto 256 signals for display later. You can trigger your signals at any combination or desired point. Putting USB in a system is a complete new project with its complexities. You will need an external protocol negotiator (since you wouldnt want to write your own IP). So a microcontroller with all the issues resolved may offer a solution and USB data in form of FIFOs which can then be interfaced with the FPGA for data readout. You will require a PCB redesign in that case. Cypress, Microchip etc. offer microcontrollers with USB hardwired USB Protocol resolvers inside. Hope this helps. MakArticle: 122749
hi all, i am new to this group and i am beginner in this FPGA field so i need ur help to find some material regarding FPGA i hope u people can help me out thank u
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Threads starting:
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