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You are kindly invited to visit www.visualipd.com Visual IP Designer is an EDA tool for design entry and integration which enable designers to intuitively build, maintain and reuse their designs using a full graphical approach. Visual IP Designer provides an advanced and fast methodology to develop HDL-based designs targeting ASIC and FPGA. The Visual IP format is able to describe designs at RTL level in a more flexible and attractive way. The automatic code generation feature allows obtaining a high quality VHDL code optimized for synthesis with a non scarified readability.Article: 113901
You are kindly invited to visit www.visualipd.com Visual IP Designer is an EDA tool for design entry and integration which enable designers to intuitively build, maintain and reuse their designs using a full graphical approach. Visual IP Designer provides an advanced and fast methodology to develop HDL-based designs targeting ASIC and FPGA. The Visual IP format is able to describe designs at RTL level in a more flexible and attractive way. The automatic code generation feature allows obtaining a high quality VHDL code optimized for synthesis with a non scarified readability.Article: 113902
tersono wrote: > On 25 Dec 2006 11:12:44 -0800, "fpgauser" > <fpgaengineerfrankfurt@arcor.de> wrote: > > <snip> > > One reason *I* need to use 8.2 rather than 8.1- to quote from "What's > New": > ## > iMPACT > Support for direct programming of SPI FLASH PROMs from Atmel=AE and ST > Micro=AE. > ## > -this explained the frustration of my being unable to use a Spartan3E > board from Avnet, while a colleague with v8.2 used it OK. > -- > Per ardua ad nauseam Just out of curiosity, is this referring to xapp 445, or something new? I know Xilinx has a tool that allows you to program Atmel and STMicro flash SPI flash using a platform cable, but it was bit-banged, and required you to create a second "JTAG" connector. (Mind you, I'm not complaining - this utility will allow me to replace a platform flash and separate flash memory with one, larger, flash memory) It would be great if I could program the part via the actual JTAG chain through the FPGA, as though it were a platform flash. This would definitely make it simpler to use SPI flash for configuration. I suspect, though; that they rolled the code from the utility in that XAPP into Impact, and you still need a separate programming port for the SPI flash on the board. Otherwise, why would anyone buy platform flash chips anymore?Article: 113903
impact:477 the bsdl for device 'UNKNOWN' is out of date does anyone have any idea? I have this error when working with system ace. i'm trying to make my Virtex4 XtremeDSP kit to be self-programmabel using system ace. I built the system ace circuit and encountered this error. What i did was i hooked up the jtag cable to my board's 'test jtag' port, and i hooked up my 'config jtag' port to the xtremeDSP kit. I tried to initialize chain using impact and i got this error. I tried using the system ace board with my spartan3 board and it detects all the devices with no problem, including the system ace chip. But when i tried to use it on the XtremeDSP kit, it keeps giving me error and the boundary scan in impact shows random results. sometimes it shows alot of devices detected in the chain, but they are unkown, sometimes it shows that it only detects 2 or 3 of the devices in the chain, and this happens very randomly. can anyone suggest anything here? thx tejoArticle: 113904
I dont know the true cause of it, but in the past when i've had that error, i've removed the jtag programmer, closed impact and restarted the computer, and it usually works first time when i've tried again. Sorry if thats not helpful! sutejok wrote: > impact:477 the bsdl for device 'UNKNOWN' is out of date > > does anyone have any idea? I have this error when working with system > ace. > i'm trying to make my Virtex4 XtremeDSP kit to be self-programmabel > using system ace. I built the system ace circuit and encountered this > error. What i did was i hooked up the jtag cable to my board's 'test > jtag' port, and i hooked up my 'config jtag' port to the xtremeDSP kit. > I tried to initialize chain using impact and i got this error. > > I tried using the system ace board with my spartan3 board and it > detects all the devices with no problem, including the system ace chip. > But when i tried to use it on the XtremeDSP kit, it keeps giving me > error and the boundary scan in impact shows random results. sometimes > it shows alot of devices detected in the chain, but they are unkown, > sometimes it shows that it only detects 2 or 3 of the devices in the > chain, and this happens very randomly. > > can anyone suggest anything here? > > thx > > tejoArticle: 113905
Hello Folks,
I'm writting a slave SPI code for my FPGA and very sure that
my master is generating the right SPI but somehow slave is unable to
decode it. I've never used the verilog before so it might be possible
that something is wrong with my code. Please advice.
_________________________________________________________________________
module test_spi(led,MOSI,SS,SCK,clk);
output [7:0] led;
input MOSI, SS, SCK, clk;
wire MOSI;
wire SS;
wire SCK;
wire clk;
reg num = 7;
reg [7:0] temp = 0;
reg SCK_LAST;
reg SCK_NOW;
reg [7:0] led;
always @(posedge clk)
begin
if (!SS)
begin
SCK_LAST = SCK_NOW;
SCK_NOW = SCK;
if((SCK_LAST==0)&(SCK_NOW==1)) // check SCK is rising
edge
begin
if (num < 8) // 8 bits counter
begin
if (!MOSI)
begin
temp = (temp << 1); //1 bit-shift and store it to temp when
receiving "0"
end
else
begin
temp = ((temp << 1)|8'b00000001); //1 bit-shift and store it to temp
when receiving "1"
end
if (num == 0)
begin
led = temp; //output to the LED on the board
num = 10;
end
end
end
num = num - 1;
end
else
begin
num = 7; //reset counter and temp store
temp = 8'b0;
end
end
endmodule
_________________________________________________________________________
Thanks for your time.
Article: 113906On 2006-12-29, mankin18@gmail.com <mankin18@gmail.com> wrote: > that something is wrong with my code. Please advice. > > reg num = 7; That's almost certainly wrong. I can't vouch for the rest. -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 113907
On 27 Dec 2006 14:47:43 -0800, axr0284@yahoo.com wrote: >Hi, > I have been fighting with this for some time now and I cannot figure >it out. I have read the 802.3 information and I have read a lot of >forums and they all have some kind of general answer. Go here for an exactly correct packet: http://www.fpga-faq.com/archives/91050.html#91062 =================== Philip Freidin philip.freidin@fpga-faq.org Host for WWW.FPGA-FAQ.ORGArticle: 113908
On 28 Dec 2006 15:13:40 -0800, "radarman" <jshamlet@gmail.com> wrote: > >tersono wrote: >> On 25 Dec 2006 11:12:44 -0800, "fpgauser" >> <fpgaengineerfrankfurt@arcor.de> wrote: >> >> <snip> >> >> One reason *I* need to use 8.2 rather than 8.1- to quote from "What's >> New": >> ## >> iMPACT >> Support for direct programming of SPI FLASH PROMs from Atmel® and ST >> Micro®. >> ## >> -this explained the frustration of my being unable to use a Spartan3E >> board from Avnet, while a colleague with v8.2 used it OK. >> -- >> Per ardua ad nauseam > >Just out of curiosity, is this referring to xapp 445, or something new? >I know Xilinx has a tool that allows you to program Atmel and STMicro >flash SPI flash using a platform cable, but it was bit-banged, and >required you to create a second "JTAG" connector. (Mind you, I'm not >complaining - this utility will allow me to replace a platform flash >and separate flash memory with one, larger, flash memory) > >It would be great if I could program the part via the actual JTAG chain >through the FPGA, as though it were a platform flash. This would >definitely make it simpler to use SPI flash for configuration. > >I suspect, though; that they rolled the code from the utility in that >XAPP into Impact, and you still need a separate programming port for >the SPI flash on the board. Otherwise, why would anyone buy platform >flash chips anymore? I am using a simple way to do that: I configure the CPLD and FPGA through JTAG, the last one with a loader program. Thisi program will wait for me to send it the desired contents of the FPGA (.bit file) and save the interesting part directly in the SPI FLASH (wtih no bit order messing!) through the CPLD. Easy, and fast. NOTE: You should provide some way to force the CPLD to abandon all communication with the CPLD on reset, so that you may update FLASH contents this way *if you have already put some contents in the FLASH*. That is really important, otherwise the FPGA may be programmed with a mix of FLASH contents and JTAG data. FUBAR Best regards, ZaraArticle: 113909
On Dec 29, 12:32 pm, Ben Jackson <b...@ben.com> wrote: > On 2006-12-29, manki...@gmail.com <manki...@gmail.com> wrote: > > > that something is wrong with my code. Please advice. > > > reg num = 7;That's almost certainly wrong. I can't vouch for the rest. > > -- > Ben Jackson AD7GD > <b...@ben.com>http://www.ben.com/ Thanks for prompt response! but can you elaborate a bit more?Article: 113910
Hello,
After completing the PART 1 of this tutorial you can now connect and
verify the FX2 functioning as well as establish the End Point FIFO
transfers in Bulk mode. However, all the transactions have taken place
within the scope of FX2. Majority of the time, it is required to
connect the FX2 with an external peripheral for instance FPGA or any
micro processor to transmit and receive data in a custom product. We
will now look at how to setup FX2 in synchronous slave FIFO mode with
an FPGA.
In this setup, we will first ensure that the clock common to both FX2
and FPGA should be provided by the FX2 itself. So the first experiment
should be to setup FX2 for internal clock source running at 12/24/48MHz
as you wish. You will have to set just two registers CPUCS (CPU control
and status) and IFCONFIG (interface configuration) registers for this
experiment. Write a small program as given below to establish clkout
(you will be required to add EzUSB.lib from the
C:\Cypress\USB\Target\Lib\LP\EZUSB.LIB folder, I am using FX2LP so the
folder LP, select appropriate folder for your devices):
************************************************************************************************
#include "C:\Cypress\USB\Target\Inc\fx2.h"
#include "C:\Cypress\USB\Target\Inc\fx2regs.h"
void main (void)
{
CPUCS = 0x12;
IFCONFIG |= 0x40;
while (1) ;
}
*************************************************************************************************
Now if you create the hex file using Keil uVision and burn it to the
FX2 using control panel => download, and check CLKOUT pin (pin5 in 56
pin package, pin100 in 100 pin package, pin1 in 128 pin package), you
should be able to see a valid clock signal running at 24MHz. CPUCS will
set the clock to 48 MHz and enable CLKOUT with 0x12. Try changing it to
0x0A for 24MHz.
The IFCONFIG does nothing but to set the internal clock frequency for
the GPIF/FIFO at 48MHz. The rest of the bits remain default.
You can also take this signal into FPGA and output it onto any general
purpose header pin and check whether the FPGA is reading through the
clock out signal correctly using an oscilloscope. While programming,
you need to ensure that FX2 is programmed first, then FPGA is
programmed. Also, if the clockout signal is resetting to 12MHz after
FPGA programming, then you should set the reset pin connecting the fPGA
and FX2 to high (FPGA will otherwise go low after programming and will
cause the FX2 to reset which is active low).
Now you have established a time base which will be used for designing
FPGA master read and write state machines which will read/write from
slave FIFO in FX2.
Till next time,
Hope it helps.
Mansoor Naseer
Article: 113911"Antti Lukats" <antti@openchip.org> wrote in message news:em9gsm$hg8$1@online.de... > PicoBlaze C compiler has been available for some time already, > but until yesterday I never tried it. > But today when I type: > >>start build.bat > > then the following C file Will this work with 7.1 or 7.2 ? or only 8.1 or 8.2 ?Article: 113912
Marlboro a =E9crit : > The tool is smart enough to know that you're not going to use it, so it > removes the redundant blocks. This is utterly wrong (besides, never rely too much on the tool's smartness). The tool simply sees that the two logic constructs have the same inputs and the same behaviour so it removes one of them. I haven't used ISE in some time but I know for sure that there is an option somewhere to keep it from removing redundant or equivalent logic. Or maybe it is an attribute. Search for "preserve" in the documentation. NicolasArticle: 113913
"Joseph" <joseph.yiu@obviously-not-a-valid-domain.com> wrote in message news:ekk4rt$4ma$1@cam-news1.cambridge.arm.com... > Hi all, > > I wonder if anyone here are in the same situation as me. > I am think of buying a new PC, but wondering if I should > wait for Windows Vista become available first. > Have anyone try running FPGA tools (Xilinx Webpack, > Modelsim XE, Quartus, Cygwin) on Windows Vista beta? > Does it work okay? > Or should I get a "Vista capable" PC now and upgrade later? > (sound too much hassle to me, but it might be better?) > Thanks. > > regards, > > Joe Has anyone here tried running ise or other tools on a mac under parallels ? parallels is similar to vmware. Lets you run windows in a window on a mac. http://www.parallels.com/en/products/workstation/mac/ Can also run linux in a window if you can't find what you need in fink or darwin ports collections. I'll give it a go when I get around to bying a new laptop either a macbook or macbook pro. AlexArticle: 113914
There are no means for assign RocketIO pins in ISE?Article: 113915
mankin18@gmail.com wrote: > > > On Dec 29, 12:32 pm, Ben Jackson <b...@ben.com> wrote: >> On 2006-12-29, manki...@gmail.com <manki...@gmail.com> wrote: >> >> > that something is wrong with my code. Please advice. >> >> > reg num = 7;That's almost certainly wrong. I can't vouch for >> > the rest. >> >> -- >> Ben Jackson AD7GD >> <b...@ben.com>http://www.ben.com/ > > Thanks for prompt response! but can you elaborate a bit more? I'm a VHDL guy, but I think it should be reg [2:0] num; Best regards, BenArticle: 113916
On Dec 29, 3:56 pm, Ben Twijnstra <btwijns...@gmail.com> wrote: > manki...@gmail.com wrote: > > > On Dec 29, 12:32 pm, Ben Jackson <b...@ben.com> wrote: > >> On 2006-12-29, manki...@gmail.com <manki...@gmail.com> wrote: > > >> > that something is wrong with my code. Please advice. > > >> > reg num = 7;That's almost certainly wrong. I can't vouch for > >> > the rest. > > >> -- > >> Ben Jackson AD7GD > >> <b...@ben.com>http://www.ben.com/ > > > Thanks for prompt response! but can you elaborate a bit more?I'm a VHDL guy, but I think it should be > > reg [2:0] num; > > Best regards, > > Ben- Hide quoted text -- Show quoted text - ben! thanks for clue. Let me try and i'll get back to you as i'm also not a verilog guy;-) CheersArticle: 113917
On Dec 29, 4:03 pm, manki...@gmail.com wrote: > On Dec 29, 3:56 pm, Ben Twijnstra <btwijns...@gmail.com> wrote: > > > > > > > manki...@gmail.com wrote: > > > > On Dec 29, 12:32 pm, Ben Jackson <b...@ben.com> wrote: > > >> On 2006-12-29, manki...@gmail.com <manki...@gmail.com> wrote: > > > >> > that something is wrong with my code. Please advice. > > > >> > reg num = 7;That's almost certainly wrong. I can't vouch for > > >> > the rest. > > > >> -- > > >> Ben Jackson AD7GD > > >> <b...@ben.com>http://www.ben.com/ > > > > Thanks for prompt response! but can you elaborate a bit more?I'm a VHDL guy, but I think it should be > > > reg [2:0] num; > > > Best regards, > > > Ben- Hide quoted text -- Show quoted text -ben! thanks for clue. Let me try and i'll get back to you as i'm also > not a verilog guy;-) > > Cheers- Hide quoted text -- Show quoted text - 0ops! and no difference, any idea? --Article: 113918
"radarman" <jshamlet@gmail.com> wrote: > >Johan Bernsp=E5ng wrote: >> I used to believe that ChipScope did not have any impact on the design. >> I used to. >> >> I have two FPGAs communicating on the PCB (LVDS). One of them (called >> source here) is doing some signal processing and sends the result to the >> destination FPGA. If I probe (with ChipScope) some internal results of >> the processing (FFT output) in the source, the data looks fine at the >> destination. However, if I remove the probe I get some interesting, but >> rather annoying, bit errors in the data received (and probed) at the >> destination. >> >> Before probing at the source I thought this was an issue of signal >> integrity on the PCB, but the probing proved me wrong on that point. The >> source is a V2000 device and without the probing about 90% of BRAM and >> mults are utilized. I would think that by adding a ChipScope core PAR >> would have more troubles meeting timing constraints, and consequently >> deliver a design more prone to bit errors... >> > >Yours is not an isolated experience. The company I work for had a >similar problem. The design failed, so they inserted chipscope to probe >the design. The design miraculously started working - before they even >had a chance to use the analyzer. They tried pulling chipscope out, and >it failed again. The solution was to ship it with the analyzer in >place. No one knows why it works, which is a bit freaky, but it does. I >would note that this was before my time - so I don't know the >particulars. > >I would suspect marginal timing is at fault. Inserting chipscope >physically alters the P&R, and may inadvertantly improve timing, >pushing marginal timing just enough to be stable. In my experience this is always due to not properly constraining the timing for the design somewhere. Which just makes me wonder if the tools from Xilinx can produce a list with paths which are not covered by a timing constraint. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 113919
Hi, has anybody worked with a fgpa/dsp board solution from "sundance"? I need some information about the configuration and "bitstream download" in those boards. In the web, they say that you need Code Composer Studio for the DSP and 3L Diamond for FPGA but I want to know if some other tools like ISE, XPS and IMPACT can be used for that. The reference is http://www.sundance.com/web/files/productpage.asp?STRFilter=SMT761Q. Thanks.Article: 113920
Ben Jackson schrieb: >> reg num = 7; > > That's almost certainly wrong. Initial values are ignored during synthesis. -> Create a reset for it! RalfArticle: 113921
Hi, I made that OPB Bus Master-Slave Peripheral that I was enquiring about ... You were right, I dint need to use anything but the OPB manual :) . For generating the bus interface one can either check the manual or by using Create Peripheral Wizard (with the appropriate options) and copy the signals from Xilinx generated IPIF wrapper generated I did Xilinx BFM (Bus Functional Modelling ) to test the IP. This was a really good debug tool , since any protocol violation is reported as an error message in ModelSim. Thanks VenuArticle: 113922
"radarman" <jshamlet@gmail.com> wrote: > > >Yours is not an isolated experience. The company I work for had a >similar problem. The design failed, so they inserted chipscope to probe >the design. The design miraculously started working - before they even >had a chance to use the analyzer. They tried pulling chipscope out, and >it failed again. The solution was to ship it with the analyzer in >place. No one knows why it works, which is a bit freaky, but it does. I >would note that this was before my time - so I don't know the >particulars. > >I would suspect marginal timing is at fault. Inserting chipscope >physically alters the P&R, and may inadvertantly improve timing, >pushing marginal timing just enough to be stable. Well, if I was a customer of yours, I wouldn't be best pleased at that. I like my products to work by decent engineering rather than be miracle powered. Perhaps you sell to the Vatican? I suggest you leave and go and work for another company. Actually, as you're revealing dodgy stuff about what your company does, and you appear to be posting from work, you may not have much choice! :-( Here's a late Crimbo pressie, try Googling "reverse dns". Then look up NNTP-Posting-Host. HTH & HNY, Syms. p.s. Please tell me that Chipscope isn't performing miracles in space guidance systems and helicopters. Lie to me if you have to.Article: 113923
Symon wrote: > Hi Johan, > Do you register all the signals in the IOBs using the dedicated IOB FFs? Rx > and Tx? Are you using global clock buffers fed from the dedicated GCLK pins > to clock these FFs? > If not, then any changes in the timing could bugger everything up if you've > not constrained the timing between the parts properly. The Chipscope thing > could be just coincidence, or maybe slowing the timing brings things back in > to alignment. > HTH, Syms. > > Yes, all signals are registered in the IOBs. Yes, global clock buffers (and GCLK pins) are used. I have been thinking in terms of board de-skew, but it doesn't explain why it works with ChipScope and not without. And it seems like I'm not the only one experiencing what I described earlier, as radarman pointed out. I will look through my constraints once more and also see if I can add some more pipelining in the design itself. I am certain that this is solvable without adding ChipScope. It is just a matter of designing the HW the right way... =) Right now it seems like I've chosen the wrong cost table though, PAR takes ages to complete. /JohanArticle: 113924
"Johan Bernspång" <xjohbex@xfoix.se> wrote in message news:en2va1$9rn$1@mercur.foi.se... > Symon wrote: > > Yes, all signals are registered in the IOBs. Yes, global clock buffers > (and GCLK pins) are used. I have been thinking in terms of board de-skew, > but it doesn't explain why it works with ChipScope and not without. And it > seems like I'm not the only one experiencing what I described earlier, as > radarman pointed out. > > I will look through my constraints once more and also see if I can add > some more pipelining in the design itself. I am certain that this is > solvable without adding ChipScope. It is just a matter of designing the HW > the right way... =) Right now it seems like I've chosen the wrong cost > table though, PAR takes ages to complete. > > /Johan Hi Johan, Are the Rx IOBs using the iob_delay feature to make sure you have negative hold time? Does your UCF file have the IO timing constraints in it? What data rates are the connections? Is the data transfer system source synchronous? BTW, I say adding Chipscope isn't 'solving' the problem. It's just hiding it until it re-appears, invariably one week before your next pay rise appraisal! Cheers, Syms.
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Compare FPGA features and resources
Threads starting:
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