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I have a ALTERA MAX3000A CPLD with two inscriptions: EPM3256AFC256-7 --> commercial temp, speed grade 7 and EPM3256AFI256-10 --> industrial temp, speed grade 10 I bought the industrial one. Are this two CPLDs equivalent??? If yes -> if I buy the commercial, speed grade 7 - is this CPLD equivalent to the industrial temp, speed grade 10??? Thanks for your answers in advance, ManfredArticle: 113726
Hi Dave, I have about the same problem. DDR SDRAM on opb_ddr controller does not work. We have 3 rev.D boards and 2 fail memory tests. Actually we had 2 boards and onyl one worked, then I got one extra as a waranty. This extra does not work either. So if any has a good (proven!!) memory tester I would be happy to make some more tests. Otherwise some explanation from Xilinx guys would do. Cheers, Guru Dave wrote: > I'm using ISE 8.2i and XPS 8.2i with a new Xilinx Starter Kit (the > XC3S500efg320-4 FPGA on a Rev D board) and can not get the DDR SRAM to > pass any memory tests. I have built four or five different memory test > projects including at least one tutorial, all with the same results. The > MicroBlaze communicates to a terminal window, but always reports failures > on the 32-bit, 16-bit, and 8-bit memory tests. :-( > > Does anyone have a known good MicroBlaze memory test project .bit file I > could try just to check that there is no hardware problem? > > It certainly would be nice if Xilinx shipped a few .bit files with the > board just for cases like this. Hint, hint, Xilinx. > > > Thanks, > > ~Dave~Article: 113727
Yaseen Zaidi wrote: > On Post Map and Post Route model simulations intermittently I get few X > bytes. I set up a trace check for source in ModelSim and found out that > it leads to X_BUF with 658 ps pathpulse which connects to vitalbehavior > (gsr, prld, dly of clk, set, rst etc). It's only bit 0 of the bus > that goes to X at times. > > What do I do to get consistent timing? > 1. Perform static timing analysis. The output of this will be the following bits of information: - Maximum clock frequency for each clock in the design. - Setup time of input pins relative to whatever clocks sample those input pins. - Clock to output time of all synchronous output pins. - Propogation delays to all output pins that are combinatorial functions of input pins. 2. Make sure your testbench does not violate any of the above timing. 3. If output signals are blipping to 'X' for a little bit then those signals are outputs of combinatorial logic and not directly out of a flip flop. If this momentary blip is an issue for whatever reason then you need to get rid of it. To get rid of the blip, change the output to be a clocked output. Obviously this changes the function somewhat, delaying the output to occur some Tco after the clock edge but if the signal is not allowed to blip even momentarily then a flip flop is the only output type that help you meet that goal. KJArticle: 113728
"MM" <mbmsv@yahoo.com> wrote in message news:4ur36rF19cplaU1@mid.individual.net... >I am trying to run 2 ChipScope instances connected to two different boards. >Unfortunately, Xilinx doesn't support more than one USB cable... I found in >the past that you can actually have 2 cables running at the same time if >one of them is parallel... My problem now is that my new Dell PC doesn't >have a parallel port (neither does it have a serial port )... So I got >myself a USB to Parallel adapter, but the ChipScope doesn't want to work >through it... It seems that it is only good for a printer. It doesn't even >create a proper virtual LPT port... So, I was wondering if someone knows of >an adapter that will work? > > Thanks, > /Mikhail > Mikhail, How about using VMWare to run another instance of Chipscope? Maybe that would work, you can try their software for free. I've not tried this. HTH, Syms.Article: 113729
Guru schrieb: > Hi Dave, > > I have about the same problem. > DDR SDRAM on opb_ddr controller does not work. We have 3 rev.D boards > and 2 fail memory tests. Actually we had 2 boards and onyl one worked, > then I got one extra as a waranty. This extra does not work either. So > if any has a good (proven!!) memory tester I would be happy to make > some more tests. Otherwise some explanation from Xilinx guys would do. > > Cheers, > > Guru > Hm I wonder - if there are so many issues with DDR on the 3E starterkit how reliable will be the DDR2 memory on the new Spartan-3A kit? AnttiArticle: 113730
Manfred Balik wrote: > I have a ALTERA MAX3000A CPLD with two inscriptions: > > EPM3256AFC256-7 --> commercial temp, speed grade 7 > and > EPM3256AFI256-10 --> industrial temp, speed grade 10 > > I bought the industrial one. > Are this two CPLDs equivalent??? > If yes -> if I buy the commercial, speed grade 7 - is this CPLD equivalent > to the industrial temp, speed grade 10??? > > Thanks for your answers in advance, Manfred Double marking is a standard practice for many chip manufacturers including Lattice. If the part is marked for commercial and industrial with different speed grades, it means the part has been characterized and presumably tested to meet those speed grades at the associated range of temperatures specified for commercial or industrial parts. Generally this double marking is noted in the data sheets and you can "cross-order" the equivalent part using the other number. The price is generally the same, too. If there is no such policy noted in the data sheet, I would suggest ordering the part using the number you need, since there is no guarantee that another batch of parts will be dual-marked and more importantly dual-characterized and tested. Regards, GaborArticle: 113731
On Tue, 19 Dec 2006 18:47:38 +0100, Sylvain Munaut <tnt-at-246tNt-dot-com@youknowwhattodo.com> wrote: >recently I had xst misunderstand > >generic ( > K1 : std_logic_vector(19 downto 0) := x"3eeee"; >); > >... > >constant K2 : std_logic_vector(19 downto 0) := not (K1) + 1; > > >somehow K2 ended up being incorrect ... while modelsim did it like >I expected it. > >constant K2 : std_logic_vector(19 downto 0) := x"00000" - K1; > >works fine ... XST probably should misunderstand that. Which non-standard library is XST using for arithmetic on std_logic_vector, and is Modelsim using a different one? Now if XST and Modelsim disagreed on results using either signed or unsigned type from numeric_std, it would be worth worrying about. - BrianArticle: 113732
On Tue, 19 Dec 2006 11:42:01 -0800, Vangelis <> wrote: >Does anybody know how can I simulate with Modelsim a design that containts a PowerPC in a Virtex-II Pro FPGA? I have done the PowerPC design using the EDK, and I have imported the design in ISE where I have connected it with another design implemented in the FPGA and now I want to simulate the whole design. I tried to create a testbench waveform in ISE, but it didn't work. This isn't very well documented by Xilinx (IMO) but there are two different ways. One is a "bus functional model" simulation which (as I understand it) needs a download from Xilinx and a CoreConnect license from IBM. I'm not sure but I believe this doesn't simulate object code running on the PPC, but provides functional blocks resembling the PPC bus interfaces. The EDK "Getting Started" PDF documentation talks you through the download and license process, then leaves you on your own. Then the Platform Studio User Guide doesn't mention CoreConnect anywhere at all (at least not in the 7.1 documentation), but assumes you are using the other technique. This is the "SmartModels" Swift interface, which provides a full simulation of the PPC, but requires an additional license from Modelsim ($2k or so) for the Swift interface. I can't remember the details of installation, but they are quite well described in the EDK Platform Studio User Guide. This works well enough for me, but the tools don't (at 7.1) support it very well. You build the executable as normal, then "Generate Simulation Files" from the tools menu. This takes quite a while and rebuilds the simulation files for the entire PPC system, even if you have only changed the executable. Recompiling the whole lot in Modelsim takes a very very long time; but (for software only changes) you really only need to recompile the "system_init.vhd" file which loads the BRAMs with the new executable. Software only changes could usefully be streamlined by the tools... Sim time units are bizarre; a 1ns step is too long, but 1ps warns that it is "finer than necessary". (Probably 10 or 100ps is expected, but 1ps works) - BrianArticle: 113733
> Hi Dan, > Gabor's blinkered ideas would work. However, they're not as much fun as > accelerating the LatticeXP PLL to about 0.8773 of the speed of light. If you > do that, the stationary oscillator appears to the PLL to be going at 25MHz. > IME, this method involves messing around with enormous gravitational fields > at event horizons, so watch out for evil red robots. > HTH, Syms. > Thanks, Unfortunately I'm not implicated on astrophysical research but I'll keep that on mind. Dan.Article: 113734
"cpope" <cepope@nc.rr.com> wrote in message news:458893d6$0$16948$4c368faf@roadrunner.com... > Try a USB dock like: > http://www.tigerdirect.com/applications/SearchTools/item-details.asp?EdpNo=1597389&CatId=604 Do you have a reason to believe it will work differently from all other USB-to-LPT adapters? Thanks, /MikhailArticle: 113735
Has anybody tried to write a code for crontroling what you put in a VGA port?? I have a Spartan 3E, and I want to put an image in a monitor. I've created a XPS project with Microblaze and OPB bus, and I've incorporated the VGA Peripheral. Finally I send the pixel values from a C program but there is a problem: The communication is too slow. I can't view a quiet image. Can anybody tell me how can I write a project to print an image into the VGA?. I soppuse I could write a code to access to the sdram, but I don't know how can I get it. Thanks, PabloArticle: 113736
Guys, In a recent thread here on VAF we learnt, more or less, that a large part of the Virtex-4's Cpin of 10pF is due to the large output FETs needed to drive HSTL IV at 48ma. Does the CCLK pin have this problem? If not, where do I obtain an IBIS model representative of the CCLK input? UG071 recommends simulating CCLK as an "LVCMOS_P12" which doesn't exist in the IBIS file. Of course all the other models include the "Cpin of death". Thanks, Syms.Article: 113737
"Symon" <symon_brewer@hotmail.com> wrote in message news:45895e21$1_3@x-privat.org... > > In a recent thread here on VAF we learnt, more or less, that a large part > of > CAF not VAF. Soz.Article: 113738
I need a CIC-Filter, where I can change the decimation factor during runtime.So I inserted a BlackBox-Block in the SystemGenerator Model with the vdh and edn-file from Core-Generator. It works , but the output has a bitwidth of e.g. UFIX_43_0 and I have to convert this to Fix_16_15. I use the Force-Block to force the signed format, but now here is the problem: Where is the binary point? It's always like guessing. There are some formulas of bitgrowth, but I dont get helpful results. I know it works because for some factors I found the correct conversion, but there is no link. Thanks for answering!Article: 113739
Does anyone know if it is possible to define the values in a lookup table using VHDL compatible with Xilinx tools? If so, does anyone have an example? Thanks, DavidArticle: 113740
On 2006-12-20, David <dpmontminy@gmail.com> wrote: > Does anyone know if it is possible to define the values in a lookup > table using VHDL compatible with Xilinx tools? If so, does anyone have > an example? Yes it is possible. The following URL will give some information for example: http://www.xilinx.com/xlnx/xil_ans_printfriendly.jsp?getPagePath=10068&BV_SessionID=@@@@0973742724.1166634752@@@@&BV_EngineID=cccdaddjimklkhecefeceihdffhdfkf.0 (Answer record 10068) /AndreasArticle: 113741
Pablo schrieb: > Has anybody tried to write a code for crontroling what you put in a VGA > port?? I have a Spartan 3E, and I want to put an image in a monitor. > I've created a XPS project with Microblaze and OPB bus, and I've > incorporated the VGA Peripheral. Finally I send the pixel values from a > C program but there is a problem: The communication is too slow. I > can't view a quiet image. > > Can anybody tell me how can I write a project to print an image into > the VGA?. I soppuse I could write a code to access to the sdram, but I > don't know how can I get it. > > Thanks, Pablo 1 add PLB bus 2 put the sdram controller on PLB bus 3 add xilinx VGA or TFT or DVI core (attaches to PLB bus) 4 add PLB2OPB bridge 5 connect the PLB2OPB bridge to your OPB bus done. works. anttiArticle: 113742
Antti wrote: > Pablo schrieb: > > > Has anybody tried to write a code for crontroling what you put in a VGA > > port?? I have a Spartan 3E, and I want to put an image in a monitor. > > I've created a XPS project with Microblaze and OPB bus, and I've > > incorporated the VGA Peripheral. Finally I send the pixel values from a > > C program but there is a problem: The communication is too slow. I > > can't view a quiet image. > > > > Can anybody tell me how can I write a project to print an image into > > the VGA?. I soppuse I could write a code to access to the sdram, but I > > don't know how can I get it. > > > > Thanks, Pablo > > 1 add PLB bus > 2 put the sdram controller on PLB bus > 3 add xilinx VGA or TFT or DVI core (attaches to PLB bus) > 4 add PLB2OPB bridge > 5 connect the PLB2OPB bridge to your OPB bus > > done. > works. > > antti sorry, but I am a completely novice in this area. Could you tell me how can I do that?. Why is it better than OPB?. Could you tell me where can I find some lecture for this? Thanks, againArticle: 113743
Symon, The ISE software will create a pin specific IBIS model for your design. Austin Symon wrote: > Guys, > In a recent thread here on VAF we learnt, more or less, that a large part of > the Virtex-4's Cpin of 10pF is due to the large output FETs needed to drive > HSTL IV at 48ma. > > Does the CCLK pin have this problem? > If not, where do I obtain an IBIS model representative of the CCLK input? > > UG071 recommends simulating CCLK as an "LVCMOS_P12" which doesn't exist in > the IBIS file. Of course all the other models include the "Cpin of death". > Thanks, Syms. > >Article: 113744
David wrote: > Does anyone know if it is possible to define the values in a lookup > table using VHDL compatible with Xilinx tools? If so, does anyone have > an example? > > Thanks, > > David > www.rockylogic.com/freebies.html#LUTArticle: 113745
Brian Drummond wrote: > On Tue, 19 Dec 2006 18:47:38 +0100, Sylvain Munaut > <tnt-at-246tNt-dot-com@youknowwhattodo.com> wrote: > >> recently I had xst misunderstand >> >> generic ( >> K1 : std_logic_vector(19 downto 0) := x"3eeee"; >> ); >> >> ... >> >> constant K2 : std_logic_vector(19 downto 0) := not (K1) + 1; >> >> >> somehow K2 ended up being incorrect ... while modelsim did it like >> I expected it. >> >> constant K2 : std_logic_vector(19 downto 0) := x"00000" - K1; >> >> works fine ... > > XST probably should misunderstand that. > > Which non-standard library is XST using for arithmetic on > std_logic_vector, and is Modelsim using a different one? > > Now if XST and Modelsim disagreed on results using either signed or > unsigned type from numeric_std, it would be worth worrying about. For a +1 operation there is not much that can fail ... Doesn't matter what the vector represent, I expect a +1 to add 1 at the lsb ant that's what it does usually ... SylvainArticle: 113746
Pablo wrote: > Has anybody tried to write a code for crontroling what you put in a VGA > port?? I have a Spartan 3E, and I want to put an image in a monitor. > I've created a XPS project with Microblaze and OPB bus, and I've > incorporated the VGA Peripheral. Finally I send the pixel values from a > C program but there is a problem: The communication is too slow. I > can't view a quiet image. VGA is 640 x 480 x 30frames/sec = 18Mpixels/sec average throughput, with the peak being around 27Mp/s IIRC. If the VGA controller is not getting enough bandwidth (and there should be enough bandwidth on the OPB bus for this, assuming that it does burst transfers) it would be because its bus priority needs to be higher than the other masters on the bus (i.e. the processor). If both masters have the same priority, the xilinx arbiter gives priority to that master which is earlier in the MHS file. Put the VGA before the processor in the MHS and you should be okay. If this causes your software to run too slowly, add a cache on the instruction side. Regards, Erik. --- Erik Widding President Birger Engineering, Inc. (mail) 100 Boylston St #1070; Boston, MA 02116 (voice) 617.695.9233 x207 (fax) 617.695.9234 (web) http://www.birger.comArticle: 113747
Erik Widding wrote: > VGA is 640 x 480 x 30frames/sec = 18Mpixels/sec average throughput, That should have been 60frames/sec. Rest of the numbers are correct. Regards, Erik. --- Erik Widding President Birger Engineering, Inc. (mail) 100 Boylston St #1070; Boston, MA 02116 (voice) 617.695.9233 x207 (fax) 617.695.9234 (web) http://www.birger.comArticle: 113748
"Austin Lesea" <austin@xilinx.com> wrote in message news:embsp1$1kk1@cnn.xsj.xilinx.com... > Symon, > > The ISE software will create a pin specific IBIS model for your design. > > Austin > Hi Austin, Thanks, but I don't think that works for the CCLK pin on V4 which is used to clock configuration data into the device. (CCLK can't be used as general I/O AFAIK.) Thanks, Symon.Article: 113749
On 2006-12-20, Antti <Antti.Lukats@xilant.com> wrote: > > I wonder - if there are so many issues with DDR on the 3E starterkit > how reliable will be the DDR2 memory on the new Spartan-3A kit? DDR2 is simpler than DDR. -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/
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