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=?ISO-8859-1?Q?Johan_Bernsp=E5ng?= <xjohbex@xfoix.se> wrote: >Symon wrote: > >> Hi Johan, >> Do you register all the signals in the IOBs using the dedicated IOB FFs? Rx >> and Tx? Are you using global clock buffers fed from the dedicated GCLK pins >> to clock these FFs? >> If not, then any changes in the timing could bugger everything up if you've >> not constrained the timing between the parts properly. The Chipscope thing >> could be just coincidence, or maybe slowing the timing brings things back in >> to alignment. >> HTH, Syms. >> >> > >Yes, all signals are registered in the IOBs. Yes, global clock buffers >(and GCLK pins) are used. I have been thinking in terms of board >de-skew, but it doesn't explain why it works with ChipScope and not >without. And it seems like I'm not the only one experiencing what I >described earlier, as radarman pointed out. Also check internal signals. I once got stung by using a clock as an input signal. For some reason a clock period constraint doesn't cover such a path. It caused the same symptoms you described. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 113926
On 28 Dec 2006 15:13:40 -0800, "radarman" <jshamlet@gmail.com> wrote: <snip> >Just out of curiosity, is this referring to xapp 445, or something new? <snip> No- the board I'm using is described here: http://tinyurl.com/ygshdp This board can be programmed several ways, but the way I'm using needs *only* the USB connection and a utility supplied with the board. As I said, version 8.1 Impact fails, 8.2 succeeds. I see that the user guide can be downloaded from the above page; that may well answer questions I can't. But beware- it has several errors, and it's only after a colleague was helped by yet a third party that he managed to get anywhere. -- Per ardua ad nauseamArticle: 113927
Symon wrote:
> "Johan Bernspång" <xjohbex@xfoix.se> wrote in message
> news:en2va1$9rn$1@mercur.foi.se...
>> Symon wrote:
>>
>> Yes, all signals are registered in the IOBs. Yes, global clock buffers
>> (and GCLK pins) are used. I have been thinking in terms of board de-skew,
>> but it doesn't explain why it works with ChipScope and not without. And it
>> seems like I'm not the only one experiencing what I described earlier, as
>> radarman pointed out.
>>
>> I will look through my constraints once more and also see if I can add
>> some more pipelining in the design itself. I am certain that this is
>> solvable without adding ChipScope. It is just a matter of designing the HW
>> the right way... =) Right now it seems like I've chosen the wrong cost
>> table though, PAR takes ages to complete.
>>
>> /Johan
>
> Hi Johan,
> Are the Rx IOBs using the iob_delay feature to make sure you have negative
> hold time?
> Does your UCF file have the IO timing constraints in it?
> What data rates are the connections?
> Is the data transfer system source synchronous?
>
> BTW, I say adding Chipscope isn't 'solving' the problem. It's just hiding it
> until it re-appears, invariably one week before your next pay rise
> appraisal!
>
> Cheers, Syms.
>
>
Well, the RX IOBs at the destination has IOBDELAY = NONE. I got the
impression that it was the way to go after browsing through various
appnotes etc. The data transfer is source synchronous, so maybe
inserting a IOBDELAY on the transfer clock would be the way to go. The
transfer rate is 200 MHz by the way.
My UCF does have timing constraints, including the data transfer clock.
However, talking about it, I reviewed the UCF in the destination design
and found a typo there on the constraint on the data clock. That might
be the error I'm looking for (so far I have concentrated mostly on the
source FPGA).
/Johan
From spampostmaster@comcast.net Fri Dec 29 07:29:25 2006
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NNTP-Posting-Date: Fri, 29 Dec 2006 09:27:37 -0600
From: Phil Hays <spampostmaster@comcast.net>
Subject: Re: ChipScope - impact on design or not?
Date: Fri, 29 Dec 2006 07:29:25 -0800
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Nico Coesel wrote:
> In my experience this is always due to not properly constraining the
> timing for the design somewhere. Which just makes me wonder if the tools
> from Xilinx can produce a list with paths which are not covered by a
> timing constraint.
Yes. A few examples of how to produce timing reports with a list of
unconstrained paths follow.
>From the command line:
trce -v 10 -u 1000 design.ncd -o design.twr
(the -u option is for list unconstrained paths)
>From Tcl:
timing_analysis new analysis -name $reportname
timing_analysis set $reportname analysis_type timing_constraint
timing_analysis set $reportname report_datasheet true
timing_analysis set $reportname report_timegroups true
timing_analysis set $reportname analyze_unconstrained_paths 1000
timing_analysis set $reportname paths_per_constraint 10
timing_analysis set $reportname report_name $reportname
timing_analysis set $reportname report_format ascii
timing_analysis run $reportname
>From the GUI:
In the process window
implement design
place and route
post place and route static timing properties:
report uncovered paths | 1000
--
Phil Hays
Article: 113928To discover the unconstrained paths in a design, run trce with the -u option. Regarding the original posting, as well as the followup "design runs with chipscope, but fails to run without", there are lots of specific causes for this, all falling into the category of unconstrained, or misconstrained path. Debugging obscure timing problems is a lot like debugging obscure logic problems. The secret is to add test circuitry that helps isolate the problem area. Once isolated, problem and solution eventually will surface. The statement that the design is marginal was a correct one. I think by adding chipscope, it pushed the design from margininally not working to marginally working. Unfortunately, temp, voltage and process variation will ensure that some units will wind up working only intermittantly. I would start out looking at -u option report. That will tell if there are really unconstrained paths in design. Then look at any asynchronous interfaces, clk domain crossings, etc. These are the big culprits in route specific marginal operation. -- Regards, John Retta Owner and Designer Retta Technical Consulting Inc. "Colorado based Xilinx design consultant" email : jretta@rtc-inc.com web : www.rtc-inc.com "Nico Coesel" <nico@puntnl.niks> wrote in message news:4594dfae.2834004272@news.kpnplanet.nl... > "radarman" <jshamlet@gmail.com> wrote: > >> >>Johan Bernsp=E5ng wrote: >>> I used to believe that ChipScope did not have any impact on the design. >>> I used to. >>> >>> I have two FPGAs communicating on the PCB (LVDS). One of them (called >>> source here) is doing some signal processing and sends the result to the >>> destination FPGA. If I probe (with ChipScope) some internal results of >>> the processing (FFT output) in the source, the data looks fine at the >>> destination. However, if I remove the probe I get some interesting, but >>> rather annoying, bit errors in the data received (and probed) at the >>> destination. >>> >>> Before probing at the source I thought this was an issue of signal >>> integrity on the PCB, but the probing proved me wrong on that point. The >>> source is a V2000 device and without the probing about 90% of BRAM and >>> mults are utilized. I would think that by adding a ChipScope core PAR >>> would have more troubles meeting timing constraints, and consequently >>> deliver a design more prone to bit errors... >>> >> >>Yours is not an isolated experience. The company I work for had a >>similar problem. The design failed, so they inserted chipscope to probe >>the design. The design miraculously started working - before they even >>had a chance to use the analyzer. They tried pulling chipscope out, and >>it failed again. The solution was to ship it with the analyzer in >>place. No one knows why it works, which is a bit freaky, but it does. I >>would note that this was before my time - so I don't know the >>particulars. >> >>I would suspect marginal timing is at fault. Inserting chipscope >>physically alters the P&R, and may inadvertantly improve timing, >>pushing marginal timing just enough to be stable. > > In my experience this is always due to not properly constraining the > timing for the design somewhere. Which just makes me wonder if the > tools from Xilinx can produce a list with paths which are not covered > by a timing constraint. > > -- > Reply to nico@nctdevpuntnl (punt=.) > Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 113929
Nicolas Matringe wrote: > Marlboro a =E9crit : > > > The tool is smart enough to know that you're not going to use it, so it > > removes the redundant blocks. > > This is utterly wrong (besides, never rely too much on the tool's > smartness). The tool simply sees that the two logic constructs have the > same inputs and the same behaviour so it removes one of them. What's about the output? If you don't have an output then the tool knows that you not gonna use it. As a result, it will remove the redundance. Sometimes I ran into this too, what I did was making up a dummy output for the second logic > I haven't used ISE in some time but I know for sure that there is an > option somewhere to keep it from removing redundant or equivalent > logic. Or maybe it is an attribute. Search for "preserve" in the > documentation. That rings a bell >=20 > NicolasArticle: 113930
The Rocket IO appear on the dedicated pins detiled in the data sheet pinout list. They are not relocatable, nor reprogrammable. Once a particular MGT is assigned to be used, it expects its signals to be on the pins it is already assigned. AustinArticle: 113931
Look up the keywords: SAVE KEEP If two identical blocks (including inputs) have each an output, if recognised, the logic is removed for one, and both outputs are driven from the remaining block. Why would you want to have two blocks that did exactly the same thing? With fully buffered interconnect, there is no delay penalty. AustinArticle: 113932
Marlboro a =E9crit : > Nicolas Matringe wrote: > > Marlboro a =E9crit : > > > > > The tool is smart enough to know that you're not going to use it, so = it > > > removes the redundant blocks. > > > > This is utterly wrong (besides, never rely too much on the tool's > > smartness). The tool simply sees that the two logic constructs have the > > same inputs and the same behaviour so it removes one of them. > > What's about the output? If you don't have an output then the tool > knows that you not gonna use it. As a result, it will remove the > redundance. Sometimes I ran into this too, what I did was making up a > dummy output for the second logic Ah sorry, in that case this is perfectly right. But I think the OP was talking about replicated logic with its outputs used. NicolasArticle: 113933
"Austin" <austin@xilinx.com> wrote in message news:en3fg3$10v3@cnn.xsj.xilinx.com... > > Why would you want to have two blocks that did exactly the same thing? > To detect and/or mitigate against SEUs? Cheers, Syms.Article: 113934
> Has anyone here tried running ise or other tools on a mac under parallels ? My MacPro has booted into OS X 3 times - once to run Bootcamp and twice to do system software updates; it's been running XP ever since. The latest beta of Parallels lets you run the Windows installed on the Bootcamp partition. Previous versions required a separate install. Unfortunately in this mode, Windows must be reauthorized whenever switching between Parallels and Bootcamp. When there is a release version of Parallels that runs the Bootcamp Windows, I'll probably try it. There is also CrossOver Mac http://www.codeweavers.com/products/cxmac/ which is a WINE port. One user reports some ISE 8.2 compatibility. Of course, what we really need is a Mac port of the Xilinx tools. --- Joe Samson Pixel VelocityArticle: 113935
mankin18@gmail.com wrote: > On Dec 29, 4:03 pm, manki...@gmail.com wrote: > > On Dec 29, 3:56 pm, Ben Twijnstra <btwijns...@gmail.com> wrote: > > > > > > > > > > > > > manki...@gmail.com wrote: > > > > > > On Dec 29, 12:32 pm, Ben Jackson <b...@ben.com> wrote: > > > >> On 2006-12-29, manki...@gmail.com <manki...@gmail.com> wrote: > > > > > >> > that something is wrong with my code. Please advice. > > > > > >> > reg num = 7;That's almost certainly wrong. I can't vouch for > > > >> > the rest. > > > > > >> -- > > > >> Ben Jackson AD7GD > > > >> <b...@ben.com>http://www.ben.com/ > > > > > > Thanks for prompt response! but can you elaborate a bit more?I'm a VHDL guy, but I think it should be > > > > > reg [2:0] num; > > > > > Best regards, > > > > > Ben- Hide quoted text -- Show quoted text -ben! thanks for clue. Let me try and i'll get back to you as i'm also > > not a verilog guy;-) > > > > Cheers- Hide quoted text -- Show quoted text - > > 0ops! and no difference, any idea? > > > -- I haven't checked in detail but move "num = num - 1;" inside the check for SCK rising otherwise it gets decremented for every clockcycle not every SCK cycle. easy spot if you run a simulation ;) -LasseArticle: 113936
Symon wrote: > "Austin" <austin@xilinx.com> wrote in message > news:en3fg3$10v3@cnn.xsj.xilinx.com... > >>Why would you want to have two blocks that did exactly the same thing? >> > > To detect and/or mitigate against SEUs? > Cheers, Syms. > > In which case, you should either use the TMR Tool(tm), or be very very careful (not recommended without help from Xilinx). Many people have tried to perform manual methods to perform such mitigation, but without knowledge of how the tools work, and how the hardware actually works (not the fantasy presented by FPGA Editor), they all fail miserably. Even the experts can make mistakes, and find their design has worse performance than an unmitigated one (adding anything at all, increases the failure rate, unless done properly). If anyone is serious about mitigation (in spite of the excellent SEU FIT rates -- 10 to 30 times BETTER than an equivalent 90 or 65nm ASIC or ASSP*), then I suggest you work with your disti or Xilinx FAE, who knows how to do it. Austin * Don't take my word for it, look it up for yourself. At SELSE II (2006), the industry consensus was ~1000 FIT/Mb for logic AND SRAM at 90nm and below for ASIC and ASSP. We publish our FIT rates. And you can see them anytime. If you really want FIT rates in the single digits, you have techniques in our FPGAs to get there (TMR, ECC, etc.).Article: 113937
Symon wrote: > "radarman" <jshamlet@gmail.com> wrote: > > > > > >Yours is not an isolated experience. The company I work for had a > >similar problem. The design failed, so they inserted chipscope to probe > >the design. The design miraculously started working - before they even > >had a chance to use the analyzer. They tried pulling chipscope out, and > >it failed again. The solution was to ship it with the analyzer in > >place. No one knows why it works, which is a bit freaky, but it does. I > >would note that this was before my time - so I don't know the > >particulars. > > > >I would suspect marginal timing is at fault. Inserting chipscope > >physically alters the P&R, and may inadvertantly improve timing, > >pushing marginal timing just enough to be stable. > > Well, if I was a customer of yours, I wouldn't be best pleased at that. I > like my products to work by decent engineering rather than be miracle > powered. Perhaps you sell to the Vatican? > > I suggest you leave and go and work for another company. Actually, as you're > revealing dodgy stuff about what your company does, and you appear to be > posting from work, you may not have much choice! :-( > Here's a late Crimbo pressie, try Googling "reverse dns". Then look up > NNTP-Posting-Host. > HTH & HNY, Syms. > > p.s. Please tell me that Chipscope isn't performing miracles in space > guidance systems and helicopters. Lie to me if you have to. It isn't that uncommon for these embedded logic analyzers to alter performance, and it isn't a poor reflection on my employer. This was their _first_ FPGA based system, and it was a _prototype_ - not a production system. It shipped in the sense that it was designed under contract, but it is incapable of flying - it was built out evaluation boards and ribbon cables. It has only been in the last few years that they felt FPGA's could reasonably compete with purely optical/analog solutions, and the system in question was a testbed to validate that premise. The actual production hardware doesn't use FPGA's at all. When that prototype worked, and exceed the performance of the legacy systems, they decided to start moving in that direction, and started hiring more EE's and FPGA developers to support it - hence why I am here. I would say that by recognizing their limitations, and hiring skilled EE's and FPGA developers, shows that they do care about their products. Quite frankly, I feel better knowing that - because my previous employer didn't. I know I feel comfortable with quality of the products that go out of here, and from what I've heard, so do our customers. I won't go into detail, but our systems are considered top notch in the field that they serve. Now, when your done patting yourself on the back, why don't you consider this. The prototype in question was developed in XPS, using stock components for the firmware. The guys who did the firmware weren't FPGA developers, they were software developers - and they didn't write any of the HDL themselves. I've noticed that ISE is constantly spitting out warnings about some of the stuff that comes out of XPS, so, I would argue that perhaps the dodgy stuff came from Xilinx, not the guys who did the original design.Article: 113938
Hi Colin, Thanks for the answer. This is strange. I guess i am confused with the results from software programs I used such as the one on this website http://www.zorc.breitbandkatze.de/crc.html and what I get in hardware. I would expect it to the same but i am not sure that it is. I am trying to implement a MAC in an FPGA and I need to be sure that what I am sending to the PHY and out on the wire will be understood by the receiving MAC from a NIC card for example. So if I send 00 00 12 33 FF FF to the PHY from the FPGA, this is what is sent on the WIRE from the PHY 00 00 84 CC FF FF lsb first for each byte So I feed the original data "00 00 12 33 FF FF" as is through the EASICS module with initialization of all 1, I get the <RESIDUE> AA C5 98 B0 Now it clearly states in the 802.3 specs that "The bit sequence is complemented and the result is the CRC" So I need to complement the <RESIDUE> to get the <CRC> : 55 3A 67 4F Then I need to send it MSB first since the 802.3 spec says "The 32 bits of the CRC value are placed in the frame check sequence field so that the x31 term is the leftmost bit of the first octet, and the x0 term is the right most bit of the last octet. (The bits of the CRC are thus """transmitted""" in the order x31, x30..., x1, x0.)" So I need to switch the bits in each byte before appending to the Packet Therefore the <CRC> becomes the <FCS> AA 5C E6 F2 So the full packet is 00 00 12 33 FF FF AA 5C E5 F2 but what is sent on the wire is 00 00 84 CC FF 55 3A 67 4F On receiving , I guess i need to flip the CRC back to 55 3A 67 4F before feeding it into the EASICS module to get the magic number. I hope I got it right this time. This took a while. I think i will just recompute the packet and compare the incoming FCS with that. It might be easier. Thanks a lot, I really appreciate you taking the time to help me out, AmishArticle: 113939
Phil Hays <spampostmaster@comcast.net> wrote: >Nico Coesel wrote: > >> In my experience this is always due to not properly constraining the >> timing for the design somewhere. Which just makes me wonder if the tools >> from Xilinx can produce a list with paths which are not covered by a >> timing constraint. > >Yes. A few examples of how to produce timing reports with a list of >unconstrained paths follow. > > >From the command line: > >trce -v 10 -u 1000 design.ncd -o design.twr >(the -u option is for list unconstrained paths) > > >From Tcl: > >timing_analysis new analysis -name $reportname >timing_analysis set $reportname analysis_type timing_constraint >timing_analysis set $reportname report_datasheet true >timing_analysis set $reportname report_timegroups true >timing_analysis set $reportname analyze_unconstrained_paths 1000 >timing_analysis set $reportname paths_per_constraint 10 >timing_analysis set $reportname report_name $reportname >timing_analysis set $reportname report_format ascii >timing_analysis run $reportname > > >From the GUI: > >In the process window > implement design > place and route > post place and route static timing properties: >report uncovered paths | 1000 > > >-- >Phil Hays > Thanks for the info! (also to John) -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 113940
Hi radarman, First let me apologise for my terrible piss-take/smart-ass posting style, occasionally it gets me in trouble. Anyway, I'm glad you took the opportunity to post and clarify exactly the situation when your company apparently 'shipped' something that was maybe not of the highest quality. I was trying to make the point that this is a public forum and it's not hard (a dumbass like me can do it) for folks to find out who employs you. Including your competitors. If you go back and read your original post, would you put that on your company website? After all's said and done, we're agreed that Chipscope can change the operation of a design. To stop this happening the designer must be very careful with their timing constraints. Best regards, Syms. From spampostmaster@comcast.net Fri Dec 29 11:00:20 2006 Path: newsdbm02.news.prodigy.net!newsdst02.news.prodigy.net!prodigy.com!newscon02.news.prodigy.net!prodigy.net!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.comcast.com!news.comcast.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 29 Dec 2006 12:58:32 -0600 From: Phil Hays <spampostmaster@comcast.net> Subject: Re: ChipScope - impact on design or not? Date: Fri, 29 Dec 2006 11:00:20 -0800 User-Agent: Pan/0.14.2.91 (As She Crawled Across the Table) Message-Id: <pan.2006.12.29.19.00.20.249802@comcast.net> Newsgroups: comp.arch.fpga References: <en11k1$f7u$1@mercur.foi.se> <1167346713.247454.132380@s34g2000cwa.googlegroups.com> <4594dfae.2834004272@news.kpnplanet.nl> <pan.2006.12.29.15.29.25.244820@comcast.net> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 33 NNTP-Posting-Host: 67.171.9.122 X-Trace: sv3-jYJfR9e3IbyYSas1mmb2FpgjGij7IIUzLwhiUy5MLJFff+SnfX4hfNPTwWHqP6e96YKPk0FfmN+pOz2!gpYpVSRTKUdcoOvKWBJQsBCBau05DPvS37gjPoTvnU/YTGgy6GAjyd09J113L1Y0TAPxTxeHau8d!yWuuD6Y= X-Complaints-To: abuse@comcast.net X-DMCA-Complaints-To: dmca@comcast.net X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.32 Xref: prodigy.net comp.arch.fpga:125060 X-Received-Date: Fri, 29 Dec 2006 13:58:42 EST (newsdbm02.news.prodigy.net) Phil Hays wrote: This part got munged in posting. I'll try again. >From Tcl: timing_analysis new analysis -name $reportname timing_analysis set $reportname analysis_type timing_constraint timing_analysis set $reportname report_datasheet true timing_analysis set $reportname report_timegroups true timing_analysis set $reportname analyze_unconstrained_paths 1000 timing_analysis set $reportname paths_per_constraint 10 timing_analysis set $reportname report_name $reportname timing_analysis set $reportname report_format ascii timing_analysis run $reportname Blank lines added to prevent unwanted wrapping. Sorry about that. -- Phil HaysArticle: 113941
"Alex Gibson" <news@alxx.org> schrieb im Newsbeitrag news:4vk1voF1c9aqjU1@mid.individual.net... > > "Antti Lukats" <antti@openchip.org> wrote in message > news:em9gsm$hg8$1@online.de... >> PicoBlaze C compiler has been available for some time already, >> but until yesterday I never tried it. >> But today when I type: >> >>>start build.bat >> >> then the following C file > > Will this work with 7.1 or 7.2 ? or only 8.1 or 8.2 ? > the only fpga tool required is data2mem - for the picoblaze versions can be that 7.1 is too old (does not support parity bits) I did only check with 8.1 and 8.2 a opensource utility is also in development to replace the data2mem, but no deadline on that AnttiArticle: 113942
Symon wrote: > Hi radarman, > First let me apologise for my terrible piss-take/smart-ass posting style, > occasionally it gets me in trouble. > Anyway, I'm glad you took the opportunity to post and clarify exactly the > situation when your company apparently 'shipped' something that was maybe > not of the highest quality. > I was trying to make the point that this is a public forum and it's not hard > (a dumbass like me can do it) for folks to find out who employs you. > Including your competitors. If you go back and read your original post, > would you put that on your company website? > After all's said and done, we're agreed that Chipscope can change the > operation of a design. To stop this happening the designer must be very > careful with their timing constraints. > Best regards, Syms. No problem - I was a bit pissy myself. I normally connect through a private proxy service, but I haven't had the chance to get my network at home completely working since the move. Normally, when you trace it back, my posts appear to originate from 192.168.x.x address, through my home ISP's network. :) The heads up is a good point, though. I will be more careful about posting potentially harmful information in the future, regardless of my network settings. After re-reading my original post, I could see how that could be potentially damaging out of context. Thanks, -SethArticle: 113943
Johan Bernsp=E5ng wrote: > Maybe delivering the design with ChipScope still in it is my only > choice, but it doesn't feel very good. "Test what you fly, fly what you test".Article: 113944
tersono wrote: > On 28 Dec 2006 15:13:40 -0800, "radarman" <jshamlet@gmail.com> wrote: > > <snip> > >Just out of curiosity, is this referring to xapp 445, or something new? > <snip> > > No- the board I'm using is described here: > > http://tinyurl.com/ygshdp > > This board can be programmed several ways, but the way I'm using needs > *only* the USB connection and a utility supplied with the board. As I > said, version 8.1 Impact fails, 8.2 succeeds. > > I see that the user guide can be downloaded from the above page; that > may well answer questions I can't. But beware- it has several errors, > and it's only after a colleague was helped by yet a third party that > he managed to get anywhere. > -- > Per ardua ad nauseam Hmm - I'm rolling a new board, so I'm looking into configuration options. I'm planning on using a 16Mb Atmel flash. Even after loading the configuration data, there will be adequate room (~87kB with a XC3S250E configuration file loaded) left over for program and settings storage. (I'll treat it lilke an EEPROM once the system is running) Are there any flash based xilinx config memories that you can write (easily) after configuration? (equivalent to using the SPI flash)Article: 113945
glen herrmannsfeldt wrote: > There are PCI parallel ports, and probably not to expensive. MM wrote: > PCI is out of fashion too :) This PC of mine only has PCI Express and only 2 > slots altogether. If you're not already using both slots, there are PCI-e parallel cards, and they're not too expensive. Check IOgear.Article: 113946
mankin18@gmail.com ha scritto: > Hello Folks, > I'm writting a slave SPI code for my FPGA and very sure that > my master is generating the right SPI but somehow slave is unable to > decode it. I've never used the verilog before so it might be possible > that something is wrong with my code. Please advice. > _________________________________________________________________________ > > module test_spi(led,MOSI,SS,SCK,clk); > > output [7:0] led; > > input MOSI, SS, SCK, clk; > > wire MOSI; > wire SS; > wire SCK; > wire clk; > > reg num = 7; > reg [7:0] temp = 0; > reg SCK_LAST; > reg SCK_NOW; > reg [7:0] led; > > > always @(posedge clk) > > begin > if (!SS) > begin > SCK_LAST = SCK_NOW; > SCK_NOW = SCK; > if((SCK_LAST==0)&(SCK_NOW==1)) // check SCK is rising > edge > begin > if (num < 8) // 8 bits counter > begin > if (!MOSI) > begin > temp = (temp << 1); //1 bit-shift and store it to temp when > receiving "0" > end > else > begin > temp = ((temp << 1)|8'b00000001); //1 bit-shift and store it to temp > when receiving "1" > end > if (num == 0) > begin > led = temp; //output to the LED on the board > num = 10; > end > end > end > num = num - 1; > end > else > begin > num = 7; //reset counter and temp store > temp = 8'b0; > end > > end > > endmodule > > _________________________________________________________________________ > > > Thanks for your time. simply stated you should study Verilog more seriously. Especially topics like blocking and non-blocking assignments and how they are synthesized.Article: 113947
In article <4vk1vpF1c9aqjU2@mid.individual.net>, Alex Gibson <news@alxx.org> wrote: > "Joseph" <joseph.yiu@obviously-not-a-valid-domain.com> wrote in message > news:ekk4rt$4ma$1@cam-news1.cambridge.arm.com... > > Hi all, > > > > I wonder if anyone here are in the same situation as me. > > I am think of buying a new PC, but wondering if I should > > wait for Windows Vista become available first. > > Have anyone try running FPGA tools (Xilinx Webpack, > > Modelsim XE, Quartus, Cygwin) on Windows Vista beta? > > Does it work okay? > > Or should I get a "Vista capable" PC now and upgrade later? > > (sound too much hassle to me, but it might be better?) > > Thanks. > > > > regards, > > > > Joe > > Has anyone here tried running ise or other tools on a mac under parallels ? > > parallels is similar to vmware. > Lets you run windows in a window on a mac. > http://www.parallels.com/en/products/workstation/mac/ > > Can also run linux in a window if you can't find what you need in fink or > darwin ports > collections. Has anyone run the Linux version of the ISE under Parallels on a Mac? (Or VMWare's product?) (The license for the less-expensive versions of Vista makes it illegal to run under virtualization systems like Parallels.) -- David M. Palmer dmpalmer@email.com (formerly @clark.net, @ematic.com)Article: 113948
In article <4vk1vpF1c9aqjU2@mid.individual.net>, "Alex Gibson" <news@alxx.org> wrote: > "Joseph" <joseph.yiu@obviously-not-a-valid-domain.com> wrote in message > news:ekk4rt$4ma$1@cam-news1.cambridge.arm.com... > > Hi all, > > > > I wonder if anyone here are in the same situation as me. > > I am think of buying a new PC, but wondering if I should > > wait for Windows Vista become available first. > > Have anyone try running FPGA tools (Xilinx Webpack, > > Modelsim XE, Quartus, Cygwin) on Windows Vista beta? > > Does it work okay? > > Or should I get a "Vista capable" PC now and upgrade later? > > (sound too much hassle to me, but it might be better?) > > Thanks. > > > > regards, > > > > Joe > > Has anyone here tried running ise or other tools on a mac under parallels ? > > parallels is similar to vmware. > Lets you run windows in a window on a mac. > http://www.parallels.com/en/products/workstation/mac/ Yup. Using Altera Quartus 6.x and an fpga4fun.com Pluto-II (Cyclone board). Mac Pro quad-Xeon w/ OSX 10.4.8 and XP-SP2 under Parallels. Using a Prolific PL-2303 USB-serial adapter to program the FPGA board, installed the Windows drivers into the virtual XP machine under Parallels, and enabled visibility of the USB device so Windows could pick it up as a COM port. The fpga4fun FpgaConfig tool works fine through this arrangement. I've not done anything using a USB-JTAG pod, or anything like that yet. Parallels' "Coherence" mode is really good for this, where the two desktops are visually co-mingled [1][2]. You have to see it, it works very well. Much better than just "Windows in a window", esp. on a big display. I'm also using the shared folder mode and keeping all my project files in a folder outside of the XP disk image, so if I want to do lengthy editing in BBEdit (or invoke BSD tools in OS X), the files are directly accessible in both environments. One thing I have not tried since I don't have a Boot Camp bootable partition, is the newer Parallels mode where it can run such a partition as a VM. Rob [1] http://creativefriday.com/parallels.html [2] http://arstechnica.com/journals/apple.ars/2006/12/13/6274 -- Posted via a free Usenet account from http://www.teranews.comArticle: 113949
Joseph wrote: > Some existing software will eventually move over to Vista. Don't even think about this as being a possibility. Windows XP was released (on my birthday) in 2001. There is almost no software that requires XP, that will not also run on Windows 2000. It is likely that another six years from now, there will STILL be practically no software released that requires either Windows Vista or even XP. >From a productivity standpoint, Vista is a negligible cosmetic upgrade from XP, whatever Microsoft says. If you need a computer now, buy it NOW. If you do not need a computer now, wait as long as you can - because you'll get more hardware for less money.
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