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> I have taken a look at the RAM Module. There is some more information > on the RAM chips: > > 0516 1-1 > MT 46V32M8 > TG -5B G > > What does this mean and how can I use it to find the correct > simulation model? Sorry, did not read this before writing the previous email ;) Look for a model of a Micron chip like : MT46V32M8-5BG or something. Note you'll have to instantiate the model 16 times (since you got 16 chips on your RAM stick) and connect the nets accordingly.Article: 122601
On 1 aug, 12:34, Dolphin <Karel.Dep...@gemidis.be> wrote: > On 1 aug, 12:11, ac...@in.tum.de (Georg Acher) wrote: > > > > > Dolphin <Karel.Dep...@gemidis.be> writes: > > >Hello, > > > >We have implemented a variable phase shift in a spartan 3E device. The > > >phase shift can be set with a register. Normally the PSDONE signal > > >should go high when a phase shift is performed. This happens but takes > > >a long time (several minutes). The datasheet says : > > > >"The phase adjustment might require as many as 100 CLKIN > > >cycles plus 3 PSCLK cycles to take effect, at which point the > > >DCM's PSDONE output goes High for one PSCLK cycle. > > >This pulse indicates that the PS unit completed" > > > >However it seems that our design is much slower... > > >The DCM that does the phase shift gets its clock from another DCM. > > >Could it be that there is too much jitter on this clock? > > > >Anybody had a similar problem? > > > Are you on the phase shift limits? Then it takes almost forever, and 3E has no > > status pin for the limit detection... > > -- > > Georg Acher, ac...@in.tum.de > > http://www.lrr.in.tum.de/~acher > > "Oh no, not again !" The bowl of petunias > > Hello Georg, > The input clock is 115MHz (=8.7ns). This allows for a maximum of > 20*(8.7-3) = 114steps. We are only doing 100 steps... > > Thanks for the information, > Karel We have tested this range. And it looks like all steps are slow. The first 10 steps are as slow as the last 10 steps. best regards, KarelArticle: 122602
Dolphin <Karel.Deprez@gemidis.be> writes:
>We have tested this range. And it looks like all steps are slow. The
>first 10 steps are as slow as the last 10 steps.
I have one design where the shift range is asymmetrical. For a phase
calibration, I moved the phase 60 steps back and then 120 forward. Depending on
the routing, the backward steps worked or blocked after a few steps. I only
noticed it after doing a check of PSDONE instead of a simple fixed wait loop.
Are you sure that the DCM is already locked when doing the phase shift?
--
Georg Acher, acher@in.tum.de
http://www.lrr.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 122603On 1 aug, 13:31, ac...@in.tum.de (Georg Acher) wrote: > Dolphin <Karel.Dep...@gemidis.be> writes: > >We have tested this range. And it looks like all steps are slow. The > >first 10 steps are as slow as the last 10 steps. > > I have one design where the shift range is asymmetrical. For a phase > calibration, I moved the phase 60 steps back and then 120 forward. Depending on > the routing, the backward steps worked or blocked after a few steps. I only > noticed it after doing a check of PSDONE instead of a simple fixed wait loop. > > Are you sure that the DCM is already locked when doing the phase shift? > > -- > Georg Acher, ac...@in.tum.de > http://www.lrr.in.tum.de/~acher > "Oh no, not again !" The bowl of petunias The DCM is locked before we start doing the phase shift. KarelArticle: 122604
On Wed, 01 Aug 2007 02:35:12 -0700, Sebastian Goller <sego@hrz.tu-chemnitz.de> wrote: >> >> Kingston makes DIMMs not RAMs. You can find RAM models on Micron's >> website. > >I have taken a look at the RAM Module. There is some more information >on the RAM chips: > >0516 1-1 >MT 46V32M8 >TG -5B G > >What does this mean and how can I use it to find the correct >simulation model? This is a Micron Technology RAM; look for a Micron model which matches 46V32M8 - or find how Micron translate device markings to part numbers. In the event you need a VHDL model, Micron may not offer VHDL models for newer devices for some reason, you may need a model from the Hynix equivalent part. Re: the error at pointer = 1152 - this is an odd number. Does this error coincide with a refresh cycle? - BrianArticle: 122605
> Re: the error at pointer = 1152 - this is an odd number. Does this error > coincide with a refresh cycle? > > - Brian Hi Brian, I have no idea since I am currently testing the design on the board. After I have a simulation model for the DDR RAM I can check this in the simulation.Article: 122606
Hi PFC and Brian, thanks alot for your answers. I am now about to find out, which RAM model I can use and ... believe it or not - I have some trouble. ;-) The datasheet of the Kingston DIMM says that this is DDR266 with a clock cycle time of 7.5 ns. CL = 2.5 Like Brian already said the RAM modules are Micron products. According to the Micron datasheets TG -5B G means that this is a RAM module with a clock cycle time of 5.0 ns. CL = 3.0. The Appendix G means Revision x4, x8. I have no idea what this means. It does not seem to be very important. The problem is that TG -5B is only available for DDR400B on the Micron page. There are two models available: MT46V32M8P-5B MT46V32M8TG-5B The only difference is the package which should not be important for the simulation. So the question is: Can I use this model? I am asking this question before I give it a try, because I know it will be a lot of fun to implement this model in my Xilinx EDK design.Article: 122607
On Aug 1, 9:24 am, "HT-Lab" <han...@ht-lab.com> wrote: > "Ioiod" <a...@tht.com> wrote in message > > news:7NTri.12212$eY.8991@newssvr13.news.prodigy.net... > > > On Xilinx's website, Webpack product-description no longer lists > > Windows 2000 as a supported O/S. I'm currently using Webpack 9.1i.03 on > > a Windows 2000 machiine. > > > Will I have problems if I try to upgrade to Webpack 9.2? > > Not sure if it helps but the full ISE 9.2.01i seems to be running fine on my > win2k machine. I also checked the supported OS of ISE92 and indeed win2k is > no longer listed :-( > > Hanswww.ht-lab.com > > Windows 2000 is not a supported OS from ISE 9.2i onwards. It might still work but was not tested on it. As Hans said it works fine for him which is a good sign :)Article: 122608
On Jul 30, 4:28 am, Philipp Klaus Krause <p...@spth.de> wrote: > This is good news, I didn't know that people are working on synthesis > backends. Was there a post on geda-user about it? Dunno ... don't watch that email. Just relayed a comment from private email from Steve. I responded because of your unkind, broad, unqualified, slamming assessment of Steve's work: > On Jul 27, 4:42 am, Philipp Klaus Krause <p...@spth.de> wrote: >> They used Icarus Verilog for synthesis. Synthesis capability has been >> removed from icarus Verilog (though the author hopes to reintegrate it >> one day) since it was very broken and buggy. Development branches are expected to be sometimes broken and buggy, but you unjustifiably slammed Steve's work without that qualification. I, and others, have used Steve's synthesis in past stable releases without problems .... as well as Steve, for paying work. The issues I've had with it have all been relatively minor ... and not unlike similar problems with vendors tool chains. Not knowing where people are using it and NOT having problems, does give most open source developers a vacumn for judging both what is being used, and how much.Article: 122609
On Jul 26, 6:07 pm, davem <david.maccu...@googlemail.com> wrote: > My version ofGtkWave(3.81) doesn't show the Signal Search Tree (SST) > window by default either. You can bring it up by selecting Signal > Search Tree from the Search menu. Or you can use the shortcut Shift- > Alt-T. 1) Upgrade to the 3.x series. The latest is 3.0.30. 2) Make sure you are compiling against gtk v2.8 or higher. The collapsing widget needed for the integrated tree doesn't exist in earlier versions of the toolkit. > When usingGtkWave, I can't show up vhdl signals created from > enumerated types such as state vectors. I'm think older versions ofGtkWavedid show enumerated types, but I'm not sure. Anyone else had > this problem? Nothing changed in the viewer; perhaps the dumper in your vhdl simulator did. To see enumerated types your dumper needs to support it (e.g., using the "s" gtkwave extension for VCD) or you need to use an external process/file filter that converts values to text strings. See the pdf user manual for specifics. -tArticle: 122610
Does there exist a 64-bit Linux version of Xilinx Webpack? I see the programming tools are available for Linux as 64-bit... When browsing the Webpack service packs, there is a 64-bit Linux service pack. Is this for the 64-bit programming tools, or is there a 64-bit Webpack hiding someplace? Thanks, -Chris -- | Christopher Cole, Cole Design and Development cole@coledd.com | | Embedded Electronics and Software Design http://coledd.com |Article: 122611
On Aug 1, 7:13 am, "jacob...@xilinx.com" <naude.j...@gmail.com> wrote: > On Aug 1, 9:24 am, "HT-Lab" <han...@ht-lab.com> wrote: > > > > > "Ioiod" <a...@tht.com> wrote in message > > >news:7NTri.12212$eY.8991@newssvr13.news.prodigy.net... > > > > On Xilinx's website, Webpack product-description no longer lists > > > Windows 2000 as a supported O/S. I'm currently using Webpack 9.1i.03 on > > > a Windows 2000 machiine. > > > > Will I have problems if I try to upgrade to Webpack 9.2? > > > Not sure if it helps but the full ISE 9.2.01i seems to be running fine on my > > win2k machine. I also checked the supported OS of ISE92 and indeed win2k is > > no longer listed :-( > > > Hanswww.ht-lab.com > > Windows 2000 is not a supported OS from ISE 9.2i onwards. It might > still work but was not tested on it. As Hans said it works fine for > him which is a good sign :) I understand Xilinx's position on this completely. They can't devote effort to verifying that their application runs on a platform that is (soon to be) no longer supported. My opinion is that as that platform acquires more and more features, it becomes less suitable for running CAD programs. Any CAD, not just ISE. My concern is that I don't see a stable replacement in the near future. It really isn't fair to Xilinx to have them support the large number of popular Linux systems. One possible outcome is that I will need to dedicate a machine to just running ISE. This really isn't as bad as it seems; I can buy a complete system for less than I've paid for a single FPGA (I did a design with a XC2V8000 once :). Just my opinions, G.Article: 122612
Martin, One thing that I noticed in your error message was that your ISE install was in the 'Program Files' folder. This may or may not be related to the error, but I would highly recommend that you install the tools in a directory with no spaces. Try installing to the root as Xilinx_9.1 and see if the error goes away. Repost if the error remains and we can go from there. -David <martin.leibetseder@ge.com> wrote in message news:1185962097.609559.126020@57g2000hsv.googlegroups.com... > hi, > > i get this message when i run "map". > > Using target part "5vlx30ff324-3". > Mapping design into LUTs... > Running directed packing... > Constraining slice packing based on guide NCD. > Running delay-based LUT packing... > FATAL_ERROR:Portability:PortDynamicLib.c:358:1.27 - dll open of > library > <C:/Program Files/Xilinx_ISE_9_1i/xilinx/bin/nt/ > libPlXil_DesCheck.dll> failed > due to an unknown reason. Process will terminate. For more > information on > this error, please consult the Answers Database or open a WebCase > with this > project attached at http://www.xilinx.com/support. > > Process "Map" failed > > > Could somebody help me? >Article: 122613
Chris, WebPACK support for Linux is only 32-bit. See http://www.xilinx.com/ise/logic_design_prod/webpack.htm An alternative is to request an evaluation DVD which does support 64-bit Linux. See http://www.xilinx.com/ise_eval/index.htm -David "Christopher Cole" <cole@scoob.coledd.com> wrote in message news:46b0a745$0$10343$4c368faf@roadrunner.com... > Does there exist a 64-bit Linux version of Xilinx Webpack? I see the > programming tools are available for Linux as 64-bit... > > When browsing the Webpack service packs, there is a 64-bit Linux service > pack. > Is this for the 64-bit programming tools, or is there a 64-bit Webpack > hiding > someplace? > > Thanks, > -Chris > > -- > | Christopher Cole, Cole Design and Development > cole@coledd.com | > | Embedded Electronics and Software Design > http://coledd.com |Article: 122614
I have also seen this problem with a design when I turned on timing driven Map. The Xilinx folks said to turn off the "register duplication" option in Map to avoid the problem. I've only tried this a little bit, so I can't guarantee that this is a useful fix. John Providenza On Aug 1, 10:01 am, "davide" <dav...@xilinx.com> wrote: > Martin, > > One thing that I noticed in your error message was that your ISE install was > in the 'Program Files' folder. This may or may not be related to the error, > but I would highly recommend that you install the tools in a directory with > no spaces. Try installing to the root as Xilinx_9.1 and see if the error > goes away. Repost if the error remains and we can go from there. > > -David > > <martin.leibetse...@ge.com> wrote in message > > news:1185962097.609559.126020@57g2000hsv.googlegroups.com... > > > hi, > > > i get this message when i run "map". > > > Using target part "5vlx30ff324-3". > > Mapping design into LUTs... > > Running directed packing... > > Constraining slice packing based on guide NCD. > > Running delay-based LUT packing... > > FATAL_ERROR:Portability:PortDynamicLib.c:358:1.27 - dll open of > > library > > <C:/Program Files/Xilinx_ISE_9_1i/xilinx/bin/nt/ > > libPlXil_DesCheck.dll> failed > > due to an unknown reason. Process will terminate. For more > > information on > > this error, please consult the Answers Database or open a WebCase > > with this > > project attached athttp://www.xilinx.com/support. > > > Process "Map" failed > > > Could somebody help me?Article: 122615
On Aug 1, 8:31 am, Christopher Cole <c...@scoob.coledd.com> wrote: > Does there exist a 64-bit Linux version of Xilinx Webpack? I see the > programming tools are available for Linux as 64-bit... > > When browsing the Webpack service packs, there is a 64-bit Linux service pack. > Is this for the 64-bit programming tools, or is there a 64-bit Webpack hiding > someplace? > > Thanks, > -Chris > > -- > | Christopher Cole, Cole Design and Development c...@coledd.com | > | Embedded Electronics and Software Design http://coledd.com| 64-bit makes sense mostly for the larger parts. Webpack does not support the larger parts. G.Article: 122616
On Jul 31, 10:19 am, Nir Dahan <write2...@googlemail.com> wrote: > Hi All, > > Please allow me to shamelessly plug my blog. It is relatively new (2-3 > months old) and just passed the 5000 views mark. > I am blogging about a lot of topics that might interest people here. > > visit me at:http://asicdigitaldesign.wordpress.com > > Thanks, > > Nir Hey Nir, I had a look and found it to be very very interesting! Good work! thanks, KunalArticle: 122617
hi all I am a newibe. i am tring to send bit stream data through ethernet. i am using altera DE2 board. i have my data in SDRAM and interfaced onto the etherenet pin by avalon switch fabric. The doubts what i am havin are i know the basics of TCP/IP. according to that ny data packet should contain UDP/IP address.. etc.. how to prepare my bit stream data in SDRAM so that it is made compactable for data transfer. i mean have to make the data packets that will travel through the ethernet. i am using UC/OS II rtos and NICHESTACK TCP/IP StackArticle: 122618
On Jul 31, 7:19 am, Nir Dahan <write2...@googlemail.com> wrote: > Hi All, > > Please allow me to shamelessly plug my blog. It is relatively new (2-3 > months old) and just passed the 5000 views mark. > I am blogging about a lot of topics that might interest people here. > > visit me at:http://asicdigitaldesign.wordpress.com Wow, a blog actually worth reading! I wish there was something like this covering FPGAs. Jan Gray used to run an interesting blog on http://www.fpgacpu.org but like most blogs, it eventually dried up. Thanks, TommyArticle: 122619
Jonathan Bromley wrote:
> I don't understand what's going on in your Xilinx models. I
> can't believe they put out code that doesn't work with
> zero delays.
They do. So did micron with their sdram models.
> You can be fairly sure it will work correctly
> when all the non-zero (post place-and-route) delays are
> backannotated into it.
>
> If you're desperate, introduce a tiny non-zero delay in all
> input signals except the clock, by copying them with a delay:
Or make a delayed clock for the pseudo-zero-delay models.
This is one reason I stick to synchronous functional simulation
and I leave the timing to STA.
-- Mike Treseler
Article: 122620Hi, Has anyone recently done a comparision of the utility of Primetime vs. Xilinx or Altera timing analysis engines? Anyone have an data to support if Primetime actually catches more static timing errors then the FPGA vendor tools. What are the pros / cons of using Primetime for FPGA timing analysis. Thanks, CraigArticle: 122621
On Aug 1, 8:29 pm, Tommy Thorn <tommy.th...@gmail.com> wrote: > On Jul 31, 7:19 am, Nir Dahan <write2...@googlemail.com> wrote: > > > Hi All, > > > Please allow me to shamelessly plug my blog. It is relatively new (2-3 > > months old) and just passed the 5000 views mark. > > I am blogging about a lot of topics that might interest people here. > > > visit me at:http://asicdigitaldesign.wordpress.com > > Wow, a blog actually worth reading! > > I wish there was something like this covering FPGAs. Jan Gray used to > run an interesting blog onhttp://www.fpgacpu.orgbut like most blogs, > it eventually dried up. > > Thanks, > Tommy Thanks everybody for the kind words. A lot of the stuff I blog about is also FPGA related. The only way to keep the blog alive is by people giving me specific feedback on what is interesting for them to read about. Unfortunately I have no inside connections in the industry and can not report when the next new FPGA will pop up on the market and what features it will have. What I can do, or try to do, is basically give some information based on my own limited experience in the field (10 years or so). >From the statistics page, I notice that the posts that get the most hits are the job interview questions and the puzzles. While I will keep on posting puzzles and job interview questions, I want to concentrate more on techniques that made me a better designer (so I believe). I hope this will be beneficial also for others. thanks again, NirArticle: 122622
<ctaniguchi1@gmail.com> wrote in message news:1185995501.496399.287000@q3g2000prf.googlegroups.com... > Hi, > > Has anyone recently done a comparision of the utility of Primetime vs. > Xilinx or Altera timing analysis engines? Anyone have an data to > support if Primetime actually catches more static timing errors then > the FPGA vendor tools. What are the pros / cons of using Primetime > for FPGA timing analysis. > > Thanks, > > Craig > I don't think primetime supports the FPGAs .. does it? MikeArticle: 122623
On Aug 1, 12:52 pm, "Mike Lewis" <some...@micrsoft.com> wrote: > <ctaniguc...@gmail.com> wrote in message > > news:1185995501.496399.287000@q3g2000prf.googlegroups.com... > > > Hi, > > > Has anyone recently done a comparision of the utility of Primetime vs. > > Xilinx or Altera timing analysis engines? Anyone have an data to > > support if Primetime actually catches more static timing errors then > > the FPGA vendor tools. What are the pros / cons of using Primetime > > for FPGA timing analysis. > > > Thanks, > > > Craig > > I don't think primetime supports the FPGAs .. does it? > > Mike Hi Mike, Both Altera and Xilinx tools have to option to output a netlist for primetime and some appnotes. Just not sure if it really will buy me anything to invest in the tool. I use primetime on the ASIC side but have not used it for FPGAs. Thanks, CraigArticle: 122624
On 1 Aug, 20:11, ctaniguc...@gmail.com wrote: > Hi, > > Has anyone recently done a comparision of the utility of Primetime vs. > Xilinx or Altera timing analysis engines? Anyone have an data to > support if Primetime actually catches more static timing errors then > the FPGA vendor tools. What are the pros / cons of using Primetime > for FPGA timing analysis. Con: Your bank account will be $30k down. Cheers, Jon
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