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Dear Paul When i say it executes some VHDL code , its does basic things like assert certain signal high or low. The most complicated thing it does is goes from one state to another to generate a multi bit counter. Thanks Regards Dharmesh JoshiArticle: 117251
Rob, Thanks for the information. I want to decode the data coming from a THine THC63LVD823. This chip sends dual link video data. Each link has its own clock. In my FPGA I instantiate two altLVDS cores. The clock of such a link is 70MHz. The deserialization factor is 7. This clock is edge-aligned with the data. I am testing my design with a video source that generates a known resolution. In my FPGA I can check the resolution that I receive from the altLVDS core by reading some registers. Sometimes this resolution is good, sometimes it isn't (it looks like I am not clocking the data at the correct moment). Maybe I should try to find a valid window by changing the clock alignment? best regards, KarelArticle: 117252
Colin Paul Gloster wrote: > " and since it implements a well-known ISA, commercial > devtools can target it. (Is that right?) > > [..]" > > Very expensive commercial tools do legally target Leon processors. Are you implying that gcc targeting SPARC is not legal? -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 117253
Figured it out on my own... EDK doesn't happily mix languages.. remade the top peripheral wrapper in VHDL instead of verilog and it worked right away... GREAT TOOLS!!!Article: 117254
JJ, Yes, that would be true. With only one power pin being shared, I would not expect the part to work well when a configuration is downloaded, but for JTAG, that is all that would be needed. AustinArticle: 117255
eromlignod wrote: > I'm programming a Xilinx Spartan-3 FPGA development kit. [snip] > > Well, as far as I can tell, they never gave me these drivers or > software (and I wouldn't know them if I found them anyway) and finding > any answers on their website has proven to be extremely difficult. > They have a forum, but it is not very active (only a post every day or > so). > > Has anyone here ever dealt with this kit? And, if so, do you know how > I can get hooked up? It would really help if you told us what kit you're talking about. Most of us don't have the time to search out the manufacturer based on the little bit of info you've given us. --- Joe Samson Pixel VelocityArticle: 117256
It's a Spartan-3/PCI-Express Starter Kit. DonArticle: 117257
Ken Soon wrote:
> I trying to port a design (video scaler) from Virtex 4 to Spartan 3E.
> Currently having trouble with not enough block rams.
>
> My reference (top) design uses only 15 Block Rams, but after wrapping a
> "wrapper" module around my top design. The block Rams shoots up to 60.
> Thus, I decided to go and look into this wrapper module. It instantiates
> alot of this dp_bram module. So, I went to look into this dp_bram module and
> found the following codes. ( I took out relevant portions of it for easier
> understanding)
>
> (Just for note: This wrapper module is the wrapper around the video scaler
> for trial synthesis. It includes two instances of the scaler, as well as a
> simple bus interface for the control register inputs.)
>
> --Information in Entity portion--
> data_width : integer := 8;
> mem_size : integer := 1920
> wr_addr : in std_logic_vector((LOG2_BASE(mem_size) - 1) downto 0);
> rd_addr : in std_logic_vector((LOG2_BASE(mem_size) - 1) downto 0);
> din : in std_logic_vector((data_width - 1) downto 0);
>
> Now I guess, this mem_array (mem_array(conv_integer('0' & wr_addr)) <= din;)
> is the main culprit using the block rams for data storage, right?
> Hmm, so how should I go about trying to solve this problem of having not
> enough block rams.
1920x8bits = 15.3kbits, this is less than one BRAM... I am guessing
"data_width" and "mem_size" are generics and the actual parameters on the
instance are larger than that or there are multiple instances of it. If
those are the actual parameters and there is only one instance, this code
fails to explain the 44 extra BRAMs. Even if it was x8bytes, this would
still be only 8 BRAMs instead of 45. It seems like your posting is lacking
some critical details that make it impossible for us to make educated
guesses. Also, having a wrapper around your 'top' design for a synthesis
implementation is suspicious.
The code you posted is a BRAM inference wrapper for a dual port RAM with
independently clocked read and write ports, the first real questions are:
how many times is this generic wrapper used, what are the instance
parameters in each case and what are they for?
Since a very decent scaler can be achieved with five lines worth of video
data that would require 15 BRAMs for inputs and three more for output
buffering, chances are that your scaler's wrapper needs a diet unless it
does other fancy things you may not be aware of.
> (gosh why cant I just have the mem_array just automatically use the
> dram....)
Because DRAMs have refresh cycles, row activation, row precharge and
numerous other quirks designers have to take care of before initiating any
actual data transfers... I told you so last week. Even if Xilinx had
hardware memory controllers, you would still have to work with the variable
latency and possible read re-ordering.
Article: 117258On 27 Mrz., 16:24, Austin Lesea <aus...@xilinx.com> wrote: > JJ, > > Yes, that would be true. > > With only one power pin being shared, I would not expect the part to > work well when a configuration is downloaded, but for JTAG, that is all > that would be needed. > > Austin With a multimeter I checked if the necesserly power supply pins and configuration pins are connected to their pads and they seem to be so. However, I might have accidently connected the pins to the pads by just pressing the pins with the multimeter probe or (worst case) the FPGA might be damaged. If the necesserly power supplies for configuration are not all connected, the POR( Power-On Reset) is activated. Is there way to test if the POR is activated or not from outside?Article: 117259
Wojciech Zabolotny wrote:
> Hi All,
>
> I'm looking for a tool, or a method to convert the ISE project into a
> makefile, which I could run remotely without X connection.
> The only thing I've foond is: http://www.xess.com/appnotes/makefile.html
> However I don't now if it works with ISE 9.1.
> Could anybody share some experiences?
You can use the makefile to compile your designs with ISE 9.1. You have
to do the following:
1) In xilinx_rules.mk, change the line
PROJNAV_DIR ?= __projnav
to
PROJNAV_DIR ?= .
2) Create a makefile in your ISE 9.1 project directory that contains
this line:
include xilinx_rules.mk
3) In your project directory, you can rebuild your bitstream with the
command:
make bit PART=xc3s1000-4-ft256
(You have to explicitly specify the part name because we can't get this
information anymore from the non-ASCII .ise project file.)
I tested this and it works for me. Maybe it will work for you.
Article: 117260"kha_vhdl" <abaidik@gmail.com> wrote in message news:1174986879.532908.172140@b75g2000hsg.googlegroups.com... > On 27 mar, 03:38, Eric Smith <e...@brouhaha.com> wrote: >> "kha_vhdl" <abai...@gmail.com> writes: >> > please i want some informations about reading videos using VHDL : how >> > to input videos then to treat it? >> >> It's rumored that the VHDL 2009 standard will include a standard package >> for video processing, so you're probably best off waiting for that. > > hi for all, > first of all , i m sorry for my stupid question , very sorry , but if > i m stupid please try to let me at the right way . > I try to programm a coder video it contains many modules and i want > to know how can i read my video at the first time . > for an information till now i dont have any information about my video > ( my teacher didnt tell me these details) and for me as a beginner i > want know the different ways to read it ; till now what i know two > ways of inputing manual and automatic one . > Really these are the informations that i know There is no one way. It entirely depends on what your teacher will be providing. If you assume that the simulation and the front end of the FPGA will "magically" produce data that you can conceptually think of as YUV space video (or YCrCb or RGB or one channel of monochrome) as 8-bit video components, your video processing - which is the only thing you can concentrate on until you know enough to build the FPGA front end and the simulation interface - will have an input data stream of these 8-bit elements with line-valid and frame-valid signals. That's it. Nobody here (unless your teacher is visiting comp.arch.fpga) can help you further on the front end. It's a black box. Treat it as such. And TALK to your teacher. ASK what the video format will be (YUV, RGB, etc) and how it will be provided (4:2:2 YUV, 4:1:1, 24-bit RGB). And good luck.Article: 117261
JJ, If the part is connected properly, you will see the proper signal on INIT_B. INIT_B will go high while the devices cleans out, and gets ready to try to configure, and then it will go low when cleanout is done before it starts to configure. If there is no configuration device present, then this sequence of INIT_B lets you know that the device is ready and waiting. Also, if a master mode is selected, the CCLK pin should be running. See page 56 of 280: http://direct.xilinx.com/bvdocs/userguides/ug332.pdf AustinArticle: 117262
"eromlignod" <eromlignod@aol.com> wrote in message news:1175002566.043660.255570@l77g2000hsb.googlegroups.com... > Hi guys: > > First of all, forgive me for being a dumb mechanical engineer...FPGA's > are new to me. > > I'm programming a Xilinx Spartan-3 FPGA development kit. I'm doing > pretty well so far. I've gotten my huge Verilog program written and > finally got it to simulate correctly and set up all the I/O pins, > etc. Now all I have to do is download it to the chip. > > My problem is that the board communicates via a PCI-Express slot. I > shut down my computer, plug the Xilinx board into my PCI-x slot, then > turn the computer back on. Unfortunately, the computer then insists > that I provide it with some sort of software or drivers to recognize > the new hardware (which it identifies as a "coprocessor"). > > Well, as far as I can tell, they never gave me these drivers or > software (and I wouldn't know them if I found them anyway) and finding > any answers on their website has proven to be extremely difficult. > They have a forum, but it is not very active (only a post every day or > so). > > Has anyone here ever dealt with this kit? And, if so, do you know how > I can get hooked up? I'm thinking it's probably something > ridiculously simple that I'm not grasping right now. Thanks for any > help. > > Don The development kit allows the designer to create a custom PCIe interface. Within the PC architecture, the system expects that the software that will interface to this board will provide the driver. Unfortunately, one cannot just develop a board and plug it into the PC, expecting built-in support for unknown functionalty. You can choose not to "install the hardware" on your PC and still have diagnostic access to the PCIe space. The Avnet-taught PCIe session (about 4 hours, hands-on) used a freeware PCIe snoop utility - I don't find my notes but may come across them later - to verify the configuration settings that were applied in the FPGA. If you do anything with the interface, software needs to be involved on the PC end. If you perform DMA, where do they go to or come from? If you perform register accesses, how are those registers physically mapped? It would be ideal if we could just hook hardware up to a PC and have something happen without involving software. We're not there. - John_HArticle: 117263
Andy
> I think Synopsys has problems with not knowing the type of the
> expression (A'range => ASel). Other vendors seem to be able to figure
> it out, but I've never tracked down whether it is legal per LRM.
Formally when you run into a situation where one tool accepts code
and another does not, you enter a bug (interpretation) request to
VHDL's Issues Screening and Analysis Committee (ISAC) via:
http://www.eda-stds.org/vasg/#Enhancements
In this case select: Report a BUG on an IEEE VHDL revision
Then ISAC will issue a response. The following is the ISAC
resolution to the above issue (recently ISAC Approved):
http://www.eda.org/isac/IRs-VHDL-2002/IR2097.txt
> Weng, would you rather have to type all that garbage out, or just
> write a function:
>
> ...
> temp := '0';
> for i in x'range loop
> temp := temp xor x(i);
> end loop;
> return temp;
Note that he is calculating several parity terms (such
as in SECDED logic) and each incorporates different, not necessarily
contiguous pieces of the array. I also note that in my final equation,
I had ment to give the function call a different name than XOR as you
would not want to use the operator name in this case:
y_xor(0) <= XOR_Reduce(( x(1), x(2), x(3), x(5), x(8), x(9), x(11), x(14),
x(17), x(18), x(19), x(21), x(24), x(25), x(27), x(30), x(32), x(36),
x(38), x(39), x(42), x(44), x(45), x(47), x(48), x(52), x(54), x(55),
x(58), x(60), x(61), x(63) ));
You can either code your own XOR_reduce or use the one from synopsys'
package, std_logic_misc (IIRC).
Cheers,
Jim
Article: 117264
On Mar 26, 11:25 pm, "news.la.sbcglobal.net" <dontre...@nowhere.net>
wrote:
> I see lots of CPU-projects onwww.opencores.org, some with obviously
> amateurish documentation/legal-disclaimers ("I copied company X's
> CPU, so I don't know you can legally use my core in your project, enjoy!")
I kind of agree with that.
> What about the 8-bit and 16-bit cores?
Depends what you're looking for (what do you want to do with your this
CPU?).
I have my own core (http://www.delajii.net/proc4) which is optimized
for control applications. It can be an 8b core, 16b, 24b, 32b, etc.
Without more info I can not say if it's suitable for you.
--
mmihai
Article: 117265Well, normally I would have used some type of microcontroller. The only reason I chose this version of FPGA is that I needed a large amount of I/O (over 250) and the Spartan-3/PCIe version had enough for my application. They also offer Spartan-3A and Virtex versions that include programming cables, but they didn't have enough I/O. The Digikey description said I was getting a programming cable with this model, but when I enquired as to why I didn't receive one, they said it was a misprint. I didn't realize that the PCIe interface was the only thing available for communication and downloading. So I guess the upshot is that there is no other way to download my program except through the PCIe and there is no existing software that allows me to do that. So apparently I must develop some sort of drivers myself. I'm OK with doing that, but I guess I need more information. Can you recommend a source? DonArticle: 117266
Karel, You should determine what your data valid window will be given the variance in the bit positions of the THline part, its out clock jitter, and the Cyclone2's setup and hold times. At 490MHz (speed of the serialized lane) your period is approx 2ns. This is a respectable speed for a CycloneII part. I would also check the output clock skew between the two links of the dual video, coming from the THline device. The skew could be large enough that your design might have to implement a FIFO to correctly align the data coming from your two alt_lvds cores. Rob On Mar 27, 10:01 am, "Dolphin" <Karel.Dep...@gemidis.be> wrote: > Rob, > > Thanks for the information. I want to decode the data coming from a > THine THC63LVD823. This chip sends dual link video data. Each link has > its own clock. In my FPGA I instantiate two altLVDS cores. The clock > of such a link is 70MHz. The deserialization factor is 7. This clock > is edge-aligned with the data. > > I am testing my design with a video source that generates a known > resolution. In my FPGA I can check the resolution that I receive from > the altLVDS core by reading some registers. Sometimes this resolution > is good, sometimes it isn't (it looks like I am not clocking the data > at the correct moment). > > Maybe I should try to find a valid window by changing the clock > alignment? > > best regards, > KarelArticle: 117267
I'm working on a new project using some code from opencores for my thesis research. I'd love to use a nice, high-quality tiny-fsm like picoblaze or the lattice semi micro8. However, I'm worried about licensing issues, as I'd also like to be able to use the opencores IP and release the whole thing under the GPL. Does anyone know / have a strong opinion on whether or not the Lattice Open IP license allows the code to be incorporated into GPL'd designs? I pretty sure the PicoBlaze does not allow this, and pacoblaze isn't so useful for those of us in vhdl-land. Thanks again, ..EricArticle: 117268
While you will still need a driver and api/control software to interface to your board via the PCIe port, what you may be looking for is a Xilinx programming cable to load your bit file into the FPGA. http://direct.xilinx.com/bvdocs/publications/ds300.pdf "eromlignod" <eromlignod@aol.com> wrote in message news:1175002566.043660.255570@l77g2000hsb.googlegroups.com... > Hi guys: > > First of all, forgive me for being a dumb mechanical engineer...FPGA's > are new to me. > > I'm programming a Xilinx Spartan-3 FPGA development kit. I'm doing > pretty well so far. I've gotten my huge Verilog program written and > finally got it to simulate correctly and set up all the I/O pins, > etc. Now all I have to do is download it to the chip. > > My problem is that the board communicates via a PCI-Express slot. I > shut down my computer, plug the Xilinx board into my PCI-x slot, then > turn the computer back on. Unfortunately, the computer then insists > that I provide it with some sort of software or drivers to recognize > the new hardware (which it identifies as a "coprocessor"). > > Well, as far as I can tell, they never gave me these drivers or > software (and I wouldn't know them if I found them anyway) and finding > any answers on their website has proven to be extremely difficult. > They have a forum, but it is not very active (only a post every day or > so). > > Has anyone here ever dealt with this kit? And, if so, do you know how > I can get hooked up? I'm thinking it's probably something > ridiculously simple that I'm not grasping right now. Thanks for any > help. > > Don >Article: 117269
On 27 mar, 17:34, "John_H" <newsgr...@johnhandwork.com> wrote: > "kha_vhdl" <abai...@gmail.com> wrote in message > > news:1174986879.532908.172140@b75g2000hsg.googlegroups.com... > > > > > On 27 mar, 03:38, Eric Smith <e...@brouhaha.com> wrote: > >> "kha_vhdl" <abai...@gmail.com> writes: > >> > please i want some informations about reading videos using VHDL : how > >> > to input videos then to treat it? > > >> It's rumored that the VHDL 2009 standard will include a standard package > >> for video processing, so you're probably best off waiting for that. > > > hi for all, > > first of all , i m sorry for my stupid question , very sorry , but if > > i m stupid please try to let me at the right way . > > I try to programm a coder video it contains many modules and i want > > to know how can i read my video at the first time . > > for an information till now i dont have any information about my video > > ( my teacher didnt tell me these details) and for me as a beginner i > > want know the different ways to read it ; till now what i know two > > ways of inputing manual and automatic one . > > Really these are the informations that i know > > There is no one way. It entirely depends on what your teacher will be > providing. > > If you assume that the simulation and the front end of the FPGA will > "magically" produce data that you can conceptually think of as YUV space > video (or YCrCb or RGB or one channel of monochrome) as 8-bit video > components, your video processing - which is the only thing you can > concentrate on until you know enough to build the FPGA front end and the > simulation interface - will have an input data stream of these 8-bit > elements with line-valid and frame-valid signals. > > That's it. > > Nobody here (unless your teacher is visiting comp.arch.fpga) can help you > further on the front end. It's a black box. Treat it as such. > > And TALK to your teacher. ASK what the video format will be (YUV, RGB, etc) > and how it will be provided (4:2:2 YUV, 4:1:1, 24-bit RGB). > > And good luck. Thank you for your anwser first of all : for my video it will be RGB and provided 24-bit RGB ( as i did program my modules ) , what i will do is to simulate my coder with a video thank youArticle: 117270
I've just started a new FPGA project, and am having trouble getting the parallel cable IV to work at speed. I'm using a Win XP computer that's new since the last project, and I removed the combination PCI parallel card from my old computer, to use in the new one. I can't get the Xilinx parallel cable to work in anything other than compatibility mode (where I either tell the software that it's a PCIII, or a PCIV running at 200 kHz. I never had any problem with the same PCI card in my old computer. Xilinx says to make sure the parallel port is configured in the BIOS as ECP, but the parallel port doesn't appear in the BIOS. The hardware properties page allows me to select use of interrupts in the "Filter Resource Method" pane, and to enable legacy plug and play detection. None of this seems to make a difference. Any suggestions? Thanks PeteArticle: 117271
"eromlignod" <eromlignod@aol.com> wrote in message news:1175012785.271000.67140@n76g2000hsh.googlegroups.com... > Well, normally I would have used some type of microcontroller. The > only reason I chose this version of FPGA is that I needed a large > amount of I/O (over 250) and the Spartan-3/PCIe version had enough for > my application. They also offer Spartan-3A and Virtex versions that > include programming cables, but they didn't have enough I/O. The > Digikey description said I was getting a programming cable with this > model, but when I enquired as to why I didn't receive one, they said > it was a misprint. I didn't realize that the PCIe interface was the > only thing available for communication and downloading. > > So I guess the upshot is that there is no other way to download my > program except through the PCIe and there is no existing software that > allows me to do that. So apparently I must develop some sort of > drivers myself. I'm OK with doing that, but I guess I need more > information. Can you recommend a source? > > Don I didn't realize you were using the board as a non-PCIe device, just a general FPGA development board with a large number of I/O. This board is designed to operate stand-alone as well. I am a little disappointed they didn't include the embedded USP programming interface found on other boards. I would also recommend the Platform Cable USB programming cable (as opposed to the Parallel-IV or a home-built Parallel-III compatible cable) because the power is supplied by the USB connection and the Vref - not used on the Parallel-III - gives a good range of acceptable voltages for any future development. Maybe you can push Digikey for a discount on the cable thanks to their poor description. If not, maybe going direct to the Xilinx online store would be a better route. - John_HArticle: 117272
Patrick wrote: > Hi there > > I have some general question for implementing a general RISC > architecture. > I have coded so far the fetch, decode, execute and writeback stage. > > 1) Next step is to implement forwarding. Do I have here a 2:1 > multiplexer in front of the alu that > takes as input the output of the alu of the former cycle and the > source register and the decode stage > then sets the multiplexer select signal ? > > 2) How is it working with a NOP instruction? Does there the alu > "execute" for example a R0 = R0 + R0. As R0 is always zero this doesnt > have any effect. Or is there somehow an additional signal from the > decode stage that tells the alu to do nothing? > > 3) Normally the writeback is done in the first half of the clock cycle > whereas the registers are read in the second half in the decode > register. Does this mean that the decode logic just works in the > second half of the clock cycle or does it do some stuff in the first > clock cycle and then just read out the operands in the second half of > the cycle? > > I know some easy questions but would be helpful for understanding to > know this ;) > > Cheers, > Patrick > Have a look at "Logic and Computer Design Fundamentals" by Mano and Kime, 2nd edition pages 542-562 BenArticle: 117273
Hi, I'm working on a Microblaze system in a Spartan 3-2000. I am trying to implement a watchdog timer using the opb_timebase_wdt IP core. I'm currently using ISE/EDK 8.2.02i, and the WDT version is 1.00a. The watchdog timer otherwise works fine. I can start/stop/reset the timer with no problem. The trouble is that when the watchdog timer DOES cause a reset, it won't release the reset line, which was effectively locking up the system. It did NOT respond like the datasheet. To solve the immediate problem, I have inserted an edge detector into the reset control logic, which allows the system to reboot, but I can't get the WDT_Reset signal to go low at all. The end result is that the WDT can only reset the system once. I did bring both signals out on test points, and I can see this behavior on a scope. The interrupt performs as expected, but once the WDT_Reset signal goes high, it stays high until I reconfigure the FPGA. Note, I am using a custom reset controller, because the ComBlock 1200 board I'm using requires special treatment due to the clock situation. (the clock isn't stable until after configuration, causing DCM problems). Any reset input will cause both a sys_reset and dcm_reset. dcm_reset is released as soon as the reset input goes away, but sys_reset is held until the clock is stable for at least 64 clocks or so. I haven't had any other problems with this reset controller. What am I missing here? Thanks!Article: 117274
On Mar 27, 11:34 am, "Colin Hankins" <Colin.Hank...@touit.com> wrote: > While you will still need a driver and api/control software to interface to > your board via the PCIe port, what you may be looking for is a Xilinx > programming cable to load your bit file into the FPGA. > > http://direct.xilinx.com/bvdocs/publications/ds300.pdf Aha! Brilliant! That's just what I'm looking for (I think) and well worth the $150 if it solves my problem. Thanks to everyone...I owe you a beer. Don
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