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On 3 Jun., 04:26, Ambreen Ashfaq Afridi <amboafr...@gmail.com> wrote: > recalculate the checksum. For that i have to first calculate the > cheksum. Now the problem is that im a bit confused as to which > algorithm should I use to calculate the cheksum. I started to work on > TCP/IP checksum algo but now im totally confused b/w TCP/IP checksum > and CRC. So can anyone tell me which algo shud i use? If CRC is confusing you, why not taking even parity over the whole word? bye ThomasArticle: 132601
"Peter Alfke" <peter@xilinx.com> wrote in message news:182802ac-178e-46b6-92c7- Sam, here is an even simpler solution that works if you accumulate for many clock ticks and can sacrifice two or three clock ticks before you get the result. You just divide the long accumulator into 2, 3, or 4 parts, with a single carry flip-flop between (you thus pipeline the carry signal) Then, at the end, you use 1, 2, or 3 clock ticks to flush the carry through the accumulator. It costs you no additional hardware at all, (Virtex-5 has the pipeline flip-flop built-in) and it runs as fast as a short accumulator. You pay with the latency at the end. There is no free lunch... Peter Alfke Thanks, Peter. The added latency is fine. I am already fine with 2 ticks as it is. But, I do not understand what you mean by, "flush the carry through the accumulator". Is there an HDL example you can refer to? Thanks in advance. - SamArticle: 132602
Hi, does anybody have any experience in using Virtex 5 FPGA with 1) MPMC 2) tr-mode ethernet MAC hard core with the xps_ll_temac and the ll_fifo? The card I am working on has an input of 100 MHz. this is the problem that I face, something which i am not sure: 1) MPMC has to run at a multiple of 133 MHz etc...thus the whole microblaze PLB system has to run at 133 MHz? 2) the xps_ll_temac requires some clocks like MGTCLK and GTX_CLK_0 at 125 MHz and 200 MHz respectively. Can these clocks required by the TEMAC be generated off the clock generator such that they are not running at same frequency as the system clock (ie the PLB bus clock SPB_Clk). does anyone have any idea? thanks! ChrisArticle: 132603
On Jun 2, 10:18=A0pm, "Sam Worth" <no-re...@some.org> wrote: > "Peter Alfke" <pe...@xilinx.com> wrote in message > > news:182802ac-178e-46b6-92c7- > Sam, here is an even simpler solution that works if you accumulate for > many clock ticks and can sacrifice two or three clock ticks before you > get the result. > You just divide the long accumulator into 2, 3, or 4 parts, with a > single carry flip-flop between (you thus pipeline the carry signal) > Then, at the end, you use 1, 2, or 3 clock ticks to flush the carry > through the accumulator. It costs you no additional hardware at all, > (Virtex-5 has the pipeline flip-flop built-in) and it runs as fast as > a short accumulator. You pay with the latency at the end. There is no > free lunch... > Peter Alfke > > Thanks, Peter. > The added latency is fine. I am already fine with 2 ticks as it is. But, I= > do not understand what you mean by, "flush the carry through the > accumulator". Is there an HDL example you can refer to? > > Thanks in advance. > - Sam horudeArticle: 132604
Kolja Sulimma wrote: > It should be noted that in FPGAs both delay and area are dominated by > the routing ressources. Therefore mainly the granularity of the > routing should be optimized. I think that FPGAs could achieve quite big advances in performance, if the FPGA tools would do better job in placing the components well to help up the routing. It still seems that the logic and especially the coarse grained units (for example memories) are placed randomly first, and then the tools try to fix the mess they did :) Good placements might enable changes the routing architectures also. > No design has millions of gates of random logic. Large designs are > dominated by arithmetic function blocks. Therefore it is likely that That depends on the design. For telecom chips random logic usually is the dominating factor, and arithmetic is not pushing the limits. DSP style designs and pure packet processing and switching designs are quite different beasts. > This is old knowledge for FPGA architecure folks, but there are two > strong arguments against it: > > 1.) > It is hard to quantify routing utilization, but the competitors > marketing will immediately target the lower LUT utilization as a > disadvantage. (But hey, if a LUT costs 75% less, who cares if I can > only use 80% of the LUTS? Especially if the clock frequency is > better?) I think the biggest problem in this is how to estimate what is the fill level you can achieve beforehand to select the FPGA for PCB design etc. In the past it was quite a problem when the designs were unroutable and you still had huge amounts of logic free. The routability was different in each design, and not very predictable and caused big problems. Maybe this problem might get some help from the the ASIC side RTL tools that look for routing congestion already at RTL level and the congested places can be recoded etc. But is this a good way to use coding time is a question. > 2) > Granularity 1 FPGAs make use of the huge knowledge about ASIC EDA > algorithms. For higher granularities you need to redevelopemost of the > software toolflow from scratch. Even todays granularity is too much for the tools, there are many blocks that have existed for years in the fabrics that the tools just can't infer. The tools are getting better, but the pace is quite slow. --KimArticle: 132605
Hi im looking for a vhdl to verilog converter. Im working with Trimode Ethernet MAC core which is written in VHDL. I have to modify this code but the problem is that I dont have any knowledge of VHDL. I do programming in Verilog.Plz send me any link for the converter. Thank you Regards, Ambreen AshfaqArticle: 132606
Thanks everyone. Now the issue is that how will i extract tcp and IP information from the ethernet frame? What libraries would i include while coding it in verilog?Article: 132607
"Peter Alfke" <alfke@sbcglobal.net> wrote in message news:2549ead4-b56f-4d6e-ab21- horude Hello, Peter. I am not familiar with that word. What does it mean?. - SamArticle: 132608
The time you will spend on the "translation" could also be used to make a design on your own=B4. Rgds AndreArticle: 132609
Mike Lewis schrieb:
> "backhus" <nix@nirgends.xyz> wrote in message
> news:g1o928$c8$1@news.hs-bremen.de...
>> Hi Vijayant,
>> every "rule of thumb" you are trying to use will give you a misleading
>> result. Even if you just want a maximum value.
>>
>> The only way to get a nearly accurate number is to synthesize your design
>> with an asic synthesis tool using the desired technology library.
>>
>> You may use a default synthesis at first, to get an idea of the size and
>> gate count. These results may vary depending on your design goals. If you
>> want to increase speed your design may become larger. If speed is
>> negotiable the design may become smaller with some area optimization
>> constraints.
>>
>> However, the result of this synthesis will be an area value (most likely
>> in square micro meters) because the used gates (and flipflops) heavily
>> vary in size and transistor count. Unless you are using a sea of gates
>> technology that has only nand2-elements.
>>
>> To give you an idea think about this:
>>
>> If you have a simple 4to1 mux, this may be synthesized with a single mux4
>> cell in some standard cell technologies. With a sea of gates technology
>> you need a bunch of nand2's for this function, plus some routing
>> resources.
>> So, how would you express the number of gates in these two cases?
>> The mux4 is just the solution with the minimum number of cells. depending
>> on your constraints the result might be any correct combination of simpler
>> gates.
>>
>> Also, the gate count, however calculated is not relevant for production.
>> Only the area tells you how many chips can be fabricated on a single
>> waver. And the area changes with the used technology of course.
>> So 1000 gates in a 130nm technology yield less chips per waver than 2000
>> gates in a 45nm technology. (rough estimation, just to give you an idea)
>>
>> So forget gate counts if you want to compare technologies.
>> Only use of gate counts is if you want to compare designs using the same
>> technology. And I mean the very same technology! (Just take a look at some
>> of the fruitless gate count discussions about Brand-A and Brand-X FPGAs)
>>
>
>
> Just wanted to argue on your last point .. gate count is the easiest means
> to compare technologies. It will stay relatively constant from tech to tech
> and you will have the nand2 area for the technology you are in so you can
> roughly compare the area of a design for different technologies using the
> gate count for the design.
>
> Mike
>
>
Hi Mike,
Muzaffer added a good point about drive strength, and another one is
that the area of different gate-cells (e.g. xor2) differ heavily from a
nand2. Even worse when looking at FFs-cells.
And, the libraries give you no multiplication factor based on the nand2
area, so you have to calculate all these for yourself for up to hundreds
of different cells. (easy???)
One more thing is that the use of more complex cells saves routing area.
how will you put that in your calculation?
And these are just points that show how misleading a gatecount-value
would be for comparing standard cell technologies. Comparing different
technologies like FPGA and standard cells would make even less sense.
The area calculated by the synthesis (or layout) tool gives you a value
you can work with.
And for FPGAs this would be the number of LUTs and FFs (plus some vendor
specific stuff if necessary).
And even these values for themselves can only be seen as one aspect of a
specific implementation. Because area can change heavily when you are
optimizing the very same design with different constraints.
The area may vary by a factor of two or three. (is 200% variation good,
even for a rough compare?)
In the end it's just another number. And like many others only useful if
you know more about the background of it.
And of course it depends on what you want to do with that number. (e.g.
Megapixels for digital cameras...nice to see them increase, but what
good is further increase when the pictures become worse due to noise?
The marketing guys love it anyway because the average custumer don't know.)
Best regards
Eilert
PS.: Just some funny story...
I'm preparing a lab course for FPGA synthesis and compared the
technology schematic views of XILINX ISE and Mentor Precision RTL.
ISE shows the equivalent logic inside a LUT as a bunch of 2 input gates
and inverters while Precision RTL uses big N input gates with bubbles.
It's all inside a LUT and uses the same resources, but confronted with
pictures of the same LUT drawn in these two styles needs some time to
tell that they show the same.
Article: 132610hello when i add a peripheral (plb EMAC in this case) from BSB to my embedded system (PPC405,ML300), do i have to explicitly write the drivers and, especially, an interrupt handler,and download them too? if yes, how do i add them? further, in the drivers and examples provided by xilinx, where can i find out what the argument values are? (for example, an argument instance pointer[InstancePtr] appears in most functions. for EMAC, say, how do i find out what its value is? same thing with device id etc) Or does xilinx EDK link the drivers too when the peripheral is added? please help me out asap... thanks vikram ps: i am new to this so please keep it simple....Article: 132611
On Jun 3, 6:18 am, vikram <vikram...@gmail.com> wrote: > hello > > when i add a peripheral (plb EMAC in this case) from BSB to my > embedded system (PPC405,ML300), do i have to explicitly write the > drivers and, especially, an interrupt handler,and download them too? > if yes, how do i add them? > > further, in the drivers and examples provided by xilinx, where can i > find out what the argument values are? (for example, an argument > instance pointer[InstancePtr] appears in most functions. for EMAC, > say, how do i find out what its value is? same thing with device id > etc) > > Or does xilinx EDK link the drivers too when the peripheral is added? > > please help me out asap... > > thanks > > vikram > > ps: i am new to this so please keep it simple.... Well..... EDK comes with OS-independent drivers for most of its peripherals. So from that standpoint, no you don't have to write the low-level driver. Now, you do have to write the "glue" logic to interface to this low-level driver. For each driver provided by EDK, there is an example of it being used. I'm not sure where they're at, but they do exist. The drivers are enabled when you select them in the Software configuration portion of your EDK project. After you have enabled them, you build them by running libgen. This is performed from the command line by "make libs" or from the gui : Build software libraries. After the libraries have been built, you can view all the source code to them since they'll be in: <EDK project root>/<name of the embedded processor: i.e. ppc405_0>/ libsrc/<driver name>. HTH, MikeArticle: 132612
Hi to everyone. I have some stupid problem that took lot of my time and if someone could help me please do so .I would be veryy greatfull I was implementing counter for my fpga (vhdl) and my code was thi library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity counter is generic ( width: positive:=8); port ( CE: in std_logic; C: in std_logic; CLR: in std_logic; RST: in std_logic; Q: out std_logic_vector(width-1 downto 0); CEO: out std_logic; TC: out std_logic); end counter; architecture Behavioral of counter is constant TERMINAL_COUNT: std_logic_vector (width-1 downto 0) := (others=>'1'); signal Q_internal: std_logic_vector (width-1 downto 0); signal TC_internal: std_logic; begin process (CLR, C, CE, RST) begin if CLR = '1' then Q_internal <= (others => '0'); elsif C'event and C='1' then if RST <='1' then Q_internal <= (others => '0'); elsif CE = '1' then Q_internal <= Q_internal+'1'; end if; end if; end process; process (Q_internal) begin if Q_internal = TERMINAL_COUNT then TC_internal <= '1'; else TC_internal <= '0'; end if; end process; CEO <= TC_internal and CE; TC <= TC_internal; Q <= Q_internal; end Behavioral; but when I try to sintetize the code ISE gives me these warings WARNING:Xst:647 - Input <CLR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input <CE> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input <RST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input <C> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. I can't realiye how these ports are not used when it is clear that I am using them. Also after route and map I see that counter isn't implemented. I can't understand waht is happening. I know that is probably some stupid mistake but I can't see it. If anyone see what is wrong here please help me. Thank you very much ZoranArticle: 132613
On Tue, 3 Jun 2008 07:09:27 -0700 (PDT), Zorjak wrote: >I can't realiye how these ports are not used when it is clear that I >am using them. Also after route and map I see that counter isn't >implemented. Check what you've done with the counter's OUTPUTS. If they don't find their way to a device output pin, then the whole counter will ultimately be optimised away, leaving its input signals unused. Oh - and while you're checking, remove CE and RST from the sensitivity list of your clocked logic. They're synchronous controls, and shouldn't trigger the clocked process. In VHDL it does no harm except to confuse the reader and waste simulation time, but if you did the same thing in Verilog you would get crazy behaviour in simulation. Also, when you have some leisure time, trawl the recent archives of comp.lang.vhdl for discussions on NUMERIC_STD, to understand why many of us don't much like your code :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 132614
Which Tri mode ethernet MAC you are using now? from Xiliux? On Jun 3, 1:40 am, Ambreen Ashfaq Afridi <amboafr...@gmail.com> wrote: > Hi im looking for a vhdl to verilog converter. Im working with Trimode > Ethernet MAC core which is written in VHDL. I have to modify this code > but the problem is that I dont have any knowledge of VHDL. I do > programming in Verilog.Plz send me any link for the converter. > Thank you > Regards, > Ambreen AshfaqArticle: 132615
On Jun 3, 1:30 am, chrisde...@gmail.com wrote: > Hi, > does anybody have any experience in using Virtex 5 FPGA with > > 1) MPMC > 2) tr-mode ethernet MAC hard core with the xps_ll_temac and the > ll_fifo? > > The card I am working on has an input of 100 MHz. this is the problem > that I face, something which i am not sure: > > 1) MPMC has to run at a multiple of 133 MHz etc...thus the whole > microblaze PLB system has to run at 133 MHz? > 2) the xps_ll_temac requires some clocks like MGTCLK and GTX_CLK_0 at > 125 MHz and 200 MHz respectively. Can these clocks required by the > TEMAC be generated off the clock generator such that they are not > running at same frequency as the system clock (ie the PLB bus clock > SPB_Clk). When you generate the core, please select clock generate. so you only need to give only one clock into the TEMAC then it will use DCM to generate what it need > does anyone have any idea? > > thanks! > ChrisArticle: 132616
For those that are just getting started with using Xilinx FPGAs, we have released a new version of our ISE/WebPACK tutorial that is updated for version 10.1i: http://www.xess.com/appnotes/ise-10.pdf . -- <html> <body> <tt>-----------------------------------------------------------------<br> <font face="Verdana">Dave Van den Bout<br> XESS Corp.<br> 2608 Sweetgum Dr.<br> Apex NC 27539-8851<br> Phn: (919) 363-4695<br> Fax: (206) 339-5912<br> devb@xess.com<br> <a href="http://www.xess.com/" eudora="autourl">http://www.xess.com<br> </a></font></body> </html>Article: 132617
On Jun 3, 6:54=A0pm, morphiend <morphi...@gmail.com> wrote: > On Jun 3, 6:18 am, vikram <vikram...@gmail.com> wrote: > > > > > > > hello > > > when i add a peripheral (plb EMAC in this case) from BSB to my > > embedded system (PPC405,ML300), do i have to explicitly write the > > drivers and, especially, an interrupt handler,and download them too? > > if yes, how do i add them? > > > further, in the drivers and examples provided by xilinx, where can i > > find out what the argument values are? (for example, an argument > > instance pointer[InstancePtr] appears in most functions. for EMAC, > > say, how do i find out what its value is? same thing with device id > > etc) > > > Or does xilinx EDK link the drivers too when the peripheral is added? > > > please help me out asap... > > > thanks > > > vikram > > > =A0 ps: i am new to this so please keep it simple.... > > Well..... EDK comes with OS-independent drivers for most of its > peripherals. So from that standpoint, no you don't have to write the > low-level driver. Now, you do have to write the "glue" logic to > interface to this low-level driver. For each driver provided by EDK, > there is an example of it being used. I'm not sure where they're at, > but they do exist. > > The drivers are enabled when you select them in the Software > configuration portion of your EDK project. After you have enabled > them, you build them by running libgen. This is performed from the > command line by "make libs" or from the gui : Build software > libraries. > > After the libraries have been built, you can view all the source code > to them since they'll be in: > > <EDK project root>/<name of the embedded processor: i.e. ppc405_0>/ > libsrc/<driver name>. > > HTH, > > Mike- Hide quoted text - > > - Show quoted text - thanks for the prompt reply... will check it out. regards vikramArticle: 132618
On Jun 2, 11:16=A0pm, "Sam Worth" <no-re...@some.org> wrote: > "Peter Alfke" <al...@sbcglobal.net> wrote in message > > news:2549ead4-b56f-4d6e-ab21- > horude > > Hello, Peter. > I am not familiar with that word. What does it mean?. > - Sam Sorry, that was a silly security code that I was asked to enter . Then I gave up... You do not need any HDL code, you need a basic understanding. The problem with a long accumulator is the carry ripple delay. That's why I cut up the accumulator into smaller chunks. Into the cut I insert a pipeline flip-flop that delays the rippling carry by one clock tick. Whenever there is a 1 in any of these pipeline registers, it represents an "undigested" carry, which means that the accumulator output is incorrect. Obviously, I must get rid of these stored carry bits before I look at the accumulator output. So I run a few cycles of dummy accumulation, with the data inputs at zero or disabled. Each clock tick will move the stored carry into the accumulator. Worst- case I need one clock tick for every carry-pipeline flip-flop. If you divide the accumulator in two halves, you need only one extra clock tick, and you need it only for read-out, not for the normal accumulator operation. Think about it. It's really quite simple. Peter Alfke, Xilinx ApplicationsArticle: 132619
> Keep in mind the 20 pin header may be rearranged from what your cpld/ > fpga board expects; there is no header standard used throughout the > industry. Also please make sure your JTAG voltages are compatible. > Does your jtag programmer include your xilinx devices as a target? I > end up just using the Xilinx USB Platform Cable to program my chips > directly from the Xilinx utilities when I'm doing iterative design. A > different JTAG programmer will probably need a generic, compatible > file format. I had to remove the idc plug to make direct connection to vdd/vss/tdo/tdi/tck/tms but still webpack impact will not recognise the cable. It seems to me some jtag programmers are not compatible with xilinx. I have the jtag schematic from xilinx Title: jtag/parallel download cable comments: 0380507 10 july 1996 ver 2 According to this schematic D6/Busy/Pe (pins 8/11/12) should be connected together, yet by looking at this jtag of mine I don't see this at all. I tried to build an unbuffered programmer for a schematic I found on wikipedia; this had better results, but still not working as I think it should; it can erase the chip, test for erased chip, program, but the check sum always comes back wrong, and the led doesn't come on either. more below > > The Verilog module you included is one step in your journey. You may > find a high on the input turns off the LED by driving the cathode > high, depending on your board (active low logic). You still need to > compile the code, assign pins, place & route the design, and generate > a programming file. Yes, done all that, and yes - I did insert the led the right way round. > > You have all that down? It should be covered pretty well in the > documantation available to you. Yes, all the documentation is good and it is fun, but it will be more fun if my jtag will start working, at least returning correct checksums?Article: 132620
<ghuardian@gmail.com> wrote in message news:81f41ef2-8141-4126-8cb5-8e663854d1f9@e53g2000hsa.googlegroups.com... >Hi, I`m trying to make a temporal simulation ( Post place & route >model ) of a FPGA designed in Xilinx 9.2i in Modelsim 6.0, but the >Modelsim gives me an error of type Error - (vsim 3193), refered from a >library called swifpli_mti.dll wich Modelsim doesn´t find. I suspect that Modelsim 6.0 (released in 2004) PLI is incompatible with ISE9.2i (released in 2007?), is there any reason why you have to use 6.0? The manual described how to setup the swift interface, search the manual for Smartmodel. Hans www.ht-lab.comArticle: 132621
discussions@fpga.usenet wrote: > I had to remove the idc plug to make direct connection to > vdd/vss/tdo/tdi/tck/tms but still webpack impact will not > recognise the cable. It seems to me some jtag programmers > are not compatible with xilinx. > The Xilinx tools (iMPACT, ChipScope) only work with cables that they have been designed for, they will not work with any random JTAG cable. Ed McGettigan -- Xilinx Inc.Article: 132622
discussi...@fpga.usenet wrote: <snip> > > I had to remove the idc plug to make direct connection to > vdd/vss/tdo/tdi/tck/tms but still webpack impact will not > recognise the cable. It seems to me some jtag programmers > are not compatible with xilinx. <snip> Virtually all jtag programmers are not compatible with the Impact tool. Your jtag programmer SOFTWARE may be compatible with Xilinx programming files, however. Or just spend $150 on a very good Xilinx USB Plaform Programmer cable. - John_HArticle: 132623
On Apr 28, 6:55=A0am, "ALu...@web.de" <ALu...@web.de> wrote: > What kind of design are you running at 620MHz ? > > Rgds > Andre Hi Andre, It was an SERDES with 8B10B decoder/encoder targetting OC-12. regards, HuaArticle: 132624
On Apr 28, 11:55=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > Huawrote: > > Hi there, > > > I am trying to get a design passing the timing to run at 622.08MHz > > clock on aCycloneIII device. > > > All the critical paths has been pipelined so there is only one level > > of combinational logic inbetween registers and the fitter and > > synthesizer's setting has been tuned up for performance oriented > > according to the QII handbook. But still, some paths failed because of > > the propagation delay on the interconnections between LABs. I know I > > can set minimum delay constraints on these pathes to force the fitter > > place those LEs close together, but I am afraid some other paths will > > be placed apart on the chip and fail the timing. And I will have to > > put constraints on them and repeat this cycle over and over. > > > Now I am trying different fitter seeds to see if there is a lucky > > initial placement plan will work magically. But, are there any smart > > way to do this? > > > And, is there anyway to set the fitter to give higher priority in > > place and route to high frequency clock domains? > > > BTW, the design has already passed the timing for the fast timing > > model, but not for the other two slow timing model. Does that mean the > > design may work in some compilation, but may not work in some worse > > cases? > > > Thanks in advance and any advice will be highly appreciated. > > Altera parts aren't my area of expertise, but I was curious about this > question so I poked into theCycloneIII datasheet. =A0You should have a > look at Clock Tree Specifications, Table 1-18 in the datasheet, as the > part is not capable of running this fast. =A0The maximum clock frequency > is 500 MHz. > > Ed McGettigan > -- > Xilinx Inc.- Hide quoted text - > > - Show quoted text - Yes Ed, we found out too. In fact, the bottleneck was the clock toggle rate for I/O pins. For LVDS the highest toggle rate was only 300+ MHz for this part. Hua
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