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this is part of the prm file PROMGEN: Xilinx Prom Generator J.30 Calculating PROM checksum with fill value ff Format Mcs86 (32-bit) Size 512K PROM start 0000:0000 PROM end 0007:ffff PROM checksum 06e37c23 in Mcs file To calculate the checksum, add all bytes in Record Length, Address, Record Type, and Data fields. The checksum will be the 2's compliment of the sum. but the checksum in prm file is not as same as in mcs file. how can i get the prom checksum. From dave@comteck.com Sun Apr 01 21:24:38 2007 Path: newssvr21.news.prodigy.net!newsdbm03.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!nx02.iad01.newshosting.com!newshosting.com!208.49.83.146.MISMATCH!uns-out.usenetserver.com!news.usenetserver.com!pc03.usenetserver.com!COMTECK.COM-a2kHrUvQQWlmc!not-for-mail From: Dave <dave@comteck.com> Subject: Re: Webpack 9.1 Service Pack 3 Date: Mon, 02 Apr 2007 00:24:38 -0400 User-Agent: Pan/0.14.2 (This is not a psychotic episode. It's a cleansing moment of clarity.) Message-Id: <pan.2007.04.02.04.24.38.4354@comteck.com> Newsgroups: comp.arch.fpga References: <eugumh$k7b$1@lnx107.hrz.tu-darmstadt.de> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Complaints-To: abuse@usenetserver.com Organization: UseNetServer.com Lines: 10 X-Trace: e3bf646108588e51d970906099 Xref: prodigy.net comp.arch.fpga:129075 On Thu, 29 Mar 2007 17:57:37 +0000, Uwe Bonnes wrote: > did my update go wrong or does also a succeeded update of Xilinx Webpack > with 9_1_03i_lin.zip still display "Release Version: 9.1.01i"? Interesting. I updated Saturday night and mine displays "Release Version: 9.1.03i" and "Application Version: J.33" in the About window. ~Dave~Article: 117476
Islam Ossama wrote:
> Matthew,
>
> Parallelism was also a factor in choosing PCA for implementation on
> FPGA, and Composite-PCA can even increase that parallelism.
>
> I think it's a very good point what you said about speed concerning a
> C implementation, which means we'll probably take your suggestion and
> do it entirely in VHDL. The part of the team working on the algorithm
> is already breaking it down into parallel parts; hopefully this would
> make the algorithm really "shine", as we definitely need it to. Also,
> for the sake of comparison, I'm thinking we can implement the same
> algorithm on a standard PC with threading and run it in real-time
> priority, and compare the results to see what was gained through the
> FPGA implementation. I'm sure the results would be interesting either
> way.
You could opt for an hybrid solution... do all the massively parallelizable
things with FPGA fabric (after all, this is what FPGAs are all about when
applied to high-speed processing) and do the more
sequential/supervisory/etc. stuff on a CPU, preferably one of the PPC405
cores present in V2P and 4VFX FPGAs - these real on-chip CPU cores will
provide far better performance than any soft-CPU you can possibly come up
with, the only caveat is that you will only have two such CPUs available at
most.
From dave@comteck.com Sun Apr 01 22:31:01 2007
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From: Dave <dave@comteck.com>
Subject: Dear Xilinx
Date: Mon, 02 Apr 2007 01:31:01 -0400
User-Agent: Pan/0.14.2 (This is not a psychotic episode. It's a cleansing moment of clarity.)
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Dear Xilinx,
I updated my WebPack Saturday night. Thank you for making these
available. I have been unable to get my Spartan 3E Starter Board to work
with the DDR SDRAM since I got it four months ago. Full of optimism, I
started the new MIG, clicked the "Generate-3E Starter Kit" button, and
then downloaded the .bit file to my board. And once again, it didn't do
anything.
As I was going thru the Readme, I realized that maybe it isn't my fault or
a problem with the board. The file specifies a MT46V32M16xx-5B DDR SDRAM.
I don't know where you are getting your info from, but inspecting my Rev D
board and its schematic reveal my SDRAM is an MT46V32M16TG-6T. I realize
it's just a speed grade difference, but you know the old saying: "A
nanosec here and a nanosec there and pretty soon you have real time." The
Readme says "the design has been hardware verified for the following
configuration" and goes on to list the SDRAM the board does not have.
Would it be too much trouble for you to get a board with the configuration
you are shipping and try this file on it? I might even loan (maybe even
give) you my board, if it would lead to some resolution of this DDR issue.
Since I had the MIG open, I thought I would try modifying the parameters
of one of the SDRAMs (since you don't have mine listed in the Components
Window) and see if the "Generate " button would use it. It doesn't.
However, I had the distinctly unpleasant experience of dealing with a user
interface which doesn't allow you to save over an existing part. You have
to make your change(s), save under a different name, click down through
several levels to get to the old version of the part, delete it, click
down through the same levels to get to the new version you saved under a
temp name, save it under the original name, then click down through
several levels again to get to the temp name and delete it. How about a
popup that says "File exists. Do you want to overwrite it? Yes No"?
Sincerely,
~Dave~
P.S.: Yes I tried to submit this SDRAM issue as a WebCase. However, I
am waiting to "receive security clearance on our server". So I
thought I'd vent gently here while waiting.
Article: 117477I installed ISE 9.1i WebPack and service pack 3 without problems. See my blog : <http://svenand.blogdrive.com/archive/41.html> SvenArticle: 117478
Is EDK9.1i a free upgrade if you have EDK8.1 installed and does anyone know where it can be found. SvenArticle: 117479
Hello, Thanks for the information. After struggling with the core I have developed my own core (I allready had an LVDS deser for Xilinx, I rewrote it for Altera). I used the "Input Delay from Pin to Input Register" constraint to set all input delay chains to "0". After adding this constraint all LVDS pins have nearly similar tSU and tH. The best news is that the design works nice. Thanks for your help, KarelArticle: 117480
I had a problem that was quite similar. Check if you have turned off SELinux. Use "setenforce 0" for temporary disable. regards GüntherArticle: 117481
Interesting that... http://download.micron.com/pdf/datasheets/dram/ddr/512MBDDRx4x8x16.pdf If you read the differences between these memories, you see that the -5B is DDR400... whereas the -6 is DDR333... Do you know whether the clock rate is 200M or 133-167M for the starter kit? Actually, which starter kit are you using? I have a pile of kits, want to make sure I can't have the same problem... Ben "Dave" <dave@comteck.com> wrote in message news:pan.2007.04.02.05.30.50.602424@comteck.com... > Dear Xilinx, > > I updated my WebPack Saturday night. Thank you for making these > available. I have been unable to get my Spartan 3E Starter Board to work > with the DDR SDRAM since I got it four months ago. Full of optimism, I > started the new MIG, clicked the "Generate-3E Starter Kit" button, and > then downloaded the .bit file to my board. And once again, it didn't do > anything. > > As I was going thru the Readme, I realized that maybe it isn't my fault or > a problem with the board. The file specifies a MT46V32M16xx-5B DDR SDRAM. > I don't know where you are getting your info from, but inspecting my Rev D > board and its schematic reveal my SDRAM is an MT46V32M16TG-6T. I realize > it's just a speed grade difference, but you know the old saying: "A > nanosec here and a nanosec there and pretty soon you have real time." The > Readme says "the design has been hardware verified for the following > configuration" and goes on to list the SDRAM the board does not have. > Would it be too much trouble for you to get a board with the configuration > you are shipping and try this file on it? I might even loan (maybe even > give) you my board, if it would lead to some resolution of this DDR issue. > > Since I had the MIG open, I thought I would try modifying the parameters > of one of the SDRAMs (since you don't have mine listed in the Components > Window) and see if the "Generate " button would use it. It doesn't. > However, I had the distinctly unpleasant experience of dealing with a user > interface which doesn't allow you to save over an existing part. You have > to make your change(s), save under a different name, click down through > several levels to get to the old version of the part, delete it, click > down through the same levels to get to the new version you saved under a > temp name, save it under the original name, then click down through > several levels again to get to the temp name and delete it. How about a > popup that says "File exists. Do you want to overwrite it? Yes No"? > > > Sincerely, > > ~Dave~ > > P.S.: Yes I tried to submit this SDRAM issue as a WebCase. However, I > am waiting to "receive security clearance on our server". So I > thought I'd vent gently here while waiting.Article: 117482
Hi, thanks now it's working... Regards ManuelArticle: 117483
Great News!! "Dolphin" <Karel.Deprez@gemidis.be> wrote in message news:1175496898.375032.121520@b75g2000hsg.googlegroups.com... > Hello, > > Thanks for the information. After struggling with the core I have > developed my own core (I allready had an LVDS deser for Xilinx, I > rewrote it for Altera). I used the "Input Delay from Pin to Input > Register" constraint to set all input delay chains to "0". After > adding this constraint all LVDS pins have nearly similar tSU and tH. > The best news is that the design works nice. > > Thanks for your help, > Karel >Article: 117484
Dear all, We are searching a company having a large Xilinx VIRTEX and/or a large Altera STRATIX for testing our SVF player via Amontec JTAGkey (USB to JTAG interface). We already tested ERASE-PROG-CHECK of Xilinx Coolrunner / Spartan2 / Spartan3 / Platform Flash, and some other Altera Lattice devices, but we want to have a feedback on the download speed of a large Xilinx VIRTEX via JTAG. If your company has a large on-board VIRTEX or STRATIX and can do some SVF file tests for us, we will send one FREE Amontec JTAGkey sample and one Flying Lead connector sample. Please write to laurent.gauch-AT-amontec.com Thank you in advance for your help, Laurent http://www.amontec.comArticle: 117485
On Apr 2, 1:27 am, Austin <aus...@xilinx.com> wrote: > Mehdi, > > The DCM Macro is to prevent the unlikely possibility of NBTI shift in > the delay lines. > > If the macro is used, or is the DCM is used with a clock that is > present, then the DCM will never experience NBTI shift. > > NBTI shift requires: circuit is static (does not toggle), and power is > applied, and a long time. NBTI can be accelerated by very high > temperature and high voltage. Since the delay line supplies are > regulated, there is no way for a customer to apply a higher voltage to > the delay lines. > > It was thought that in some cases, a pcb is inserted, and not > provisioned (such as a card in a large network). The card might remain, > powered up, at a fairly high ambient temperature for a few weeks before > it is needed. > > The NBTI shift will cause the delay line to have duty cycle distortion, > which means that the maximum frequency will drop from ~700 MHz (where it > normally breaks) to ~500 MHz. > > In order to stay inside the +/-5% duty cycle specification for > distortion, we placed the "autocal" macro in the software to > automatically get placed. > > If you use, or don't use, the DCM's, and never plan to change, or use > them all below 250 MHz, then it is pretty much a don't care. > > If you don't use a DCM, and need to use that DCM later, and it needs to > work >250 MHz, then the autocal block is a good idea (guarantees > operation to specification). > > If you use the DCM for awhile, then the shifts are equalized, and > subsequent loss of clock doesn't do anything at all (eg a 168 hour > active burn in would prevent any further issues). > > NBTI can be baked out by powering the device off, and annealing it at > 125 C for ~72 hours. Or, you can just exercise the DCM, and the NBTI > shifts will equalize, and it will (eventually) work. > > As annoying as the NBTI was, it was a terribly obscure and minor issue, > one that has never occurred in any report from the field, and one that > we only saw in our qualification tests where we intentionally run things > at temperatures and voltages outside of the absolute maximum specifications. > > For V5, NBTI was accounted for, so you do not need to worry. > > Austin Another question on the subject. Is it interesting to try changing the macro to control all the unused DCMs? Another question: I extensively use the DRP port to change the frequency during the development phase of my projects. As I see it's impossible on Stepping Level 1? MehdiArticle: 117486
"Daniel S." <digitalmastrmind_no_spam@hotmail.com> writes: > Martin Thompson wrote: >> "Daniel S." <digitalmastrmind_no_spam@hotmail.com> writes: >> >>> "Hey Martin, there's a new feature we added to the specs... you will >>> have six more control bits and two extra pipeline stages to >>> manage. Unfortunately for you, the extra stages and controls sit smack >>> in the middle of the two spots that gave you so many headaches over >>> the last week or two." >> >> That's be the difference then - most of my current FPGA is explicitly not >> data-path, so there are very few changes to the data-path that are >> likely to cause me headaches :-) I hope... >> >>> Of course, waiting until the data path is completed only reduces the >>> likelihood of late changes ruining control efforts, it does not >>> immunize against late changes... and it still requires a "disposable" >>> (minimum effort) controller for preliminary data path testing. >> >> Indeed. How about we disallow late changes :-) That's go down well! > <snip good story> > I am certain these > folks would be really happy if Xilinx decided to include a SINGLE (and > no more than one) PPC405 core in all LX/SX FPGAs... an XC5VSX95T with > an on-chip PPC405 would be a dream platform for them: excellent > logic-to-DSP48 ratio for their application, a couple of MGTs and one > PPC405 in one package to reduce external parts count. > Yes, I found it weird that one PPC wasn't in *all* the families. > You get to see lots of interesting things when riding with people who > are at the edge of their respective domains. Indeed! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 117487
"Daniel S." <digitalmastrmind_no_spam@hotmail.com> wrote in message news:B4QPh.39$py.32477@wagner.videotron.net... > news reader wrote: >> My altera FPGA is connected to a SDRAM on the prototype board. >> Assume the clock frequency is 100MHz, how much margin should I >> give to the SDRAM? 3ns? 5ns? > > Huh? > > Read your DRAM's specs and arrange your FPGA's timings to meet your > particular DRAM's setup and hold times just like you should already be > doing for any other external IC... or any clocked component for that > matter. assume the SDRAM is 133MHz type, and my FPGA system design clock is 90MHz. During simulation I use 10ns clock, and timing satisfied. Will it guarantee that the system will work after setup/hold time is satisfied? For a large board with 133MHz SDRAM and FPGA, what are the approx. range of interconnect delays between FPGA pins and SDRAM pins?Article: 117488
On Mar 31, 12:54 pm, Markus Knauss <markus.kna...@gmx.net> wrote: > Hi all, > > at the moment, we are using AT17LV010 configuration devices for a > spartan 2S100. > I have to look for a different solution which is not so expensive. > > The Xilinx XC17V01 is OTP and more expensive than the AT17LV010. > > Does someone know a different prom (OTP, EEPROM, Flash)? > I don't want to use a pld or microcontroller for active serial programming. > > Thanks a lot > > Markus Do you need it to be pin compatible or are you re-designing your board? For new designs I would suggest the PlatformFlash series (xcf01s), but these won't come in the same 8-pin packages as the XC17LV01. In addition to being much cheaper, they are JTAG in-system programmable (but beware of issues of you use them ahead of your Spartan 2 in a JTAG chain). HTH, GaborArticle: 117489
Mehdi, The autocal block should be automatically inserted for all DCM's, used or unused by the software... At least, that is what I had heard. As for the DRP port, if it is listed in the errata for that stepping, then that is what that device (does not) delivers. Which device? What steppings? AustinArticle: 117490
Hi all, I'm trying to generate 32 16bits registers using verilog generate : reg [15:0] Data_reg [N_REG-1:0]; reg [N_REG-1:0] DataSelFlag; reg Data_reg_RST; reg Data_reg_LATCH ; genvar i; generate for(i=0;i<N_REG;i=i+1) begin : WordLine always@(posedge i_CORE_CLOCK) if(Data_reg_RST) begin Data_reg[i]=16'b1; DataSelFlag[i]=1'b0; end else if((Data_reg_LATCH)&&(i==i_EEAddressHVP2[5:1])) begin Data_reg[i]=io_MemoryOut&Data_reg[i]; DataSelFlag[i]=1'b1; end end endgenerate I want to reset the 32 registers to 0xFFFF on the same i_CORE_CLOCK period, so I think using this parallel structure allow that. But when I simulate that, there is only the LSB of each register which is set to '1', all others bits stay equal to '0'. I'm begining with verilog ( I'm more used with VHDL ), so, maybee I do something bad.. Could you help me please ? Best regardsArticle: 117491
On 2 avr, 16:54, michel.ta...@gmail.com wrote:
> Hi all,
>
> I'm trying to generate 32 16bits registers using verilog generate :
>
> reg [15:0] Data_reg [N_REG-1:0];
> reg [N_REG-1:0] DataSelFlag;
> reg Data_reg_RST;
> reg Data_reg_LATCH ;
>
> genvar i;
> generate
> for(i=0;i<N_REG;i=i+1)
> begin : WordLine
> always@(posedge i_CORE_CLOCK)
> if(Data_reg_RST)
> begin
> Data_reg[i]=16'b1;
> DataSelFlag[i]=1'b0;
> end
> else
> if((Data_reg_LATCH)&&(i==i_EEAddressHVP2[5:1]))
> begin
> Data_reg[i]=io_MemoryOut&Data_reg[i];
> DataSelFlag[i]=1'b1;
> end
> end
> endgenerate
>
> I want to reset the 32 registers to 0xFFFF on the same i_CORE_CLOCK
> period, so I think using this parallel structure allow that.
> But when I simulate that, there is only the LSB of each register which
> is set to '1', all others bits stay equal to '0'.
>
> I'm begining with verilog ( I'm more used with VHDL ), so, maybee I do
> something bad..
>
> Could you help me please ?
>
> Best regards
Re
In fact, I was reading my post, and I've seen my error!
So Sorry for the post, this was the line : Data_reg[i]=16'b1;
The good line is Data_reg[i]={16{1'b1}};
This is my biggest probleme between verilog and vhdl, verilog is not
typed like VHDL..
Article: 117492"news reader" <newsreader@google.com> wrote in message news:eur0ab$tco$1@mawar.singnet.com.sg... > > For a large board with 133MHz SDRAM and FPGA, what are the approx. range > of > interconnect delays between FPGA pins and SDRAM pins? > Hi News, You should learn how to Google! ;-) propagation delay trace HTH, Syms.Article: 117493
On Mar 31, 7:12 pm, Ron <N...@spamex.com> wrote: > While browsing the page you provided a link to, I also found comparisons > of the Spartan-3 XC3S4000, XC3S5000, the Spartan-3L XC3S4000L, and the > "Spartan-3 EasyPath" XCE3S4000 and XCE3S5000. They all have me drooling. > The 4000 series has 96 multipliers and the 5000 series has 104 > multipliers!!! (Although in my case, there are only 64 usable > multipliers in either one). Make sure you don't depend on the ISE WebPACK tool chain. It doesn't support the larger Spartans. FYI, Altera's $150 Cyclone III starter kit has a EP3C25 with 66 multipliers and it is supported by the gratis Quartus II web edition. Tommy - not affiliated with either.Article: 117494
Hi All, Would anyone please tell me to find a standard PCI FPGA Xilinx board with ethernet port ? Thanks ThuyArticle: 117495
Have a look at Raggedstone1 Board http://www.enterpoint.co.uk/moelbryn/raggedstone1.html and the Ethernet Phy module http://www.enterpoint.co.uk/moelbryn/modules/ethernet_phy.html. This needs the ethernet MAC to be built into your FPGA design although we may have another solution coming in a few weeks time if we can fit it into our production schedule. John Adair Enterpoint Ltd. On 2 Apr, 17:41, Thuy Pham <t...@xilinx.com> wrote: > Hi All, > > Would anyone please tell me to find a standard PCI FPGA Xilinx board > with ethernet port ? > > Thanks > ThuyArticle: 117496
Ron Away from S3A but still S3 is our Raggedstone1 board. RS1-1500 with 32 multipliers. There is a 4 digit 7 seg display and 4 leds and if that is not enough add-on modules can give you more display options. Some details here http://www.enterpoint.co.uk/moelbryn/raggedstone1.html. Price is =C2=A3140/=E2=82=AC210/US$280(=C2=A390/=E2=82=AC135/US$180 student= )=2E If you want bigger our Broaddown2 board is now available with a XC3S2000 on board giving 40 multipliers and can a Virtex-4 added on for even more capability. John Adair Enterpoint Ltd. On 1 Apr, 00:40, Ron <N...@spamex.com> wrote: > Greetings, > > Would anyone happen to know where if could purchase an FPGA development > board with the Xilinx Spartan-3A XC3S1400A FPGA on it (or a socketed > board capable of accepting an XC3S1400A) please? =C2=A0I need the 32 > multipliers on the 1400A, but the starter board Xilinx sells through > Avnet only comes with the XC3S700A FPGA which only has 16 usable > multipliers (yes, I know there are actually 20, but since I'm doing > extended precision binary multiplication I can only use 16 of them. Why > on earth Xilinix incorporated a number of multipliers that isn't a power > of two is beyond me!). Incidentally, the FPGA doesn't necessarily have > to be a Spartan or even a Xilinx part as long as it has fast hardware > multipliers. > > My I/O needs are minimal. All I really need are 8 switches and 8 Leds > (although a hexadecimal display would be great). Basically all I need is > something to display a binary factor of the RSA-704 and RSA-768 > challenge numbers. ;-) > > Any suggestions? > > Thanks, > > RonArticle: 117497
I started working with the MGT's recently on a V4 PCI-E development board. I am just using the digital recevier in oversampling mode. Everything is working as expected. I put serial data in and get the bytes out of the backend. The data is asynchronous to the line rate clock and the oversampler works fine. My question is: how does the oversampler work? What kind of algorithm is used to extract the data? I doubt anyone will answer these questions since the design is proprietary and contains Xilinx IP. But it's worth a shot, right? : ) I simulated the system and found that by closing the data eye down to about 87 percent, the oversampler output the wrong data. I couldn't find any spec for this in Xilinx documentation. And I haven't tried in actual hardware. I am just trying to get a grasp on the boundaries of the oversampling circuit.Article: 117498
Thanks for the suggestion, I'm seriously taking it into consideration. I already contacted the local Xilinx supplier and working out the details of getting the XUP board. I just hope I can live up to the level of this project, all this hardware stuff is new to me and I'm kinda starting to long for the comfort and warmth of software implementations and having the OS take care of all the dirty details for me. I guess that's why the idea of using the PPC processors would be attractive to me, though I'd still have to take care of some low-level details myself (unless I load a tiny linux kernel on one or both of the processors, maybe? hmmm, it'll definitely take some careful (re)thinking). Well, thanks again to everyone, your responses have all been extremely helpful. Best Regards, Islam Ossama On Apr 2, 7:29 am, "Daniel S." <digitalmastrmind_no_s...@hotmail.com> wrote: > > You could opt for an hybrid solution... do all the massively parallelizable > things with FPGA fabric (after all, this is what FPGAs are all about when > applied to high-speed processing) and do the more > sequential/supervisory/etc. stuff on a CPU, preferably one of the PPC405 > cores present in V2P and 4VFX FPGAs - these real on-chip CPU cores will > provide far better performance than any soft-CPU you can possibly come up > with, the only caveat is that you will only have two such CPUs available at > most.Article: 117499
Hello, I would really appreciate if you could give me some insight on the following -Can you guide me to a link/example which runs thru the process of dynamic reconfiguration on Virtex2/4 step by step.I read and understood the paper you guys pointed to.I have also read the documentation on the Xilinx website(userguide etc).I would like to see an example implementation(could be trivial example).Else if you guys could give me some suggestions on a trivial example for me to test and see that partial dynamic reconfig actually works using the ICAP. -Also,from the paper I would assume that the patial bitstreams would be generated using the FPGA editor from Xilinx.Now assuming I want to have a set of bit streams loaded on to the Internal memory buffer of the microblaze,How do I do that i.e how do I store the bit streams on the microblaze(internal memory).I am using an ML310 board. Thanks!
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