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Hi, I understand that because of the 2d array CLB structure of FPGA, systolic architecture can be mapped efficiently into FPGA. however, what about the high IO ports requirements. if the outputs need to be stored in the memory, all the achieved speed will be lost due to the limited off chip ram bandwith [especially if using one bank]. so why this architecture is widely used in matrix algorithms implementation. The excessive I/O bandwidth requirement will surely dent the expected high clocking frequency am i missing something? ThanksArticle: 117626
In my defense, this is the only module (in my design) that isn't idiot proof thus my surprise at having to gate the write myself. One could argue that if xilinx is the one telling me (the user) the fifo is full shouldn't they already know not to allow any more writes? But I get your point. -Clark "Peter Alfke" <alfke@sbcglobal.net> wrote in message news:1175739444.142886.279410@n76g2000hsh.googlegroups.com... > That's the way controllers are designed. When a FULL signal is > generated, it is up to the data source to stop writing (and when > EMPTY,it's up to the destination to stop reading.) That's what these > status or handshake signals are for. > One could design these controllers to be idiot-proof, but that usually > sacrificesperformance or versatility. In a FIFO controller, you want > to be "lean andmean", to maintain max performance. > Nothing stops you as user to add "child-proof" circuitry, as long as > the loss of performance is acceptable. > Peter Alfke, Xilinx > > On Apr 4, 4:09 pm, "cpope" <cep...@nc.rr.com> wrote: > > FYI, I found that by gating the fifo write request with the fifo full signal > > I could prevent this problem. Apparently the fifo does not like to be > > written to once it is already full. > > > > -Clark > > > > "cpope" <cep...@nc.rr.com> wrote in message > > > > news:4613bd5c$0$18872$4c368faf@roadrunner.com... > > > > > Note: using EDk 8.2.02 with peripheral generated with the wizard with FIFO > > > enabled and one user interrupt that is set to the fifo_almostfull line. > > > > > I'm set up to generate interrupts on the fifo almost full signal but I get > > a > > > couple interrupts and then it stops. If I go read the occupancy register I > > > get a number(0x737) greater than the size of the fifo (0x400). If I then > > go > > > and manually read from the fifo data register(from gdb) I can get the > > > occupancy to go back to 0x400 and the next interrupt occurs when I run but > > > they stop shortly after. > > > > > So, > > > How could the occupancy be greater than the size of the fifo? > > > Have you seen anything like this before? > > > > > Thanks, > > > Clark > >Article: 117627
If I follow what you said...
1. You're using counters to make a slower clock from a faster one...
2. You get NO warnings when your counter goes 1 - 2n or 0 - (2n-1)...
3. You get a gated clock warning otherwise.
This makes perfect sense to me.
If you have a counter going through a 2n range then the electronics is
easier to make - and it probably just uses the MSB flip-flop of your counter
as the clock signal
BUT if you have a comparator and synchrnous reset to stop your counter going
to 2n then you have a problem... the synthesisor will use this MSB in
combination with the comparator, and you end up with a funky looking clock
circuit, which may or may not behave like you expect...
anyways, this is all beside the point, post your code which is inside your
clkdiv entity. Because there are bad ways of doing this, and REALLY bad ways
of doing this.
Just as an aside, I would try a different approach. use one global clock,
and then use a clock enable which arrives at the correct frequency... Good
for timing analysis... Good for synthesis... don't mess around with gated
clocks or mixed clocks until you really have to.
process_using_a_clock_enable : process (clk, rst)
begin
if rst = '1' then
--
elsif rising_edge (clk) then
if clock_enable = '1' then
--
end if;
end if;
end process;
generate this clock_enable = '1' signal in your clkdiv block...
I'll leave it there for you to experiment.
Ben
"Taylor Hutt" <thutt151@comcast.net> wrote in message
news:m3ps6lnhtq.fsf@localhost.localdomain...
>
>
> Hello again,
>
> First, as a side note, Xilinx has so far gone out of their way to get
> me the ability to file Webcases, and I'm grateful to everyone who
> helped in that process, most notably, because he's where the ball
> started rolling, Austin. (And, I will file Webcases, but I've been
> sick since last Wednesday)
>
> However, I've run into a rather odd situation which I haven't yet been
> able to figure out, and I'm not sure that this rises to the level of
> actually filing a web case at this point. Hopefully someone with more
> experience with the Xilinx tools will be able to point me in the right
> direction to figuring the situation out.
>
> First, the background:
>
> I'm creating an RS232 module which has send & receive. I calculate
> the basic ratio of clock frequency for the RS232 like this:
>
> constant clock_ratio : integer := clock_rate / bps;
>
> Where 'clock_rate' is 50,000,000 and 'bps' is 115200.
>
> I have a generic library which will generate a clock of a particular
> frequency, given a parameter 'n', which is the ratio of the FPGA clock
> to the desired clock -- in other words, 'clock_ratio.
>
> signal tx_clk : std_logic;
> signal rx_clk : std_logic;
>
> After the requisite parameter checking (i.e., ensure that 'bps > 0'), I
> generate the transmit and receive clock signals like this
>
> rs232_tx_clk : entity clkdiv
> generic map (n => clock_ratio)
> port map(clkin => clk,
> reset => '0',
> clkout => tx_clk);
>
> rs232_rx_clk : entity clkdiv
> generic map (n => clock_ratio * 16)
> port map(clkin => clk,
> reset => '0',
> clkout => rx_clk);
> end generate;
>
> When running, 'bitgen' produces the following warning:
>
> WARNING:PhysDesignRules:372 - Gated clock. Clock net
> rs232_port/tx_clk is sourced by a combinatorial pin. This is
> not good design practice. Use the CE pin to control the loading
> of data into the flip-flop.
>
> 'rs232_port/tx_clk' refers to the signal shown above, and it's the
> clock signal for the RS232 TX block.
>
> There is no warning for the 'rx_clk' signal, and if I change the 'n'
> value of the instantiation of 'clkdiv' from 'clock_ratio' to
> 'clock_ratio * 16', as present for the 'rx_clk' generation, the
> warning disappears.
>
> My questions are these:
>
> -- Why does the warning appear? As far as I can tell, there should
> be no combinatorial circuit -- but I'm a newbie, so I'm probably
> wrong. (If the clkdiv source is required, I can provide it)
>
> -- Can anyone give me a clue why multiplying the ratio by 16 causes
> the warning to go away?
>
> -- What can I do, besides multiplying by 16, to get the error to go
> away? (There is probably not enough information posted in this
> message to answer this question)
>
> -- Is there any way, short of looking at the ISE's RTL schematic, to
> see what the combinatorial circuit comprises (it's not obvious
> from the sources, as far as I can tell)?
>
> Thanks for the help,
> thutt
Article: 117628On Apr 5, 7:19 am, tlenom...@googlemail.com wrote: > Hi, > > I understand that because of the 2d array CLB structure of FPGA, > systolic architecture can be mapped efficiently into FPGA. however, > what about the high IO ports requirements. if the outputs need to be > stored in the memory, all the achieved speed will be lost due to the > limited off chip ram bandwith [especially if using one bank]. so why > this architecture is widely used in matrix algorithms implementation. > The excessive I/O bandwidth requirement will surely dent the expected > high clocking frequency > > am i missing something? > > Thanks I guess it depends on the memory requirements of your algorithm. Most modern FPGA's have embedded memory. If your storage requirements per node are small (from a few bytes to a few Kbytes depending on the type of embedded memory) you don't need to go offchip. In a matrix algorithm usually there is a "core" size required for the local operation. If the core is larger than would fit inside one FPGA you will run into the I/O bandwidth problems you mentioned.Article: 117629
morpheus wrote: > The need is to reduce the analog front end and also the risk in the > FPGA. By risk, I mean, with such a high frequency design, comes > tighter control on the design. I am trying to get a healthy balance. > I agree with you that its going to be hard to digitize the RF > directly. I should work on the analog downconversion to IF. > The more I think about it, the more redundant the chip gets (AD6654). > I think, by carefully considering undersampling techniques on the IF, > the FPGA design can be made easier. > The kicker is that i'll have to have 4 ADCs to do the job on the FE. > I do appreciate your input. I did get Matlab (finally...my manager > cringed paying $4500 for the license re-activation) so the modeling > should be insightful. > Be careful with undersampling, as it puts stringent jitter requirements on the ADC and it's clock that can be difficult to meet in the real world, especially with carrier frequencies above 100 MHz. If you do have analog downconversion to an IF, you generally will need separate ADCs unless all your frequencies of interest are within a bandwidth that is narrower than Fs/2. In your case, I think you have two (three if you also do 406 MHz) bands that do not have overlap and are not adjacent. In that case, you ought to be able to use a front end for each band, and then have each channel select which input band to use and then tune from that band digitally. That way you'd need only 2 ADCs (3 if you cover 406 MHz too) rather than the 4 you'd need by having one for each channel. Also, do you have a requirement to tune frequencies other than the emergency frequencies (121.5, 243 and 406), or do you just need to receive the beacon frequencies? If you just have 121.5 and 243, you may be able to play some tricks with aliasing with your front end mixer to put both at the same IF.Article: 117630
You have a loss-of-data condition which should NEVER be handled politely and automatically by the FIFO. You should either have the system designed to never be in that situation or use the (almost) full flag to make things happen so you don't overfill; usually this means shutting off the flow of data, not simply ignoring it. cpope wrote: > In my defense, this is the only module (in my design) that isn't idiot proof > thus my surprise at having to gate the write myself. One could argue that if > xilinx is the one telling me (the user) the fifo is full shouldn't they > already know not to allow any more writes? But I get your point. > > -Clark > > > "Peter Alfke" <alfke@sbcglobal.net> wrote in message > news:1175739444.142886.279410@n76g2000hsh.googlegroups.com... >> That's the way controllers are designed. When a FULL signal is >> generated, it is up to the data source to stop writing (and when >> EMPTY,it's up to the destination to stop reading.) That's what these >> status or handshake signals are for. >> One could design these controllers to be idiot-proof, but that usually >> sacrificesperformance or versatility. In a FIFO controller, you want >> to be "lean andmean", to maintain max performance. >> Nothing stops you as user to add "child-proof" circuitry, as long as >> the loss of performance is acceptable. >> Peter Alfke, Xilinx >> >> On Apr 4, 4:09 pm, "cpope" <cep...@nc.rr.com> wrote: >>> FYI, I found that by gating the fifo write request with the fifo full > signal >>> I could prevent this problem. Apparently the fifo does not like to be >>> written to once it is already full. >>> >>> -Clark >>> >>> "cpope" <cep...@nc.rr.com> wrote in message >>> >>> news:4613bd5c$0$18872$4c368faf@roadrunner.com... >>> >>>> Note: using EDk 8.2.02 with peripheral generated with the wizard with > FIFO >>>> enabled and one user interrupt that is set to the fifo_almostfull > line. >>>> I'm set up to generate interrupts on the fifo almost full signal but I > get >>> a >>>> couple interrupts and then it stops. If I go read the occupancy > register I >>>> get a number(0x737) greater than the size of the fifo (0x400). If I > then >>> go >>>> and manually read from the fifo data register(from gdb) I can get the >>>> occupancy to go back to 0x400 and the next interrupt occurs when I run > but >>>> they stop shortly after. >>>> So, >>>> How could the occupancy be greater than the size of the fifo? >>>> Have you seen anything like this before? >>>> Thanks, >>>> ClarkArticle: 117631
These are my experience from Xilinx ISE Webpack. System: Thinkpad R60 (Intel Core 2 duo) Xubuntu 6.20 Edgy eft, 32bit (Large extra SW installed: Eclipse, Openoffice, some other KDE apps) Tried software: ISE Webpack 9.1i First attempt: I downloaded the web installer zip archive, unziped and ran ./setup as root. Filled in the information requested and clicked to start installation. Program terminated without any error message. Second attempt: Downloaded the complete 1,4 GB file. Unzipped and ran ./setup as root. Everything worked without problems! "cd:ed" to the installation, sourced settings.sh, executed bin/lin/ ise. Started without complaints. Note: I have not tested to do anything inside ISE yet. Hope this may help someone!Article: 117632
I have a hardware designed by VHDL, it has 32MB SDRAM plus input and output, thinking about adding microblaze to add new functionality, I want to know what is the best way to exchange data between my hardware and microblaze, some questions I need to clarify. Can microblaze access the same 32MB SDRAM or it has to have its own memory space? if it can, then the quick solution is share memory space in SDRAM to exchange data. my guess is not, what is the way around this? is FIFO a solution? how to make a FIFO communicate through OPB? is it a solution to make my hardware a customer peripherial and communicate through OPB? can I use FSL(Fast simplex link)? thanks jetArticle: 117633
Ken Soon wrote: > > Yeh kind of learnt little about the refreshing of the DRAM in school and it > was difficult. > Hmm, i seriously need some ultra pure basic on how to use the DRAM, any such > books or websites or watever? I'll repeat myself: read some DRAM's specs, you can start with those on your board - most DRAM manufacturers do a reasonably thorough job at describing how DRAMs work. > Meaning the structure of the HDL codes is written such that the synthesis > will infer what kind of devices to use. > (Amazing..write first or write later also have effect on the device being > used...) oh the XST guide offered alot of help on this. The memory access policy will not change the "kind of device", all BRAMs are the same but not all FPGAs implement all access policies. Devices prior to the Virtex4 do not support read-before-read while write-before-read is supported by all Xilinx devices I know of. > Wow, the synthesis report is so cool. It tells me alot of information, like > which modules contains their respective warnings, the devices inferred from > the each modules (like adders, subtractors,etc) and analysis of different > values for the data types. > Thumbs up! Synthesis and implementation logs are your friends, remember to inspect them thoroughly and you will run a lower risk of getting chastised for posting newbie questions... I can usually find answers to about 90% of my would-be questions in there. > Anyway got this information on the BRAMs > 57 rams > RAMB16_S2_S2 : 2 > RAMB16_S36_S36 : 18 > RAMB16_S4_S4 : 25 > RAMB16_S9_S9 : 12 > All are 16kbits Ram with different port widths for A and B (as indicated by > 16_Sx_Sy) Any RAM uses exactly one BRAM and on modern Xilinx devices, all BRAMs are 16kbits so any sub-16kbits RAM you infer will consume one 16kbits BRAM even if you use only 256bits. This part of the report only tells you the port widths of the different BRAMs used by your design, now you need to hunt down each of these instances and see how many addresses each has to determine how many kbits each actually uses. If you are having a hard time determining which BRAMs are used where, you should look at the "Macro Statistics" instead: the Macro Stats reports memories with their actual inference parameters instead of the final report report's raw BRAM usage. Macro Statistics # Block RAMs : 17 256x16-bit dual-port block RAM : 1 256x72-bit dual-port block RAM : 4 512x32-bit dual-port block RAM : 8 512x64-bit dual-port block RAM : 4 Macro statistics allow me to easily find out the size of all the memories present in my design so I can cross-check with the final report to determine whether or not the synthesis tools have mapped everything as expected... and here, I do not remember what the 256x16 RAM is for so I'll have to investigate where it came from next time I work on the project I pasted this from. >> 2) If your coefficient tables (ROMs?) use under half a BRAM and only one >> port, you should be able to merge two tables into one BRAM by using both >> ports for reading: map one address to "'0' & addrA" and the other to "'1' > & addrB". > Nah, no chance. from my final synthesis report, all of them are using dual > port rams. Anyway the codes were already written for dual port BRAM so there > shouldn't be any reason that my coefficient tables will be using under half > a BRAM, ya? I am not psychic... without knowing exactly how the BRAMs are being used, I cannot tell if packing is applicable to your case. If your coefficient table BRAMs use the same inference template and are duplicated to provide multiple coefficients from a same table but are never written to (effectively used as ROMs), you can create a dual read port template and remove half of those BRAMs. If your coefficients need to be programmable, this trick is still applicable but you will have to implement the trickier "true dual-port BRAM" template and manage writes somehow. At this point, I think this probably is your best avenue. > Hmm oh yah I have used 4570 out of 14752 slices. Now I read that I can use > the distributed rams from the remaining slices and I thinking it is not > enough to reduce the BRAMs till there is no overloading but it certainly > reduce to a extent. > I went to check out the language templates for using distributed rams, > but... they all support only 1bit data storage while many bits > address...(what's use can this be..) hmm but then I read that this > distributed rams can be combined to form longer data bits storage (some sort > of combination). If RAMs are left alone (no pragmas, no attributes, no force options in tool settings), synthesis tools will automatically map memories to available resources: they will try to map all large-ish memories to BRAMs until all BRAMs are used and then start using distributed (LUT) memory for smaller memories. > So I thought of looking at 1) and found out that in my code there was this > constraint already being used > <<attribute ram_style of mem_array : signal is "block">>; > Thus, I changed it to <<attribute ram_style of mem_array : signal is > "pipe_distributed">> > However, it seems to continue forever during my synthesis. It takes forever because Map/PAR is unable to complete routing when all memory gets forced into LUT memory. Remove (comment) this attribute altogether to let synthesis tools decide which memories should be dumped in BRAMs and which ones should use distributed memory. Alternatively, you could add a generic port to the template to specify block or distributed on a per-instance basis. Note: large distributed memories will become slow unless you add multiple pipelining registers on their output so you should be careful when using these. > Currently, I'm using 57 out of 36 BRAMS (after lowering the H taps) > 57 - 36 = 21 => 378000 bits of ram... 10k free slices * 2 LUTs per slice * 16bits per LUT = 320kbits of available distributed RAM = no fit, assuming all your BRAMs are fully used. The fact that synthesis did not flat out say that there was no fit means some of your BRAMs are definitely not completely used.Article: 117634
On Apr 5, 12:29 am, Sylvain Munaut <tnt-at-246tNt- dot-...@youknowwhattodo.com> wrote: > >>> If you had a belt tight around the equator of the earth, how > >>> much length do you figure you'd need to add to raise the belt to an > >>> altitude of 1 foot across the entire distance and why? > > The earth's equatorial radius is 3,963.189mi, so elevate the radius by > > 1 ft, from the top view, it would be like drawing an outer circle with > > a 1 ft border. From this we can calculate the new radius and hence the > > addition in the radius gives us the new circumference and thus the > > addition in length.....what do u think...am I way off??? > > You don't need the earth radius. > > Let's says the original radius is r and expressed in feet, the > original belt would be 2*pi*r . By adding 1 feet, you now have > a belt of 2*pi*(r+1). So you added 2*pi feet to it no matter what. > > Sylvain Yeah I knw....I have a habit of thinking out loud....atleast I wasnt way off Any idea on the estimation on the number of gas pumps in the US?Article: 117635
"John_H" <newsgroup@johnhandwork.com> wrote in message news:13185gkp47lpq2c@corp.supernews.com... > > Now, do you know how to properly pipeline? How about state machines: can > you design a soda dispenser state machine to count change? And how many > gas stations would you estimate are in the US (please explain your > reasoning)? If you had a belt tight around the equator of the earth, how > much length do you figure you'd need to add to raise the belt to an > altitude of 1 foot across the entire distance and why? > > Good luck with your interviewing. Hi John, I used to drive my buddy Kurt insane with these questions. The secret is to ask him about two pints into a Friday night Guinness session. After four pints he'll let you tell him the answer. The next few pints erase his memory so you can do it all over again a couple of weeks later. Eventually he bought himself a notebook! For example, a brother and sister were born on the same day a few minutes apart. But they're not twins. How? Cheers, Syms.Article: 117636
Matthias Einwag <matthias.einwag@web.de> wrote: >Hi, >thanks for your answer at first > >> Your bandwidth requirement is less than 800kB/s. How about compact >> flash or an SD-card? These are well known and there are loads of >> resources available on the internet. >Flash is no option, because I write an read the data streams, and this >should also be possible 24/7, where Flash would die fast. >It will be a kind of mixer application (with the possibilty for delay on >each channel), where incoming and outgoing audio streams are using a >rather complex bus system. I want the Microblaze to handle the higher >level bus protocols, store the data in RAM and load the mixed stream >after the delay and give it back on the bus system. >Because the Microblaze should also run of this RAM (I will have SPI >Flash attached as FPGA Configuration and Microblaze Program Storage, but >I think it's too slow to run the program directly out of it), the >bandwith memory is higher than 800kB/s. But I have no experience how >fast the memory should be for a good Microblaze performance. > >> There are no free _usefull_ cores to control DDR memory. >So Xilinx OPB DDR Interface is not useful? At the moment SDRAM is my >favourite. But I'm still not sure if Xilinx SDRAM Interfaces work with >Spartan 3E :( I ended up with rolling my own DDR interface for a Spartan3. IIRC the Spartan 3E is a bit slower than the Spartan3. The Spartan3 speedgrade 4 just manages to interface with DDR memory at 100MHz (the memory itself needs to meet 133MHz timing). However, most DDR (and I suppose also SDRAM) memory can be run at 83MHz as well. I think builbing an SDRAM implementation at 83MHz is very feasable using 2 clocks (one 'normal' and one with a 90 degree phase shift). -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 117637
"Gordon Freeman" <gordonfreeman1983@gmail.com> wrote:
>On Apr 5, 1:16 am, "Daniel S." <digitalmastrmind_no_s...@hotmail.com>
>wrote:
>> Gordon Freeman wrote:
>> >> Watch the values change in the accumulators as you add and subtract the
>> >> input values.
>>
>> > Hi everyone!
>> > Thank you for your reply!
>> > I used ModelSim to simulate. The result is the same when I canculate
>> > by calculator.
>> > But when I implement on FPGA, it don't work too.
>> > I design IIR filter with 10 orders. I use Matlab to generate
>> > coefficients for filter (b(k) and a(k)). For coefficient "b", I
>> > multiply with 2^14 and multiply with 2^5 for coefficent "a". After
>> > that I round them. These coefficients stored in LUT. I use SDA for
>> > filter. Because I think IIR filter include tow FIR filter. One filter
>> > with coefficient "b" and one with coefficient "a". Is it right?
>>
>> Check your synthesis log to make sure your design did not get 'optimized'
>> away. If you forgot some control signals somewhere, it is possible that
>> synthesis deduced that some of your design had static elements, removed
>> them to optimize, then deduced that everything else is now unconnected and
>> removed that as well.
>>
>> BTW, also make sure your VHDL agrees with your board's reset polarity.
>
>Hi.
>Thank you for your reply.
>I design it by myself and RTL coding in Verilog and I implement it on
>Xilinx FPGA (XC3S400).
>I use Matlab to generate coefficients. And this is the code:
>
>% All frequency values are in Hz.
>Fs = 48000; % Sampling Frequency
>
>N = 10; % Order
>Fpass1 = 3000; % First Passband Frequency
>Fpass2 = 6000; % Second Passband Frequency
>Apass = 1; % Passband Ripple (dB)
>Astop = 80; % Stopband Attenuation (dB)
>
>% Construct an FDESIGN object and call its ELLIP method.
>h = fdesign.bandpass('N,Fp1,Fp2,Ast1,Ap,Ast2', N, Fpass1, Fpass2, ...
> Astop, Apass, Astop, Fs);
>Hd = ellip(h);
>
>% Get the transfer function values.
>[b, a] = tf(Hd);
>
>The result:
>
>a(k) =
>-8.0088
>30.2376
>-70.5488
>112.3786
>-127.5439
>104.4117
>-60.9016
> 24.2544
>-5.9702
> 0.6931
>
>b(k) =
> 0.0004
> -0.0019
> 0.0040
> -0.0050
> 0.0036
> 0.0000
> -0.0036
> 0.0050
> -0.0040
> 0.0019
> -0.0004
>
>After that:
>
>round(a(k)*2^5)=
>32
>-256
>968
>-2258
>3596
>-4081
>3341
>-1949
>776
>-191
>22
>
>round(b(k)*2^14)=
>7
>-31
>65
>-82
>59
>0
>-59
>82
>-65
>31
>-7
>
>The filter output result will be divide by 2^5 * 2^14.
>
>And filter structure is Direct Form I and this is biquads.
>
>I think it run into overflow errors, too. But I don't know how can I
>modify it.
A 10th order filter is very prone to overflows because some sections
will have a high Q factor. You said you simulated the design; try to
do that again with a maximum amplitude input signal and see what
happens.
It is probably better to create several 4th order filters and cascade
these. However, this may deteriorate the filtering result.
--
Reply to nico@nctdevpuntnl (punt=.)
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Article: 117638"morpheus" <saurster@gmail.com> wrote in message news:1175787053.797301.170230@d57g2000hsg.googlegroups.com... > On Apr 5, 12:29 am, Sylvain Munaut <tnt-at-246tNt- > dot-...@youknowwhattodo.com> wrote: >> >>> If you had a belt tight around the equator of the earth, how >> >>> much length do you figure you'd need to add to raise the belt to an >> >>> altitude of 1 foot across the entire distance and why? >> > The earth's equatorial radius is 3,963.189mi, so elevate the radius by >> > 1 ft, from the top view, it would be like drawing an outer circle with >> > a 1 ft border. From this we can calculate the new radius and hence the >> > addition in the radius gives us the new circumference and thus the >> > addition in length.....what do u think...am I way off??? >> >> You don't need the earth radius. >> >> Let's says the original radius is r and expressed in feet, the >> original belt would be 2*pi*r . By adding 1 feet, you now have >> a belt of 2*pi*(r+1). So you added 2*pi feet to it no matter what. >> >> Sylvain > > Yeah I knw....I have a habit of thinking out loud....atleast I wasnt > way off > Any idea on the estimation on the number of gas pumps in the US? It's not about the answer, it's about the process. Can you demonstrate how to come up with a credible engineering estimate with sparse real data (your own experience)? If you rely on precise data as a crutch (diameter of the earth to 7 decimal places) you may not find a place as a "superb" engineer, but still quite passable.Article: 117639
"Symon" <symon_brewer@hotmail.com> wrote in message news:46151b41$1_2@x-privat.org... > "John_H" <newsgroup@johnhandwork.com> wrote in message > news:13185gkp47lpq2c@corp.supernews.com... >> >> Now, do you know how to properly pipeline? How about state machines: can >> you design a soda dispenser state machine to count change? And how many >> gas stations would you estimate are in the US (please explain your >> reasoning)? If you had a belt tight around the equator of the earth, how >> much length do you figure you'd need to add to raise the belt to an >> altitude of 1 foot across the entire distance and why? >> >> Good luck with your interviewing. > Hi John, > I used to drive my buddy Kurt insane with these questions. The secret is > to ask him about two pints into a Friday night Guinness session. After > four pints he'll let you tell him the answer. The next few pints erase his > memory so you can do it all over again a couple of weeks later. Eventually > he bought himself a notebook! > For example, a brother and sister were born on the same day a few minutes > apart. But they're not twins. How? > Cheers, Syms. Assuming the same day of the same year, 1) At least one is adopted. 2) They're in a monastery (and not related). 3) At least one is born to a surrogate mother. A man marries his daughter. Legally. How? A (biological) father and son are in a car accident, both rushed to the hospital. The unconscious son is wheeled into the operating room for emergency surgery. At first glance, the doctor turns pale and declares "we need another surgeon to perform this operation; that's my own (biological) son!" How can this be? [I added the "biological" notes to try to avoid some of the arguments related to your question.]Article: 117640
"CMOS" <manusha@millenniumit.com> wrote in message news:1175743403.927787.98160@e65g2000hsc.googlegroups.com... > hi, > > having a state machine in a datapath element a bad design practice? > > CMOS > no MikeArticle: 117641
"John_H" <newsgroup@johnhandwork.com> wrote in message news:131a8e3mm8hpl4a@corp.supernews.com... > > A (biological) father and son are in a car accident, both rushed to the > hospital. The unconscious son is wheeled into the operating room for > emergency surgery. At first glance, the doctor turns pale and declares > "we need another surgeon to perform this operation; that's my own > (biological) son!" How can this be? I must be missing something. The surgeon is the kid's mother?!Article: 117642
"John_H" <newsgroup@johnhandwork.com> wrote in message news:131a8e3mm8hpl4a@corp.supernews.com... > "Symon" <symon_brewer@hotmail.com> wrote in message >> I used to drive my buddy Kurt insane with these questions. For example, a >> brother and sister were born on the same day a few minutes apart. But >> they're not twins. How? >> Cheers, Syms. > > Assuming the same day of the same year, > 1) At least one is adopted. > 2) They're in a monastery (and not related). > 3) At least one is born to a surrogate mother. > Good effort, but no. They're biological brother and sister, no fancy IVF nonsense involved, same mother and father. No relativistic effects either! IIRC Kurt was similarly very inventive too... :-) > > A man marries his daughter. Legally. How? > > A (biological) father and son are in a car accident, both rushed to the > hospital. The unconscious son is wheeled into the operating room for > emergency surgery. At first glance, the doctor turns pale and declares > "we need another surgeon to perform this operation; that's my own > (biological) son!" How can this be? [I added the "biological" notes to > try to avoid some of the arguments related to your question.] > I've heard these, and, rest assured, so has Kurt! :-) Cheers, Syms.Article: 117643
"Pete Fraser" <pfraser@covad.net> wrote in message news:52686$461527ab$43656287$21395@msgid.meganewsservers.com... > "John_H" <newsgroup@johnhandwork.com> wrote in message > news:131a8e3mm8hpl4a@corp.supernews.com... > >> >> A (biological) father and son are in a car accident, both rushed to the >> hospital. The unconscious son is wheeled into the operating room for >> emergency surgery. At first glance, the doctor turns pale and declares >> "we need another surgeon to perform this operation; that's my own >> (biological) son!" How can this be? > > I must be missing something. > The surgeon is the kid's mother?! Bingo. This addresses bad assumptions and was easier to trip people up a decade or two ago.Article: 117644
> I understand that because of the 2d array CLB structure of FPGA, > systolic architecture can be mapped efficiently into FPGA. however, > what about the high IO ports requirements. if the outputs need to be > stored in the memory, all the achieved speed will be lost due to the > limited off chip ram bandwith [especially if using one bank]. so why > this architecture is widely used in matrix algorithms implementation. > The excessive I/O bandwidth requirement will surely dent the expected > high clocking frequency You are entirely correct. There are all kinds of designs where the memory and IO bandwidths are not a problem, but there are other cases where those limitations can reduce the FPGA to a relatively small amount of logic that spends most of its time starved for data. Those are the times when you try to keep a straight face and explain to Xilinx that you really do need 10,000 IO to keep the device busy (a true story from Los Alamos), or when you start considering completely different approaches, preferably with the help of one of the consultants who frequent this forum.Article: 117645
John_H wrote: > "Symon" <symon_brewer@hotmail.com> wrote in message > news:46151b41$1_2@x-privat.org... >> "John_H" <newsgroup@johnhandwork.com> wrote in message >> news:13185gkp47lpq2c@corp.supernews.com... >>> Now, do you know how to properly pipeline? How about state machines: can >>> you design a soda dispenser state machine to count change? And how many >>> gas stations would you estimate are in the US (please explain your >>> reasoning)? If you had a belt tight around the equator of the earth, how >>> much length do you figure you'd need to add to raise the belt to an >>> altitude of 1 foot across the entire distance and why? >>> >>> Good luck with your interviewing. >> Hi John, >> I used to drive my buddy Kurt insane with these questions. The secret is >> to ask him about two pints into a Friday night Guinness session. After >> four pints he'll let you tell him the answer. The next few pints erase his >> memory so you can do it all over again a couple of weeks later. Eventually >> he bought himself a notebook! >> For example, a brother and sister were born on the same day a few minutes >> apart. But they're not twins. How? Given that the definition of twins is that they're born from the same pregnancy, I see two options : - They are only half brother and sister : Same father, different mother and they just happened to give birth at the same time. - They are from the same mother but different pregnancy ... some women have two uteruses, one baby in each could be viewed as different pregnency and even with slightly different conception date, they could come to term at the same time (one of them induced for convenience for example ...). > A man marries his daughter. Legally. How? Couldn't the man have a daughter when he was young and either abandon her, or give her for adoption, then ... twenty years later decides to find him self a young wife and by "chance" choose his own daughter without knowing it ... SylvainArticle: 117646
Symon a écrit : > For example, a brother and sister were born on the same day a few minutes > apart. But they're not twins. How? Hasn't this something to do with a boat crossing the date change line ? I seem to recall something like that ... NicolasArticle: 117647
Neil, we all have to live in the real world. If you think of something that needs 10,000 I/O, then it is time to start thinking differently. Usually there are many ways to "skin a cat". I remember when 16 pins were the norm, and 40 pins was the max. But we can now give you almost a thousand usable I/O in BGAs, with no fear of accidentally bending the pins. But let's not go too much further, otherwise the pc-board design becomes worse than a nightmare. Ultra-high speed serial communication looks more extendable, especially once we learn to put the electrical-to-optical (and vice vers) transducers on the chip... Peter Alfke ================== On Apr 5, 10:37 am, Neil Steiner <neil.stei...@vt.edu> wrote: > > I understand that because of the 2d array CLB structure of FPGA, > > systolic architecture can be mapped efficiently into FPGA. however, > > what about the high IO ports requirements. if the outputs need to be > > stored in the memory, all the achieved speed will be lost due to the > > limited off chip ram bandwith [especially if using one bank]. so why > > this architecture is widely used in matrix algorithms implementation. > > The excessive I/O bandwidth requirement will surely dent the expected > > high clocking frequency > > You are entirely correct. There are all kinds of designs where the > memory and IO bandwidths are not a problem, but there are other cases > where those limitations can reduce the FPGA to a relatively small amount > of logic that spends most of its time starved for data. > > Those are the times when you try to keep a straight face and explain to > Xilinx that you really do need 10,000 IO to keep the device busy (a true > story from Los Alamos), or when you start considering completely > different approaches, preferably with the help of one of the consultants > who frequent this forum.Article: 117648
> Neil, we all have to live in the real world. Sad but true. ;) But then isn't our profession in the business of trying to change that world? > If you think of something that needs 10,000 I/O, then it is time to > start thinking differently. Hence the implied reference to Mr. Andraka and others on this forum. The context was a sparse matrix multiplication core (double precision IEEE 754), that we wanted to run on the Cray XD1. The original software code had been finely optimized to run on regular processors. A pipelined FPGA design could of course run circles around the software processors, but even though the FPGA board had good memory and communication bandwidth (3.2 GB/s each, I believe) and connections to adjacent blades (four each at 2.0 GB/s, back in 2005), it still spent five out of every seven cycles waiting for data. The functionality was both memory intensive and computation intensive, so there was no simple trade-off to be had, but because this code was used so extensively on supercomputer-sized problems, a significant performance increase could have made a big difference. (Allowing for Ahmdal's law, I believe this might still have shaved days or weeks off some of the really big problems.) They probably shouldn't have stuck an intern on the problem. ;)Article: 117649
I'm looking for the perfect FPGA dev board for a project I'm contributing to. I've found one that is *almost* ideal, with the drawback being lack of support for 66 MHz PCI bus rates, and an FPGA that's too small: The MESA 5120ds http://www.mesanet.com/pdf/parallel/5i20ds.pdf I was hoping the community would have some suggestions. Basically, we need the FPGA for some high-speed custom data conditioning, and an easy way to get the processed data onto a PC. We'd like: - A fairly large FPGA, preferably Xilinx (something as big as a Virtex- II VP20 or VP30 chip) - PCI capabilities at 66 MHz/32 bits - (optionally) a PCI bridge chip to greatly simplify the FPGA logic (that is, we'd only need to deal with simple handshaking, rather than using a PCI core and having to create an embedded system) - Failing the last requirement, the FPGA should be able to handle the Xilinx LogiCORE PCI IP - 20-30 LVDS pairs through general I/O - software examples with source code - working drivers (for either Windows or Linux) We'd like this for a high-speed custom DAQ system we're making. Thanks in advance!
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