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Messages from 117650

Article: 117650
Subject: Re: PCI FPGA Dev Board Suggestions
From: "Kunal" <kunals.spam.account@gmail.com>
Date: 5 Apr 2007 18:01:59 -0700
Links: << >>  << T >>  << A >>
I should also mention that we'd like to keep the cost under $2000, and
emphasize that we are really trying to stay away from an embedded
system (essentially outsourcing the PCI tasks to a PCI bridge chip).

Kunal wrote:
> I'm looking for the perfect FPGA dev board for a project I'm
> contributing to. I've found one that is *almost* ideal, with the
> drawback being lack of support for 66 MHz PCI bus rates, and an FPGA
> that's too small:
> The MESA 5120ds
> http://www.mesanet.com/pdf/parallel/5i20ds.pdf
>
> I was hoping the community would have some suggestions. Basically, we
> need the FPGA for some high-speed custom data conditioning, and an
> easy way to get the processed data onto a PC.
>
> We'd like:
> - A fairly large FPGA, preferably Xilinx (something as big as a Virtex-
> II VP20 or VP30 chip)
> - PCI capabilities at 66 MHz/32 bits
> - (optionally) a PCI bridge chip to greatly simplify the FPGA logic
> (that is, we'd only need to deal with simple handshaking, rather than
> using a PCI core and having to create an embedded system)
> - Failing the last requirement, the FPGA should be able to handle the
> Xilinx LogiCORE PCI IP
> - 20-30 LVDS pairs through general I/O
> - software examples with source code
> - working drivers (for either Windows or Linux)
>
> We'd like this for a high-speed custom DAQ system we're making.
>
> Thanks in advance!


Article: 117651
Subject: Re: Digital Receiver chip suggestion
From: "Marty Ryba" <martin.ryba.nospam@verizon.net>
Date: Fri, 06 Apr 2007 01:27:55 GMT
Links: << >>  << T >>  << A >>
We're hitting some slightly different bands, but the general concept is the 
same. We're not trying to sample different bands simultaneously though.

IIRC, our HW folks chose the Linear LTC2227. It is nicely low in power draw, 
is single 3V supply, and it handles undersampling pretty well. For instance, 
we're driving it with a 25.6 MHz clock rate with a 380 MHz IF (5 MHz BW 
signal in something like the 11th aliasing band).

The bits go into a TI "Graychip" GC5016 (I figure that's who you're 
referring to when you said Grayscale). We use a small Altera Cyclone II to 
package this data for sending to a AD Blackfin DSP (BF537?). The Blackfin 
can run Linux (uCLinux), which is pretty impressive for a cheap low power 
chip.

Like one of the other responders said, you could pick your clocking rate 
and/or mixer frequencies (if any) so that two (or more) of your bands fall 
into different parts of your (folded) spectral response. The narrower each 
of your bands are and the higher the clock rate the easier this gets to 
plan. Then your DDC can pick each channel off regardless of band. Remember 
that depending on the folding and mixing your frequencies might be 
"reversed." You usually can tell the DDC to conjugate the output to get the 
net result straight.

HTH,

Marty

"morpheus" <saurster@gmail.com> wrote in message 
news:1175702771.897449.271210@w1g2000hsg.googlegroups.com...
> Hi Folks,
> I've been active on this forum asking questions on digital receiver.
> Earlier I was doing most of the work in the FPGA (thats how I
> architected it). Due to space constraints, this radio is going to be
> used as a Search and Rescue radio for the coast guard, I am re-
> architecting and planning to use a multi-channel  digital receiver
> chip instead. This helps us to get rid of most of our analog front end
> and do minimal processing in the FPGA, and thus use a smaller FPGA
> also.
> The chips that come to mind are AD6654 and AD6624A. The AD6654A is
> special as it has the in-built ADC.
> Now some specs on my design requirements
> a) 4 channels,
> b) 121.5MHz - 245MHz band of interest.
> c) AM, FM, FSK demodulation.
> I have also looked at some Grayscale chips. I was wondering if you
> have any more suggestions.
> Thanks
> Morpheus
> 



Article: 117652
Subject: Transition from ASIC to FPGA
From: "From_ASIC_2_FPGA" <praneet.dixit@gmail.com>
Date: 5 Apr 2007 18:58:11 -0700
Links: << >>  << T >>  << A >>
Hi All,

I've been working on ASICs for quite a while and now Iam required to
move to FPGA domain.
I'd be glad if someone could give some suggestions on what I should
know, where to start how easy or difficulty is it going to be.
I'd like to know if anyone has had such experience and would like to
knopw their vies regarding the same.

Thanks.


Article: 117653
Subject: Re: what is the best practice to exchange data between microblaze softcore and customer hardware writen in VHDL
From: "Alan Nishioka" <alan@nishioka.com>
Date: 5 Apr 2007 20:31:32 -0700
Links: << >>  << T >>  << A >>
On Apr 5, 7:33 am, "jetq88" <jetq5...@gmail.com> wrote:
> I have a hardware designed by VHDL, it has 32MB SDRAM plus input and
> output,  thinking about adding microblaze to add new functionality, I
> want to know what is the best way to exchange data between my hardware
> and microblaze, some questions I need to clarify.
>
> Can microblaze access the same 32MB SDRAM or it has to have its own
> memory space?

Yes, you can put custom hardware on the opb bus and both can access
the same SDRAM (been there).


>  if it can, then the quick solution is share memory space
> in SDRAM to exchange data. my guess is not, what is the way around
> this?
>
> is FIFO a solution? how to make a FIFO communicate through OPB?

Yes, you can use a FIFO (done that).


> is it a solution to make my hardware a customer peripherial and
> communicate through OPB?

Yes, you can do this too (done that too).


> can I use FSL(Fast simplex link)?

Yes, this is another option (haven't gone there).

You are designing the hardware.  You can make it do anything you want
it to.  It just depends on what you want to design, and what your
other requirements are.

Alan Nishioka


Article: 117654
Subject: Memory Interface Recommendation for ML410 Design
From: "Dima" <Dmitriy.Bekker@gmail.com>
Date: 5 Apr 2007 23:06:57 -0700
Links: << >>  << T >>  << A >>
Hello,

I am working on my MS Thesis which involves building a PowerPC based
system
on the ML410 development board from Xilinx (V4FX60 FPGA). This system
will
need to do some intense computation (accelerated through hardware) and
will
need to process a lot of data. I need to squeeze out as much
performance out
of my memory interfaces as possible, so cache support will be
critical. I
will be using the APU controller and FCB bus to transfer data to
hardware
for co-processing, so my CPU speed is limited at 275 MHz.

Right now, I have a design working with the following:
266 MHz CPU (single core for now)
266 MHz FCB (fabric co-processor bus)
200 MHz DDR2
100 MHz PLB
100 MHz OPB
PLB BRAM

I use the DDR2 primarily as heap space for reading in a large amount
of
data. The rest of the program sections can go to PLB BRAM or to DDR2.
Now,
all the cores that I am using are the standard ones that come in EDK
9.1i.
As far as the standard memory cores, I am limited to 266 MHz on the
DDR2
controller (my DIMM is DDR2-400, so thus I clock it at a lower 200
MHz), and
100 MHz for DDR controller, if I choose to use it (the DDR component
on the
board can go up to 266 MHz, according to the ML410 manual). So, given
these
specifications, what is the best I can do for performance? I recently
stumbled upon MPMC2 (multiport memory controller - from Xilinx),
should I
try that? What benefits can it provide (I am not using ethernet
controllers). Can that give me any more in terms of performance than
what I
have setup already? What about OCM - can I leverage that somehow to
supplement the caches? Just to recap, these are the memory/controller
specifications:

DDR2-400 DIMM: memory - up to 200 MHz, controller in EDK - up to 266
MHz
(frequency limited by memory)
DDR component: memory - up to 266MHz, controller in EDK - 100 MHz
(frequency
limited by controller)

Any suggestion on this issue would be highly appreciated. I'd like to
set-up
a base system first before going into the development of the hardware
accelerator.

Thanks

- Dmitriy


Article: 117655
Subject: virtex 4vfx12 evaluation kit schematics
From: ashasravanthi@gmail.com
Date: 5 Apr 2007 23:15:38 -0700
Links: << >>  << T >>  << A >>
hi,
     can any please tell me where i can get virtex 4vfx12 evaluation
kit schematics.


thanks
asha.


Article: 117656
Subject: Nios2: elf2hex settings for epcs bootloader
From: "Dolphin" <Karel.Deprez@gemidis.be>
Date: 6 Apr 2007 00:34:23 -0700
Links: << >>  << T >>  << A >>
Hello,

I have recompiled the assembler code for the bootloader of the Nios2.
After this compilation I have an .elf file. Now I have to convert this
elf file to a hex file which can be used as memory content for the
epcs controller RAM. I guess this should be done with the elf2hex
command.
Can anybody tell me which prms I have to use for the:


Article: 117657
Subject: Nios2: elf2hex settings for epcs bootloader
From: "Dolphin" <Karel.Deprez@gemidis.be>
Date: 6 Apr 2007 00:35:08 -0700
Links: << >>  << T >>  << A >>
Hello,

I have recompiled the assembler code for the bootloader of the Nios2.
After this compilation I have an .elf file. Now I have to convert this
elf file to a hex file which can be used as memory content for the
epcs controller RAM. I guess this should be done with the elf2hex
command.
Can anybody tell me which prms I have to use for the:
- elf2hex width
- elf2hex base
- elf2hex end
?

Thanks and best regards,
Karel


Article: 117658
Subject: Re: PCI FPGA Dev Board Suggestions
From: "John Adair" <g1@enterpoint.co.uk>
Date: 6 Apr 2007 01:08:42 -0700
Links: << >>  << T >>  << A >>
Kunal

I think if such a card does not exist today it probably won't. PCIE is
killing of PCI66 very rapidly although we do hear of other people,
usually Sun machine users, wanting PCI66 and we have considered doing
a PCI66 version of our Broaddown4 product. I would be interested to
hear from anyone else that thinks there is a market for this
interface, even niche smallish quantities, as we could deliver such a
product within a few weeks if a strong requirement exists.

Your next problem is getting a Virtex level product cheaply. Spartan
level products don't often support PCI66. Our base level version of
Broaddown4 does come just with your price target but at the moment is
the wrong interface with the PCIE.

Is this an academic application? If so some vendors like ourselves
have University discount schemes.

The PLX style approach isn't used by many FPGA development board
manufacturers as usually they are trying to demo PCI inside a FPGA. We
are doing an alternative to this in some planned products and you can
see the first implementation in our Trarfessock1 board that has a FPGA
for the PCI(Cardbus) interfaces and an independent one for the main
logic development. This allows a lot of flexability in how the card is
used.

John Adair
Enterpoint Ltd.

On 6 Apr, 02:01, "Kunal" <kunals.spam.acco...@gmail.com> wrote:
> I should also mention that we'd like to keep the cost under $2000, and
> emphasize that we are really trying to stay away from an embedded
> system (essentially outsourcing the PCI tasks to a PCI bridge chip).
>
>
>
> Kunal wrote:
> > I'm looking for the perfect FPGA dev board for a project I'm
> > contributing to. I've found one that is *almost* ideal, with the
> > drawback being lack of support for 66 MHz PCI bus rates, and an FPGA
> > that's too small:
> > The MESA 5120ds
> >http://www.mesanet.com/pdf/parallel/5i20ds.pdf
>
> > I was hoping the community would have some suggestions. Basically, we
> > need the FPGA for some high-speed custom data conditioning, and an
> > easy way to get the processed data onto a PC.
>
> > We'd like:
> > - A fairly large FPGA, preferably Xilinx (something as big as a Virtex-
> > II VP20 or VP30 chip)
> > - PCI capabilities at 66 MHz/32 bits
> > - (optionally) a PCI bridge chip to greatly simplify the FPGA logic
> > (that is, we'd only need to deal with simple handshaking, rather than
> > using a PCI core and having to create an embedded system)
> > - Failing the last requirement, the FPGA should be able to handle the
> > Xilinx LogiCORE PCI IP
> > - 20-30 LVDS pairs through general I/O
> > - software examples with source code
> > - working drivers (for either Windows or Linux)
>
> > We'd like this for a high-speed custom DAQ system we're making.
>
> > Thanks in advance!- Hide quoted text -
>
> - Show quoted text -



Article: 117659
Subject: Re: PCI FPGA Dev Board Suggestions
From: "evilkidder@googlemail.com" <evilkidder@googlemail.com>
Date: 6 Apr 2007 02:27:17 -0700
Links: << >>  << T >>  << A >>
On Apr 6, 1:57 am, "Kunal" <kunals.spam.acco...@gmail.com> wrote:
> I'm looking for the perfect FPGA dev board for a project I'm
> contributing to. I've found one that is *almost* ideal, with the
> drawback being lack of support for 66 MHz PCI bus rates, and an FPGA
> that's too small:
> The MESA 5120dshttp://www.mesanet.com/pdf/parallel/5i20ds.pdf
>
> I was hoping the community would have some suggestions. Basically, we
> need the FPGA for some high-speed custom data conditioning, and an
> easy way to get the processed data onto a PC.
>
> We'd like:
> - A fairly large FPGA, preferably Xilinx (something as big as a Virtex-
> II VP20 or VP30 chip)
> - PCI capabilities at 66 MHz/32 bits
> - (optionally) a PCI bridge chip to greatly simplify the FPGA logic
> (that is, we'd only need to deal with simple handshaking, rather than
> using a PCI core and having to create an embedded system)
> - Failing the last requirement, the FPGA should be able to handle the
> Xilinx LogiCORE PCI IP
> - 20-30 LVDS pairs through general I/O
> - software examples with source code
> - working drivers (for either Windows or Linux)
>
> We'd like this for a high-speed custom DAQ system we're making.
>
> Thanks in advance!


Hi,

These chaps might have someting suitable:

http://www.alpha-data.co.uk/

Cheers,

Andy


Article: 117660
Subject: Re: Spartan-3A XC3S1400A development board?
From: Ron <News5@spamex.com>
Date: Fri, 06 Apr 2007 04:01:01 -0800
Links: << >>  << T >>  << A >>
Tommy Thorn wrote:
> Make sure you don't depend on the ISE WebPACK tool chain. It doesn't
> support the larger Spartans.
> 
> FYI, Altera's $150 Cyclone III starter kit has a EP3C25 with 66
> multipliers and it is supported by the gratis Quartus II web edition.

Wow, thanks for the tip Tommy! I just put an Altera Cyclone III Starter
kit on order (it's on backorder for about a month). It's so much easier
when I can order right on the manufacturer's website instead of having
to go find a local vendor. I'm very glad I inquired about this here, and
am very grateful for your answer.

Best wishes,

Ron

Article: 117661
Subject: Re: OT Re: Gray code in asynchronous FIFO design.
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 6 Apr 2007 13:25:40 +0100
Links: << >>  << T >>  << A >>
"Nicolas Matringe" <nicolas.matringe@fre.fre> wrote in message 
news:461549a6$0$28810$426a74cc@news.free.fr...
> Symon a écrit :
>
>> For example, a brother and sister were born on the same day a few minutes 
>> apart. But they're not twins. How?
>
> Hasn't this something to do with a boat crossing the date change line ? I 
> seem to recall something like that ...
>
> Nicolas

Hi Nicolas,
I like your thinking, but that only gives you a day maximum. Hard to 
conceive and gestate a baby in 24 hours, I think?! :-)
Anyway, it's much simpler than that. There's another sibling. So, not twins. 
Triplets!
Sometimes it's safer to post this online than IRL!!
Cheers, Syms.
p.s. The guy who married his own daughter? He's a vicar! Happy Easter all! 



Article: 117662
Subject: Re: virtex 4vfx12 evaluation kit schematics
From: "cpope" <cepope@nc.rr.com>
Date: Fri, 6 Apr 2007 08:36:51 -0400
Links: << >>  << T >>  << A >>
http://www.em.avnet.com/evk/home/0,1719,RID%253D%2526CID%253D25726%2526CCD%253DUSA%2526SID%253D32214%2526DID%253DDF2%2526SRT%253D1%2526LID%253D32232%2526PRT%253D0%2526PVW%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html

<ashasravanthi@gmail.com> wrote in message
news:1175840138.136251.72030@e65g2000hsc.googlegroups.com...
> hi,
>      can any please tell me where i can get virtex 4vfx12 evaluation
> kit schematics.
>
>
> thanks
> asha.
>



Article: 117663
Subject: Icarus Verilog
From: Eli Hughes <emh203@psu.edu>
Date: Fri, 06 Apr 2007 08:42:31 -0400
Links: << >>  << T >>  << A >>
I just wanted to get a heads up from anyone out there about this tool. 
My initial results (for some trivial designs) were pretty good with the 
synthesizer

Has anyone used this for any large synthesis tasks?  Any general 
comments about usability?  Has anyone used this tool in a full design flow?

Thanks,
Eli

Article: 117664
Subject: Re: OT Re: Gray code in asynchronous FIFO design.
From: "KJ" <Kevin.Jennings@Unisys.com>
Date: 6 Apr 2007 07:18:11 -0700
Links: << >>  << T >>  << A >>
On Apr 6, 8:25 am, "Symon" <symon_bre...@hotmail.com> wrote:
> "Nicolas Matringe" <nicolas.matri...@fre.fre> wrote in message
>
> news:461549a6$0$28810$426a74cc@news.free.fr...
>
> > Symon a =E9crit :
>
> >> For example, a brother and sister were born on the same day a few minu=
tes
> >> apart. But they're not twins. How?
>
> > Hasn't this something to do with a boat crossing the date change line ?=
 I
> > seem to recall something like that ...
>
> > Nicolas
>
> Hi Nicolas,
> I like your thinking, but that only gives you a day maximum. Hard to
> conceive and gestate a baby in 24 hours, I think?! :-)
> Anyway, it's much simpler than that. There's another sibling. So, not twi=
ns.
> Triplets!
> Sometimes it's safer to post this online than IRL!!
> Cheers, Syms.
> p.s. The guy who married his own daughter? He's a vicar! Happy Easter all!

Triplets (or more) is a solution, but an even more common one is that
they are simply born from different mothers who have previously had
another child.  The statement was just that "a brother and sister were
born..." there is nothing saying that the 'brother' is the brother of
the 'sister' that was born (and vice versa), just that they are a
'brother' and a 'sister'.

This situation happens every day in every maternity ward in every
major hospital (i.e. one with more than a couple mothers in labor on a
given day), whereas the multiple births are not nearly as common.

KJ


Article: 117665
Subject: Re: Looking for Memory Recommendation for Spartan 3E 1200
From: "Paul" <pauljbennett@gmail.com>
Date: 6 Apr 2007 07:20:09 -0700
Links: << >>  << T >>  << A >>
Any Dynamic RAM interface is going to be tricky because of opening and
close rows, refresh cycles,
etc.. etc....

No matter what you do, you're going to have to dive deep into the code
to get it working,
even if you get a canned interface.

Use a simple synchronous SRAM... it will probably interface with very
little
logic aside from the I/O ports of the microblaze.


You say "fast enough to let the microblaze run at a decent speed".
Presumably,
you're not storing and retreiving data any faster than the sample
rate, no? So even if your
processing has to run faster - just throw a fifo into your memory
interface to buffer the
memory from your processor.  So your processor can drop data in the
fifo, move on and do
other things, while the interface puts the data in memory at whatever
speed it runs, even if that's
not the 100mhz or whatever you wanna run your processor at.

On Apr 3, 5:03 pm, Matthias Einwag <matthias.ein...@web.de> wrote:
> Hi everyone,
>
> I'm working on a Board for Bus Interfacing and some Audio Processing,
> which will use Spartan 3E 1200 and the Microblaze.
> Now I'm not sure what kind of memory I should use. Size ist not too
> important for me. 8Mbytes would be ok, but more is always better. But
> the speed should be high enough to get the Microblaze run at a decent
> speed and to allow permanent storing auf 4 stereo audio streams.
> Most important is, that the layout and memory interface should run
> stable and from the beginning. There's not much time for error
> investigations and redesigns.
>
> Spartan 3E Starter Kit uses a 16bit Wide DDR SDRAM Memory. But I read
> here and in some other boards, that people have much trouble with this
> one. Is this because Spartan 3E and the given IP Cores have always
> Trouble with DDR, or because of the missing clock feedback path on the
> board?
>
> Another option would be normal SDRAM Memory. I think this should give
> less trouble. But here I'm wondering that Xilinx doesn't mention the
> Spartan 3E in the Device Family Support List of the OPB SDRAM Controller
> and the MultiChannel OPB SDRAM Controller. Only Spartan 3 and 3A are
> supported according to the Links on this page:http://www.xilinx.com/ise/embedded/edk_ip.htm
> In fact the Spartan 3E is only listed in the support list for the OPB
> DDR SDRAM Controller. Are there mistakes in this list, or is spartan 3e
> really not supported by most memory controllers?
>
> Greetings
> Matthias



Article: 117666
Subject: Re: Transition from ASIC to FPGA
From: Austin Lesea <austin@xilinx.com>
Date: Fri, 06 Apr 2007 07:32:52 -0700
Links: << >>  << T >>  << A >>
ASIC_2_FPGA,

If you have been designing your ASIC by writing a HDL, like VHDL, or
verilog, then there is little you need to change.

Generally, a hardware description language is intended to abstract the
hardware to make the process easier.

However, just as a good ASIC engineer will optimize their code to
synthesize efficiently into a standard cell library, so a good FPGA
engineer will recognize that some constructs are not efficient for the
FPGA resources, and try to modify the coding style (usually by guessing,
changing, and checking -- or by asking others about specific coding
styles, or reading the application notes, and examining code written by
others).

Generally, since one stage of logic in the FPGA has a lot more
functionality than one stage in an ASIC, people try to code such that
they have few levels of logic between the registers so that they meet
their speed requirements.

Constraints in synthesis is always a challenge, so when you get your
code functionally correct, then apply as few as possible constraints to
get your timing met.  The more constraints you add that do not improve
the timing, the worse the result will be in general.  Take out any
constraints that are not doing what was intended, and try another
constraint.

If you were used to short delays, and very fast clocks in the ASIC, you
will need to realize that due to the large size of the FPGA, the delays
are generally all larger, and clock speed is less (550 MHz in the
fastest V5 speed grade).


If you were designing custom ASIC, then conversion will be a real
challenge, as hardly anyone uses the schematic flow for FPGA any longer
(some of us are old enough to remember it).

Choicer of tools, features, options, etc. are all important.  For
example, if you had been using Synopsis DC, then redirecting it to
synthesize FPGA logic is as simple as a click on a box.

Austin

Article: 117667
Subject: Re: Transition from ASIC to FPGA
From: "From_ASIC_2_FPGA" <praneet.dixit@gmail.com>
Date: 6 Apr 2007 08:50:16 -0700
Links: << >>  << T >>  << A >>
On Apr 6, 7:32 am, Austin Lesea <aus...@xilinx.com> wrote:
> ASIC_2_FPGA,
>
> If you have been designing your ASIC by writing a HDL, like VHDL, or
> verilog, then there is little you need to change.
>
> Generally, a hardware description language is intended to abstract the
> hardware to make the process easier.
>
> However, just as a good ASIC engineer will optimize their code to
> synthesize efficiently into a standard cell library, so a good FPGA
> engineer will recognize that some constructs are not efficient for the
> FPGA resources, and try to modify the coding style (usually by guessing,
> changing, and checking -- or by asking others about specific coding
> styles, or reading the application notes, and examining code written by
> others).
>
> Generally, since one stage of logic in the FPGA has a lot more
> functionality than one stage in an ASIC, people try to code such that
> they have few levels of logic between the registers so that they meet
> their speed requirements.
>
> Constraints in synthesis is always a challenge, so when you get your
> code functionally correct, then apply as few as possible constraints to
> get your timing met.  The more constraints you add that do not improve
> the timing, the worse the result will be in general.  Take out any
> constraints that are not doing what was intended, and try another
> constraint.
>
> If you were used to short delays, and very fast clocks in the ASIC, you
> will need to realize that due to the large size of the FPGA, the delays
> are generally all larger, and clock speed is less (550 MHz in the
> fastest V5 speed grade).
>
> If you were designing custom ASIC, then conversion will be a real
> challenge, as hardly anyone uses the schematic flow for FPGA any longer
> (some of us are old enough to remember it).
>
> Choicer of tools, features, options, etc. are all important.  For
> example, if you had been using Synopsis DC, then redirecting it to
> synthesize FPGA logic is as simple as a click on a box.
>
> Austin

Hi Austin,

I've been using Verilog HDL, so I have no issues as far as RTL coding
or Verification is concerned.
I am more concerned about the rest of things like the synthesis,P&R.
As you pointed out , application of constraints for synthesis,
selecting the speed grade etc..

I'd like to in general if a beginner is asked to work on FPGA, how
would he be guided..

Thanks.
Thanks fr your response.


Article: 117668
Subject: Re: Transition from ASIC to FPGA
From: "Jan Gray" <jsgray@acm.org>
Date: Fri, 06 Apr 2007 15:56:41 GMT
Links: << >>  << T >>  << A >>
Excellent advice from Austin Lesea.  You may also enjoy 'The Art of High 
Performance FPGA Design' [ http://www.fpgacpu.org/log/aug02.html#art ] 
although this is not necessarily the best methodology if good enough is good 
enough.  And you may draw some inspiration from this gallery: 
http://andraka.com/gallery.htm .

Jan Gray



Article: 117669
Subject: Re: Transition from ASIC to FPGA
From: curiousjyo111@gmail.com
Date: 6 Apr 2007 09:15:38 -0700
Links: << >>  << T >>  << A >>
Hi Buddy ,

Just this link its very useful.
http://www.timelogic.com/technology_fpga.html


Advantages of FPGA-Based Accelerators vs. ASICs

DeCypher's use of FPGA based logic permits our design staff to avoid
the risks and tradeoffs encountered in ASIC design. Since FPGAs can be
rewired "on-the-fly" during in-field use, each algorithm is
implemented as a separate "logic configuration file". Each algorithm
can run in a single clock cycle (two in some case) at very high speed
because each is separately optimized without on-chip constraints
imposed by any other algorithm. We control the chip clockrate
according to the performance obtainable with each algorithm,
independent of any other algorithm.  Similarly, the entire on-chip
logical resources of the FPGA can be devoted to maximizing the packing
density of a particular algorithm's processing cell independent of
other algorithms'. FPGAs do not force a rigid predefined limit on the
number of cells per chip.

Switching FPGA wiring between algorithms is brief, and is transparent
to the user. Each algorithm's "logic cell" (also called a "processing
element" or PE) is as small as possible, maximizing the opportunity
for on-chip parallelism. And, new unanticipated algorithms may be
easily added to DeCypher by distribution of new data files, as simply
as a software update is installed on a conventional computer. In
short, FPGAs permit the system designer to dodge the early design
tradeoffs associated with fully custom chips. It is not necessary to
predict (at significant risk of error) the course of the
bioinformatics state-of-the-art early in the product life cycle.





With Regards,

Sparkle




Article: 117670
Subject: Re: Transition from ASIC to FPGA
From: curiousjyo111@gmail.com
Date: 6 Apr 2007 09:23:59 -0700
Links: << >>  << T >>  << A >>
Hi ,

Really nice information provided by Austin.

Just check this link for more info.
http://www.timelogic.com/technology_fpga.html


With Regards,


Sparkle



Article: 117671
Subject: XUP virtex-II pro
From: "woutervh" <wouter.vanhauwaert@gmail.com>
Date: 6 Apr 2007 10:05:55 -0700
Links: << >>  << T >>  << A >>
Hello

I developed a hardware component in ISE which interfaces with my own-
made print-circuit by using the lower middle expansion header (just
for information).
Now I want to couple this hardware component to an OPB-bus, so I can
use it in EDK.
I don't think it's very difficult, but need something to start with.

I already discovered that I have to use the "import custom
peripheral".
As I see, the OPB-bus needs several ports (OPB_CLK, OPB_ABus, OPB_BE,
OPB_DBUS, ...)

But my hardware component has only one clocksource (which I made
through a DCM-module in ISE) and 10 Datalines which are captured on
each clock-edge. Now I don't really now how I have to implement the
OPB-bus with this component...

I suppose I have to rename my datalines to OPB_DBUS(0:9) but I'm not
sure of the rest...

grtz,
Wouter


Article: 117672
Subject: How to use the 8LEDs on DIO4 when connected to Virtex 2 Pro kit?
From: "Krishna" <chai2m@gmail.com>
Date: 6 Apr 2007 11:00:42 -0700
Links: << >>  << T >>  << A >>
Hello,

I am trying to implement an 8 bit adder program using VHDL on Virtex 2
pro with expansion kit DIO4 from digilent.

The code is correct and I can see the result on 4 LEDs of Virtex 2 pro
kit from Digilent. But when trying with LEDs on DIO4 kit, I could not
see any result. I gave the direct pin connections both for switches
and LEDs. The switches are working fine but not the LEDs. In the
reference manual,  I observed that there is latch between LEDs and
connector P1. But I dont know how to use latch for this program.

Can any one guide me how to solve this problem?

http://www.digilentinc.com/Data/Products/DIO4/DIO4_rm.pdf. This is the
reference manual for DIO4 kit.

Thanks in advance.

Krishna


Article: 117673
Subject: Re: Transition from ASIC to FPGA
From: Ben Twijnstra <ben.twijnstra@gmail.com>
Date: Fri, 06 Apr 2007 20:22:27 +0200
Links: << >>  << T >>  << A >>
Hi ASIC_2_FPGA,

> I've been using Verilog HDL, so I have no issues as far as RTL coding
> or Verification is concerned.

With respect to coding style I have a few strong suggestions:

(apologies in advance for shouting)

- DON'T DO CLOCK GATING
- DON'T DO RIPPLE CLOCKS
- REGISTERS ARE FREE
- CLOCK-ENABLES ARE FREE

> I am more concerned about the rest of things like the synthesis,P&R.
> As you pointed out , application of constraints for synthesis,

With Altera's Quartus II toolchain you'll be happy to see that it fully
supports SDC constraints, floorplanning, ECO without doing a full P&R, full
TCL scripting, either from command line or GUI, incremental compilation and
other comfort-enhancing features.

The Xilinx toolchain does pretty much all of the above, except that it
doesn't support SDC but uses its own proprietary format for setting timing
constraints, and as far as I know does not support scripting.

No clock tree synthesis is required for FPGA's. Everything's pre-buffered.

Both toolchains are available on Windows, Linux and Solaris.

> selecting the speed grade etc..

Today's FPGA's are pretty good in terms of performance (but never good
enough), so normally you start coding for the slowest speed grade, and only
once you find out that after careful tweaking of your logic and placement
you cannot meet timing you will switch to a faster speed grade.

Also, you will find that you will not need to simulate as much as you used
to do. Run into a bug? Find it through JTAG, fix it, shoot a new bitstream
into the device, and try again.

Hope this helps,


Ben


Article: 117674
Subject: Re: How to use the 8LEDs on DIO4 when connected to Virtex 2 Pro kit?
From: Mike Treseler <mike_treseler@comcast.net>
Date: Fri, 06 Apr 2007 11:30:15 -0700
Links: << >>  << T >>  << A >>
Krishna wrote:

> and LEDs. The switches are working fine but not the LEDs. In the
> reference manual,  I observed that there is latch between LEDs and
> connector P1. 

See page 4
"If the system bus is not needed, then the LDG signal
can be tied high."



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