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fpga_toys@yahoo.com wrote: > On May 11, 4:56 pm, Peter Alfke <p...@xilinx.com> wrote: >> My nasty response had nothing to do with Xilinx policy, or to our >> attitude to customers large or small. People that know me appreciate > > Your nasty reponse was not necessary, correct, or even justified. > > If you can not take it in return, then stop trashing powerless newbie > students just because you can. > > John Seeing people post something like "Urgent: need help" to ask how to code some very vaguely defined things ranging from 2:1 muxes to stuff that sound nearly as complex as a flight controller is quite annoying - it makes it look like the "powerless newbie" is asking for help before even trying to understand the issue at hand. Back when I was a lab tutor (introductory digital design classes - most students did not know what CPLDs, FPGAs and VHDL were on the first day), I would tell students that came up with such vague questions to ask again after they could reformulate their questions in a way that would clearly show they at least tried to understand the problem instead of letting them pull solutions out of me one vaguely defined bit at a time - at the very least, I wanted them to learn how to ask proper questions. Newbieness is not an excuse for not showing any apparent effort before asking questions.Article: 119126
Has anyone measured the cycles needed for a PowerPC to output data in a GPIO port? I am using a Virtex-II Pro device and plb_GPIO peripheral, and I measure ~100 cycles.Article: 119127
Leon, It is good that you have all your estimates, and are looking at it carefully. All too often, the power supply is left for last. Depending on how much risk you wish to take, and how sensitive to cost you are, and any reliability guidelines, you will see people providing exactly what they need (no margin), to a margin of 100% (supply is twice the power required). For example, the latest Dell desktop machine I bought has "just enough" for the peripherals in it. Adding a HDI video card will require that I pull the power supply, and get a larger one. This is a real pain, as I bought the system thinking I already had the whiz-bang super digital video card in it, but I must not have clicked the right button when I configured it. Basically, Dell provides just enough to power what I ordered. Another example, in telecom wired and wireless equipment, the power supply is usually able to deliver twice what is needed. From a reliability point of view, such a supply is unlikely to ever fail, as it is always operating far below its rating, resulting in less heat (which is the enemy of reliability). So, there you go: from 1.0 to 2.0 of the required power is used based on what you are doing, and who your customer is. As to the accuracy of the prediction, be prepared to increase your power supply capability: it is hard do an accurate estimation unless you know - all of the logic states (you have a "real" set of test benches to run through the more capable software tools --- not just a spreadsheet which is only as good as your guesses as to what you are doing), and the worst case silicon numbers have been characterized (the chip you have now may not be the same as the one you get next week). AustinArticle: 119128
On 12 mai, 17:20, "Daniel S." <digitalmastrmind_no_s...@hotmail.com> wrote: > fpga_t...@yahoo.com wrote: > > On May 11, 4:56 pm, Peter Alfke <p...@xilinx.com> wrote: > >> My nasty response had nothing to do with Xilinx policy, or to our > >> attitude to customers large or small. People that know me appreciate > > > Your nasty reponse was not necessary, correct, or even justified. > > > If you can not take it in return, then stop trashing powerless newbie > > students just because you can. > > > John > > Seeing people post something like "Urgent: need help" to ask how to code > some very vaguely defined things ranging from 2:1 muxes to stuff that sound > nearly as complex as a flight controller is quite annoying - it makes it > look like the "powerless newbie" is asking for help before even trying to > understand the issue at hand. > > Back when I was a lab tutor (introductory digital design classes - most > students did not know what CPLDs, FPGAs and VHDL were on the first day), I > would tell students that came up with such vague questions to ask again > after they could reformulate their questions in a way that would clearly > show they at least tried to understand the problem instead of letting them > pull solutions out of me one vaguely defined bit at a time - at the very > least, I wanted them to learn how to ask proper questions. > > Newbieness is not an excuse for not showing any apparent effort before > asking questions. first of all , i apreciate your advices secondly i want tell you that i m alone for develpment using the hardware programming that it is why i cant get the right ideas and that it is why i m asking professionals to give me some help to get it more and more better thank youArticle: 119129
On May 12, 9:20 am, "Daniel S." <digitalmastrmind_no_s...@hotmail.com> wrote: > Newbieness is not an excuse for not showing any apparent effort before > asking questions. Granted ... nor is there any excuse being openly disrespectful in a reply to them. Just ignore them, or give a polite reply. It's popular to excuse Peter's abuses because he does often provide useful information, which just brings the forum down. Either it's ok for Peter, Austin, and every other poster to be openly disrespectful in the forum, or no one. It's total BS to say the good guys have no bounds, and expect everyone else to be nice.Article: 119130
kha_vhdl wrote: > > first of all , > i apreciate your advices secondly i want tell you that i m alone for > develpment using the hardware programming that it is why i cant get > the right ideas and that it is why i m asking professionals to give me > some help to get it more and more better > thank you And yet you still haven't restated your question in a manner that can be answered. You want an "ideal" FPGA to perform video compression. The only way anyone can help is to understand what's important to you for this project. 1) Is the algorithm designed or net yet figured out? 2) Is cost more important than capability? 3) Is real-time compression a necessity or can you take a few hours? 4) Are you performing DSP-intensive applications? - Do you know the DSP capabilities of any FPGA - Do you know the DSP capabilities of leading-edge FPGAs? 5) Do you intend to use significant amounts of on-chip memory? 6) Can you supply any power needed by your design or are you limited? 7) Are you looking to design your own board or do you need a demo board? 8) Does your solution have to be compact or can you use multiple FPGAs? 9) How do you intend to interface to your system? PCIe? Ethernet? USB? Power. Connectivity. Capability. You've communicated nothing yet about what your needs are. All we know is that you want to "compress video." Why use an FPGA at all? Your PC is perfectly capable. Don't simply defend your "simple" question. Ask something that can get an answer.Article: 119131
On May 12, 3:43 am, Robert Ganter <hb9...@gmx.net> wrote: > fpga_t...@yahoo.com wrote on 12.05.2007 08:51: > > Frankly, as a key > > Xilinx asset on this list, Xilinx cann't help but drive business to > > Altera with Peter's insults ... or drive readership from this list. > > How many posters will AVOID this list at all costs rather than catch > > Peter in a foul abusive mood? > > Also frankly, this is ridiculous. I never saw an insulting answer from > Peter (actually from noone here) to reasonably formulated questions for > a well defined problem. It is this "make solution" attitude which pisses > everybody off who tries to share his experience with others. This is not the first time, or the last, that I will call Peter (and Austin, which is why he joined in they way he did) to task for being insulting, to even valid questions and others responses. Check a ways back, and you will find me objecting to Peter 's rude slaming a poster for using some chat/texting short hand. You will also find them rudely slamming me for bringing up power instability in early BG560 product. Check even further back an you will find many warnings to play nice in relatively polite responses to their abuse. Their management told me that was unacceptable, and would not happen again. Yet it appears to continue, and they seem unconstrained at all, from their replies. Seems we need quite a bit more scorched earth ridicule from both sides before Xilinx managment will get a clue this not acceptable. Austin was copied on those emails, and clearly knows why I complained then, and now. His cute little attempt to deflect it claiming ignorance was a joke, or his memory is fading fast ... as that was only last August.Article: 119132
On May 12, 10:11 am, kha_vhdl <abai...@gmail.com> wrote: > first of all , > i apreciate your advices secondly i want tell you that i m alone for > develpment using the hardware programming that it is why i cant get > the right ideas and that it is why i m asking professionals to give me > some help to get it more and more better > thank you If this is the first time you have considered an FPGA based design, you probably need to pickup a low cost development board and go through the exercise of implementing first some simple designs, then make a stab at your project requirements. Consider using training resources that are online, available in free or low cost vendor work shops, returning back to school taking some continuing education classes, or hire a consultant to help you up to speed. Your local FAE can help with this to some degree, largely depending on your product volume. You will find a number of very useful sample designs in the application notes, which can be used as reference points in developing your own design. Pickup a development board and software, and have fun! JohnArticle: 119133
On Sat, 12 May 2007 09:14:29 -0700, fpga_toys wrote: > On May 12, 9:20 am, "Daniel S." <digitalmastrmind_no_s...@hotmail.com> > wrote: >> Newbieness is not an excuse for not showing any apparent effort before >> asking questions. > > Granted ... nor is there any excuse being openly disrespectful in a > reply to them. Just ignore them, > or give a polite reply. Absolutely, well said. It is quite simply bad manners, but some people are like that on occasion, (when most of the time they aren't). Maybe they were are already having a bad day!! Or maybe they just have bad manners full stop - you can tell those types because once they have had a rush of blood and have been disrespectful to someone, they don't apologise. But hey ho, it takes all sorts to make the world go around ;-) I remember how an engineer spoke to me about a circuit that I had designed - I walked up to him as he was sitting at his desk and asked him to have a look at my circuit, and I was gobsmacked, his response was "WHAT THE F*CK IS THAT!", in a vexed, raised voice, all over our office. Priceless!!!!! He didn't apologise although the next day he did say very sheepishly that he may need to use a circuit like that in his design. The bit of electronics he was referring to was only a few gates. I added them so that a bus the board was designed to connect to would continue to work if power went down on my card - which was was desirable, although he hadn't spotted that when he first looked at my circuit (a card he was designing didn't do that, although his also had to be put onto this bus). After that episode I basically considered him as a t*sser, but in actual fact, he just had bad social skills and a bit of an ego - a deadly combination that does seem to afflict the 'odd' technical person ;-) Regards, Paul.Article: 119134
kha_vhdl wrote: > i want to implement a vhdl program into an fpga support ( the program > is compressing video ), > i want know what are the basics that i should know to choose the > perfect fpga( for example Sparta,3 or Virtex 4 into Xlinx) and thank > you for your answer I suggest that you first skim the book "Digital Video Demystified" from Keith Jack (http://www.amazon.com/Video-Demystified-Keith-Jack/dp/187870723X) and then think through what your algorithm should be, how much memory it will need etc., and once you have a rough idea of these parameters you should come back to this group. Best regards, BenArticle: 119135
austin wrote: > Leon, > > It is good that you have all your estimates, and are looking at it > carefully. All too often, the power supply is left for last. > > Depending on how much risk you wish to take, and how sensitive to cost > you are, and any reliability guidelines, you will see people providing > exactly what they need (no margin), to a margin of 100% (supply is twice > the power required). ... > As to the accuracy of the prediction, be prepared to increase your power > supply capability: it is hard do an accurate estimation unless you know > - all of the logic states (you have a "real" set of test benches to run > through the more capable software tools --- not just a spreadsheet which > is only as good as your guesses as to what you are doing), and the worst > case silicon numbers have been characterized (the chip you have now may > not be the same as the one you get next week). Also note that doubling the maximum performance of the power supply usually costs about less than 50% extra. It's worth it to have an overdimensioned power supply. 200% may be a bit far on the safe side, but it really doesn't hurt that much financially. Best regards, BenArticle: 119136
Eric Smith wrote: > I asked about driving a 3.3V FPGA input (e.g., Spartan-3) from > a 74LS14 TTL output. > > Peter Alfke wrote: > >>Pick 300 to 1000 Ohm, any value will be ok. Consider the input a 10 pF >>load and put the resistor close to it.. Then 1kilohm means a 10 ns >>time constant... > > > I have found that I can get 74LVC244AD 3.3V octal buffers with 5V-tolerant > inputs and 6 ns max prop. delay for less than the cost of 330 ohm 16-pin > SMT resistor networks! > > part Digikey quantity 100 price > > NXP 74LVC244AD $0.26 > Bourns 4816P-T01-331LF $0.71 > CTS 767-163-R330P $0.37 (not stocked) > > Amazing. I guess those bleeding-edge fabs they use to make resistor > networks must be really expensive! Maybe they could lower the cost > by outsourcing production to TSMC :-) 16 pin SMT networks are dinosaur part, so that's no real surprise. A better choice are the 1206 4 Element ones - much lower price and less PCB area - so no one uses the Bourns ones anymore. On a similar front, I noticed SiliconPOTs are getting better all the time, and one recent one had very good ppm matching and drift specs, and looking to be cheaper than alternate fixed-value precision resistors. -jgArticle: 119137
hi everybody, I'm using plb_tft_cntlr_ref IP in EDK8.1 project, based on XUP Vertex2Pro Development Board, now having some troubles. I have created a project and added the plb_tft_cntlr_ref to it using the Base System Builder wizard. Finally I added a DCR bus and connect the IP to it fllowing the user guide. The result is, a test image can be show correctly in a TFT LCD after power on or re-download the jtag file. But when I reset the processor(hardware reset or soft reset in XMD), the image changes , it does not start with the top of the screen anymore. It seems that the image starts with a random screen line ofter reset. I have checked the registers and signal connections, but could't find anything. How to resolve this problem? Thanks a lot. Regards, Yi YANGArticle: 119138
"Peter Alfke" <peter@xilinx.com> wrote in message news:1178924195.521153.186290@y80g2000hsf.googlegroups.com... > My nasty response had nothing to do with Xilinx policy, or to our > attitude to customers large or small. People that know me appreciate > that I love to help with either tutorial or also very specific > explanations. And I'm sure that most in the group do appreciate your 2 cents....and even the tone of your reply on most occasions as well. > But it irks me when a few students abuse this newsgroup by typing ill- > defined questions that obviously cannot be answered directly. Don't let it irk you then, let it go. > And it irks me double when the same student does it again. Then try twice as hard to not let it irk you....since you had no answer (due to the lack of an answerable question) you could have chosen to ignore the posting and let someone else field it if they so chose. > This is a high-powered newsgroup where experienced engineers try to > give helpful answers. This forum should not be abused by really dumb > questions. This is an unmoderated newsgroup open to all. > Even a student must know that parameters like frequency, data width, > standard etc are crucial, and should be included in the question. Depends on how much the student actually knows. > Don't be shy, but be specific ! > That was the reason for my outburst... But again, as has been stated before, there is generally no excuse for 'outburts' and 'nasty responses'. If there is no question asked, then get over the urge to reply to the post and you may get over the 'irks'. But again to reiterate what I said at the start, in general your posts to the group are usually solid, useful and not nasty. KJArticle: 119139
Thank you both, Austin and Ben! That's very helpful.
Actually the FPGA power consumption in the table above derived from
PowerPlay Power Analyzer(a function of Quartus II).
Someone told me that a margin of only 10% is need. But I think a
design with so small margin must base on very accurate power consumption
estimate. So it's better for me to provide a larger margin.
But now my main problem is how much power the non-IC components, such
as resistors and leds on board, will consume or usually how much for the
board like I am design. Maybe I could give a rough estimate, but i still
need some empirical advice.
Leon
Article: 119140Hi, I vaguely seem to remember a provision on the use of downto in EDK. I tried to dig this out before posting this with no luck---Can't remember where I came across this though I tried a couple of keyword searches in random EDK pdf docs. Kinda doubtful about something I've just written in EDK using many downto's. Would appreciate a hint on this. BTW, is Xilinx planning any short-term remedy for this? Keeping track of minor details is a bit daunting especially when you'r supposed to do loads of things from electronic circuitry design, DSP algorithmic development, to VHDL coding---You know academia! Regards, -MannyArticle: 119141
Manny <mloulah@hotmail.com> writes: > I vaguely seem to remember a provision on the use of downto in EDK. I haven't seen anything documented, but since Microblaze and PPC use big-endian bit-numbering (bit 0 is MSB), the interfaces are normally written using 0 to n-1 rather than n-1 downto 0. This caused me a fair bit of grief on my first home-grown EDK peripheral module. If I'm not mistaken, VHDL vector port associations and signal assignments occur in left-to right order when not explicitly stated otherwise. You can attach a 0 to 31 port on an EDK component to a 31 downto 0 port on a non-EDK component, and it will match 0 to 31, 1 to 30, etc. If you're coding something specifically for use with the EDK, it's probably best to use the big-endian bit numbering to avoid unnecessary confusion.Article: 119142
On Apr 17, 7:43 pm, John McCaskill <junkm...@fastertechnology.com> wrote: > On Apr 17, 3:27 am, Allen <lphp...@gmail.com> wrote: > > > > > > > On Apr 17, 11:23 am, John McCaskill <junkm...@fastertechnology.com> > > wrote: > > > > On Apr 11, 2:12 am, "Allen" <lphp...@gmail.com> wrote: > > > > > On Mar 29, 10:52 pm, "John McCaskill" <junkm...@fastertechnology.co= m> > > > > wrote: > > > > > > On Mar 29, 12:45 am, "Allen" <lphp...@gmail.com> wrote: > > > > > > > On Mar 25, 8:39 pm, "John McCaskill" <junkm...@fastertechnology= .com> > > > > > > wrote: > > > > > > > > On Mar 25, 12:32 am, "Allen" <lphp...@gmail.com> wrote: > > > > > > > > > On Mar 23, 8:33 pm, Zara <me_z...@dea.spamcon.org> wrote: > > > > > > > > > > On 23 Mar 2007 05:13:46 -0700, "Allen" <lphp...@gmail.com= > wrote: > > > > > > > > > > >hi all, > > > > > > > > > > >first, i am sorry for my poor English. > > > > > > > > > > >i use EDK 7.1i and ISE 7.1i. > > > > > > > > > > >imported custom peripheral with PLB Master Interface ( n= ot from IFIP ) > > > > > > > > > >into my .xps project after overcame several problems. > > > > > > > > > > >In the step " generate netlist " there has no error or w= arning. > > > > > > > > > > >but in the step "Generate Bitstream",i got a error messa= ge "ERROR!! > > > > > > > > > >NgdBuild:455 plb_M_ABUS<62> has multiple driver(s)": ret= urn code 2 > > > > > > > > > >abort. > > > > > > > > > > >already search this problem in xilix's answer database a= nd tried > > > > > > > > > >modify the parameter of C_BaseAddr, but it is still stuc= k here. > > > > > > > > > > >does anyone meet this problem before? > > > > > > > > > > >thanks in advance. > > > > > > > > > > I always got that messaghe when I had some signal with tw= o outputs > > > > > > > > > connected to it. That seems your case, in your plb addres= s bus, master > > > > > > > > > interface. > > > > > > > > > > Best regards, > > > > > > > > > > Zara- Hide quoted text - > > > > > > > > > > - Show quoted text - > > > > > > > > > Thanks for your reply. > > > > > > > > > so it might mean something wrong during import of custom pe= ripheral? > > > > > > > > > but in 64-bit PLB protocol, the address width is 32-bit. > > > > > > > > > i already use (C_PLB_AWIDTH-1) to replace with constant "31= " in my > > > > > > > > port declaration. > > > > > > > > > do anything i could try to solve this problem? > > > > > > > > > thank you :-) > > > > > > > > The PLB address width is 32 bits. However, the way that all = the bus > > > > > > > signals are connected to the PLB IP is that they are concaten= ated > > > > > > > together. So if you look at the MPD file for the PLB you will= see that > > > > > > > it defines the bus width to be 32 bits times the number of ma= sters: > > > > > > > > PORT M_ABus =3D M_ABus, DIR =3D I, VEC =3D [0: > > > > > > > (C_PLB_NUM_MASTERS*C_PLB_AWIDTH)-1] > > > > > > > > So the signal plb_M_ABUS<62> is bit 30 of the second master. = Look to > > > > > > > see if your core has been assigned the second master slot on = the PLB > > > > > > > bus. Assuming that is the case, find what two sources are dr= iving bit > > > > > > > 30 of the address. > > > > > > > > Assuming that you left the name of your EDK project as system= .xmp, > > > > > > > when you tell EDK to generate a netlist it will create a top = level hdl > > > > > > > file named either system.vhd or system.v depending on your to= ol > > > > > > > settings. You can look at this file to see how EDK has conne= cted the > > > > > > > cores to the PLB. > > > > > > > > It has been a while since I had to find a multi source signal= , but I > > > > > > > think that XST will produce a warning about it in its report = and tell > > > > > > > you what the multiple soures are. Look in the synthesis repor= t file > > > > > > > for the appropriate core and see if it tells you what the sou= rce of > > > > > > > the problem is. > > > > > > > > Since you are creating your own interface design instead of u= sing the > > > > > > > IPIF, are you using the bus functional models in your simulat= ions? I > > > > > > > use these, and they make the job much easier. I think it was= not > > > > > > > until EDK 8.1 that they were integrated into EDK itself, but = I was > > > > > > > able to use the CoreConnect tool kit directly from IBM in som= e of our > > > > > > > early stuff. The bus monitors will tell you as soon as your = core has > > > > > > > done something wrong, so you do not have to track the source = of the > > > > > > > problem back from when the symptoms show up. > > > > > > > > Regards, > > > > > > > > John McCaskillwww.fastertechnology.com-Hidequotedtext- > > > > > > > > - Show quoted text - > > > > > > > Thanks for your reply. :-) > > > > > > > Where i could see the second master is who( power pc or custom > > > > > > peripheral ... etc)? > > > > > > I don't know where to check this. > > > > > > While there may be an easier way, you can just look at a PLB mast= er > > > > > signal that is not a vector. For example, if you look at plb_M_R= NW in > > > > > your system.vhd you will see that it is defined as: > > > > > > signal plb_M_RNW : std_logic_vector(0 to 2) > > > > > > The entire vector is an input to the plb_wrapper. plb_M_RNW(0) wi= ll go > > > > > to PLB master 0, plb_M_RNW(1) will go to PLB master 1, etc. > > > > > > > I opened the system.vhd to see who connect to the plb_M_Abus. > > > > > > "PowerPC" have 2 ports and Custom peripheral has 1 port connect= to the > > > > > > plb_M_ABus. > > > > > > Next step, I am going to find the XST report file to see who dr= ive the > > > > > > plb_M_ABUS<62>. > > > > > > No offense intended, but with just the PowerPC, and your new cust= om > > > > > peripheral on the PLB bus the odds are that your peripheral is the > > > > > source of the problem. Take a look at the synthesis report for i= t=2E > > > > > In EDK, in the "Project Information Area" pane, and the Project t= ab, > > > > > expand the "Report Files" selection. Find the one for your perip= heral > > > > > and look through it. I think there should be a warning about mul= tiple > > > > > sources driving a destination at this point. If you do not see it > > > > > there, try looking through the implementation/xflow.log file in t= he > > > > > "Log Files" section. > > > > > > > I didn't run the simulation of this platform. I heard the "bus > > > > > > functional model" before, but I don't understand how to use it.= Would > > > > > > you like to give any information about this one? > > > > > > Take a look at: > > > > > >http://www.xilinx.com/ise/embedded/edk6_3docs/bfm_simulation.pdf > > > > > > This link is for the EDK 6.3 version of the documentation, but you > > > > > should have a more recent version in your EDK distribution at $ED= K/doc/ > > > > > bfm_simulation.pdf. > > > > > > One of the main things that I like about using the bus functional > > > > > models is that the bus monitors tell you when a error occurred in= the > > > > > simulation, and what the error was. This saves you the effort of > > > > > having to search backwards from where the symptoms of the error s= how > > > > > up to figure our what has gone wrong. > > > > > > > In addition the error"NgdBuild 455", there are several warnings= "SFF > > > > > > Primitive", i didn't find this on the Xilinx answer database.. = maybe > > > > > > this warning has something to do with the error. > > > > > > > Thank you very much~ > > > > > > Regards, > > > > > > John McCaskillwww.fastertechnology.com-Hidequotedtext- > > > > > > - Show quoted text - > > > > > Thank in advance. > > > > > I check the synthesis report and I found something in implementatio= n/ > > > > xflow.log file > > > > > ERROR:NgdBuild:455 - logical net 'plb_M_ABus<62>' has multiple > > > > driver(s): > > > > pin G on block ppc405_0/XST_GND with type GND, > > > > pin G on block dma_mci_top_0/XST_GND with type GND, > > > > pin P on block ppc405_0/XST_VCC with type VCC, > > > > pin G on block plb2opb/XST_GND with type GND, > > > > pin O on block plb2opb/plb2opb/I_BGO_addrAck with type LUT4, > > > > pin G on block plb_bram_if_cntlr_1/XST_GND with type GND, > > > > pin P on block plb_bram_if_cntlr_1/XST_VCC with type VCC > > > > > There are 7 driver to drive this node and the dma_mci_top is the > > > > custom peripheral. > > > > > I have no idea about this situation. how come does it? I only impo= rt > > > > the custom peripheral and create a platform. > > > > > Does it any problem happend at the process of "Import Custom > > > > Peripheral" ? > > > > 'cause, during the import procedure, I need to set some bus paramet= er, > > > > like C_PLB_NUM_MASTER...etc. > > > > I try to find document on the Xilinx website, but I didn't find any > > > > tutorail about the Import procedure. > > > > > Would you like to give me any hints for solving this problem. > > > > > Thank you very much. > > > > I used the import wizard just a few times to see what it did, then I > > > started creating all my peripherals by hand, so I do not remember how > > > it works very well. But, C_PLB_NUM_MASTER is a parameter/generic that > > > needs to be set by EDK when it creates all the wrapper files for the > > > PLB peripherals. Did you set it to a numeric value? > > > > EDK includes the source code and support files for the cores that it > > > comes with. Look through them for examples of how to create a PLB > > > slave. If I remember correctly, the multi port memory controller > > > reference design also has a PLB slave that is not based on the IPIF, > > > and is simpler. > > > > Regards, > > > > John McCaskillwww.fastertechnology.com-Hidequoted text - > > > > - Show quoted text - > > > Thank you very much. > > > I set C_PLB_NUM_MASTER=3D2 in the verilog design. Does EDK change this > > parameter during creating platform? > > > I wil go to check the examples. > > > Besides, I saw an example that the custom peripheral is imported inot > > EDK without bus interface. How could I do this? I search several > > document, I don't see something to do with it. > > > Thanks again > > > Sincerely. > > EDK automatically sets the values of many parameters/generics when it > creates the wrapper files. C_PLB_NUM_MASERS is one of the ones that > EDK sets. > > I would recomend that you read the "Platform Specification Format > Reference Manual" which defines the contents of the data files that > describes pcores to EDK. It is located in the EDK install directory at > $EDK/doc/psf_rm.pdf. These files > ... > > read more =BB- Hide quoted text - > > - Show quoted text - Hi~ Thanks for your help. I import custom peripheral into EDK successfully. The problem is at the "Bus parameter setting". There is another problem. After downloading the bitstream to FPGA, the function of custom peripheral failed. So, I think that I need to install "BFM" and "ChipScope" to run simulation and debug respectively. Does there have any another recommended tech. to debug? Thanks for your help. regards.Article: 119143
Antti <Antti.Lukats@xilant.com> wrote: >Stephen Williams schrieb: >> -----BEGIN PGP SIGNED MESSAGE----- >> >> Where I work, we've pretty much given up on being able to use >> impact for anything other then writing ACE files, and it does >> a clunky job at that. I suspect that open-sourcing impact would >> make a *lot* of folks very very happy. >Hi Steve >I just recalled, I have reverse engineered the ACE file format >even written ACE compressor and player, so the work has begun >already :) >ah, yes I can open-source the ACE player.. please remind in a few days >should i forget.. Isn't ACE just a compression algorithm/format..?Article: 119144
Leon, You are right to question a 10% claim on a power estimator accuracy. Altera is quite vocal is claiming that their estimator is more accurate than the Xilinx estimator. I would say to this: they are intentionally creating a controversy where none exists to draw attention away from the areas where they do not excel, and into an area where no one can prove anything! It is a typical marketing ploy. Whenever a claim of superiority is made (BRAM, SRL16, DCM, PLL, "faster, better, cheaper" etc etc etc) the customer is being shown a story that does not talk about the items where perhaps the product is not so great. So, is Altera's power estimator that accurate? The question causes everyone to stop, go look for cases where the estimator is broken, create power point slides on how "bad" the tool is, etc. Quite frankly, a waster of time, but it is all in a day's work for marketeers whose job it is to promote their product, and cause customers to look at (other) short-comings of the competition. I would give the estimate a 20% bump for what it might actually be in practice. Any one unit will be under the estimate. Only a fast corner processed part which is shipped to fill the order will come in at the high end of the estimate. Since you can not only order "typical" parts, the additional margin is absolutely necessary. Xilinx cerated a "battle board" with a Xilinx FPGA on one side, and an Altera FGPA on the other side (xc4vlx60, 2s60). We did a identical single ended non-DCI design for both, along with some switching in the core. We demonstrated a significant signal integrity improvement in the package and PCB (the "SmartChevron(tm)" technology). We also demonstrated how the same design in both chips led to a 15 to 20 degree C power savings in V4. Did we focus the customer's attention? Yes. Did we choose an area (actually 2) where we excel? Yes. Did we create a controversy that requires an Altera response? Yes. If you did not have a design that required strong, fast, switching IOs, and you did not have a design that challenged the internal core power, and had a great deal of timing margin (frankly, the majority of designs), then these two issues were "don't cares". AustinArticle: 119145
For the combinational-logic of my state-machine, if I use an always @*,
Xilinx XST erroneously optimizes/removes the logic, and then rips out
any downstream load-logic.
reg [6:0] s_instr_category;
// The "BAD" state-machine
always @* begin : state_machine // <-- line #461
if ( a00 ) s_instr_category = A;
else if ( a01 ) s_instr_category = B;
else if ( a02 ) s_instr_category = C;
...
else
s_instr_category = MY_DEFAULT;
end // always @*
always @ (posedge clk )
if ( s_instr_category == A )
decision_junk <= s;
else if (s_instr_category == B )
decision_junk <= s + 1;
...
WARNING:Xst:905 - "control_fsm.v" line 461: The signals <s_instr_category>
are missing in the sensitivity list of always block.
Module <control_fsm> is correct for synthesis.
I've tried changing always @* -> always @ ( a00,a01,a02,...), but I always
see the same WARNING in the logfile.
I've worked around this problem by using the ?: operator. For some reason,
Xilinx XST is perfectly happy with the following-code (but not the code I
posted top.)
wire [6:0] s_instr_category;
// The "BAD" state-machine
assign s_instr_category =
(a00) ? A :
(a01) ? B :
(a02) ? C :
...
: MY_DEFAULT;
...
Any ideas? I'm using Webpack 9.1i with Service Pack 3 (and IP-update 2.1)
Will this be fixed in Webpack 9.2?
And using 2D-regs in an always @* block still doesn't work.
reg [15:0] mem [0:255];
wire [7:0] address;
always @*
latch_dout = mem[ address ]; // <-- XST 9.1i.03 *ERROR*
Article: 119146<fpga_toys@yahoo.com> wrote in message news:1178922716.701468.78740@n59g2000hsh.googlegroups.com... > From Xilinx's sharp abusive reprimand, you should now understand the > basics about being a Xilinx customer -- if you are not a $100B company > with a $100M engineering budget willing to purchase $1B of Xilinx > product a year, you really don't count enough that Xilinx will be > socially respectful and polite. I feel the OP deserved it. It is really annoying when people ask completely asinine questions that show they are completely clueless and/or lazy. If they haven't got enough intelligence to write a sensible question, they probably don't have enough to do a practical technological project. You end up effectively doing the project for them. Nobody grows muscles by asking other people to do exercises for them. Nor will anybody learn anything by getting other people to think for them. Asking ridicululously vague questions just raises more questions. It's like phoning your doctor and asking "How can become healthy?".Article: 119147
On May 8, 1:53 am, Wilhelm.Kl...@gmail.com wrote: > Has anyone had problems with Altera FIR Compiler generated cores when > using the clock enable signal? > > Have a look at my post at :http://www.alteraforum.com/forum/showthread.php?p=743#post743 > > I am trying to get a programmable coefficient filter to work with a > clock enable, however I get a strange response. I have tried versions > 3.3.0, 3.3.1 and 6.1 of FIR compiler. I understand that as of 6.1 the > Avalon-ST controller is used which is independent of the global clock > enable and is probably causing problems. However v3.3.0 and v3.3.1 > are also giving problems, as I show in the post. The only FIR I can > get to work with the clock enable is a fixed coefficient filter > generated by v3.3.0. Unfortunately Altera support are not offering > good advice on this issue. Hi Wilhelm, There was a bug in earlier versions of the FIR compiler in that it relied on clock enable being high immediately after reset. If clock enable was low, the coefficient address logic would run anyway for a clock cycle, with the result that all coefficients were misaligned to the samples. With Avalon ST, clock enable would be held low until enough input samples were available, which could therefore exercise this bug. Our IP group strongly recommends upgrading to version 7.1 of the FIR compiler, which has a more robust coefficient reload. You can download it from here https://www.altera.com/support/software/download/sof-download_center.html. Hope this helps. Regards, Vaughn Betz AlteraArticle: 119148
Thank you, Austin!Article: 119149
On 13 Mai, 12:00, pbF...@ludd.invalid wrote: > Antti <Antti.Luk...@xilant.com> wrote: > >Stephen Williams schrieb: > >> -----BEGIN PGP SIGNED MESSAGE----- > > >> Where I work, we've pretty much given up on being able to use > >> impact for anything other then writing ACE files, and it does > >> a clunky job at that. I suspect that open-sourcing impact would > >> make a *lot* of folks very very happy. > >Hi Steve > >I just recalled, I have reverse engineered the ACE file format > >even written ACE compressor and player, so the work has begun > >already :) > >ah, yes I can open-source the ACE player.. please remind in a few days > >should i forget.. > > Isn't ACE just a compression algorithm/format..? I mean the "Xilinx ACE", file format for SystemACE its sort of JTAG bytecode, and the information is not public its very simple code, and player is very simple too, way simpler than jam or xsvf... Antti
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