Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On May 3, 2:19 pm, radarman <jsham...@gmail.com> wrote: > On May 3, 12:28 pm, Gabor <g...@alacron.com> wrote: > > > > > On May 3, 11:57 am, radarman <jsham...@gmail.com> wrote: > > > > You should be able to alter the UCF to add the pull-up / pull-downs, > > > though the resistor is permanently enabled after configuration. (you > > > can't control it from the fabric) You can use this feature to > > > eliminate external resistors with great effect. For example, I have a > > > small add-in board that doesn't supply a proper VCC, so I use the > > > internal pull-up to keep the reset line high, and use a switch to > > > short the circuit to ground. Perhaps not the safest circuit, but it > > > works. > > > Again the UCF method only works if the pin in question has > > a net attached to it, i.e. if it doesn't get removed from the > > project as unused. I don't know of any method in the UCF > > to refer to pins merely by location. So while you can put a > > line in the UCF like > > NET "Foo" LOC = AA12 | PULLUP ; > > as soon as the net Foo gets removed from the project > > the pullup resistor goes away, too. > > If the pin really is unused, and you really want that pin to float or > stay at a DC level, then just add the appropriate net. Even something > simple like dummy_net <= 'Z'; would cover it. Just check the FPGA > editor to make sure you are really getting a permanently disabled tri- > state buffer. Then, add the pullup/pulldown constraint to the UCF. Is > there a reason you can't add a dummy net to the pin? > > I generally make a practice of assigning nets to all external I/O, and > then tie them off in the top-level until they are used - just so I can > control stuff like this. That way, I can finish the I/O constraints > early on, and not have to worry about mucking with them later on. In my experience (using XST) if I assign Z to a pad, the net is stripped from the design and then anything attached to the net in the UCF file goes away, too. How do you keep your "dummy_net" from being removed?Article: 118801
On May 3, 4:37 pm, austin <aus...@xilinx.com> wrote: > Steven, > > http://direct.xilinx.com/bvdocs/userguides/ug331.pdf > > page 311. > > Yes. > > Austin Austin, I think the OP was looking to change the pullup/pulldown/keeper dynamically. The IOB structure is programmed at config time. There is no "input pin" to the IOB selecting this feature unless I've missed something here? GaborArticle: 118802
Hi everybody, After synthesizing my architecture using Synplify pro, i received several same warning like: ... hdl\FSM_Write.vhd":65:7:65:8|Pruning Register ...... what does it mean Pruning register? i noticed that it doesn t affect the behviour of my architecture. I found in one forum that it means that the register was removed, is it true???? i don t think so, because i need that register in my architecture. Thank you for your help! A.Article: 118803
On May 3, 2:53 pm, Paul <pauljbenn...@gmail.com> wrote:
> Rising_edge / Falling edge only matter if you're using non '0' / '1'
> values in your simulation... U -> '1' is not a rising edge with
> "rising_edge" but is a rising edge if you use 'EVENT. But U, H, X, L,
> etc... only exist in simulation, no such thing inside your FPGA, so
> assuming you setup your simulation to reflect reality there's no
> difference.
>
> On May 3, 12:17 pm, "Ben Jones" <ben.jo...@xilinx.com> wrote:
>
> > "Paul" <pauljbenn...@gmail.com> wrote in message
>
> >news:1178203259.251061.292370@u30g2000hsc.googlegroups.com...
>
> > > As far as I've heard/seen in large companies with regulated coding
> > > styles,
> > > the wait statement version of a DFF is considered to be sloppy for
> > > readability maintainability purposes. tick-event is considered a much
> > > cleaner way of coding a DFF.
>
> > Well, the IEEE rising_edge and falling_edge functions are standard practice
> > and for good reason. The 'event syntax is beyond obsolete...
>
> > -Ben-
Use of rising_edge() and falling_edge() is more self-documenting,
safer in simulation, and last but certainly not least, easier to
type!
The 'event style is discouraged in our coding style guides.
Another template that I use when needing some flops asynchronously
reset, but not others in the same process is:
process (clk, reset) is
begin
if rising_edge(clk) then
do_synchronous_stuff_here;
end if;
if reset = '1' then
reset_some_but_not_all_flops_here;
end if;
end process;
The advantage is it works without creating feedback muxes for those
flops not being reset. The disadvantage is you don't get a warning if
you unintentionally leave something out of the reset clause.
Andy
Article: 118804hello, one solution is to use a clock with enough high frequency to add delay using counter and if you need lower frequency you can divide the clock using classical architecture for that staff, it is good to use FSM in this case, Good luck, A.Article: 118805
On May 2, 9:53 pm, "Ken Soon" <c...@xilinx.com> wrote: > Oh if for what images to scale.. > hmm maybe videos from a camera? > or would it possible to scale video from a vcd player? > > "Ken Soon" <c...@xilinx.com> wrote in message > > news:f1bf8c$t11@cnn.xsj.xilinx.com... > > > Hi > > Just want to do a feasibility study on whether it is possible to design > > and implement a video scaler on a Spartan 3E? > > Well my tutor kind of came up with this proposal for a project of mine but > > then on my tutor's side, he has experience with fpga but I'm not sure > > whether he had designed video scaling so may not know the complexity of > > it. > > > So, feasible? And with which chip as well? (in the best of best case, i > > hope can use just a spartan starter kit :) ) I have 2 data points for you nased on existing designs with Spartan 2e and Virtex 2. The latter is more closely related to the Spartan 3. In that design I fit a scaler / combiner taking 4 RGB inputs each 800 x 600 at up to 120 fps. The inputs were not synchronized so they needed to be stored in SDRAM first. The output was scaled between 1:2 and 2:1 (50 - 200%) and mixed into a single 800 x 600 output frame DMA'd into a PC using a PLX9656 local bus adapter. This fit pretty handily in a Virtex 2 1000 using DDR SDRAM (1 64-bit SO-DIMM). The other design was standalone using a Spartan 2e 400. This design takes two 640 x 480 inputs stores them in single-data-rate SDRAM and then combines them into a scaled 1024 by 768 output at 60 fps. Both designs use a low-pass filter followed by linear interpolation in each dimension (horizontal and vertical). For the horizontal filtering I used distributed arithmetic filters to save logic. So, given enough time and design expertise I would think you could easily come up with a scaler for TV (even HDTV) video in a Spartan 3 400 or larger assuming you have the other required resources. Usually you'll find that you run out of block RAM before you run out of fabric in this sort of design. Also without the DA FIR, you could run out of multipliers. Have fun, GaborArticle: 118806
Hello all, I'm using XP and paths are separated with backslashes. But Tcl uses slashes. How do you handle that, are there any tricks? I'm working mostly with ISE 9.1, but looking for a common solution. Thanks and greetings UdoArticle: 118807
"Gabor" <gabor@alacron.com> wrote in message news:1178228234.152833.87170@y80g2000hsf.googlegroups.com... > On May 3, 4:37 pm, austin <aus...@xilinx.com> wrote: >> Steven, >> >> http://direct.xilinx.com/bvdocs/userguides/ug331.pdf >> >> page 311. >> >> Yes. >> >> Austin > > Austin, > > I think the OP was looking to change the pullup/pulldown/keeper > dynamically. The IOB structure is programmed at config time. > There is no "input pin" to the IOB selecting this feature unless > I've missed something here? > > Gabor I agree - as a seasoned Xilinx user, the complete user guide does little to suggest that there's pin-level control over I/O pullup/pulldon for such uses as GPIO. - John_HArticle: 118808
OK, If they want to do this using the internal logic, then Antti is correct: they would have to use ICAP, and partial active reconfiguration. AustinArticle: 118809
Andreas Ehliar wrote:
> I was also of the opinion that it wasn't a very good coding style but
> after a couple of years of basic VHDL teaching I think it is actually
> better to say that a sequential process looks like this:
>
> process
> begin -- process
> wait until rising_edge(clk);
> -- Some code...
> end process;
>
>
> The "standard" alternative is this:
>
> process (clk)
> begin -- process
> if clk'event and clk = '1' then -- rising clock edge
> -- Some code...
> end if;
> end process;
I usually write:
process (clk)
begin -- process
if rising_edge (clk) then
-- Some code...
end if;
end process;
The "clk'event and clk = '1'" has always seemed to me to be a
rather obtuse way of describing a rising edge when there is a
perfectly good rising_edge function in std_logic_1164.
However, I'd agree that the process with "wait until rising_edge (clk)"
is more clear for people that aren't familiar with the semantics of
the sensitivity list.
Eric
Article: 118810Hello, Does anyone know of an example using lwIP in RAW mode with the Virtex-4 temac? From what I understand, the lwIP temac port seemingly only supports lwIP in sockets mode with xilkernel. I don't quite understand the lack of temac support at the software level. What are people doing when using temac on the V4? Is everyone using lwIP in sockets mode? No one is using raw lwIP on the V4? PatrickArticle: 118811
I just wanted to try the JTAG Loader tools provided with PicoBlaze and I cannot run neither hex2svf.exe, nor hex2svfsetup.exe. I get "The system cannot execute the specified program" message in the Windows XP Command Prompt. Am I missing something here? Has anybody been able to run these tools and program the instruction ROM via JTAG? Thanks, From invalid@dont.spam Thu May 03 20:20:18 2007 Path: nlpi060.nbdc.sbc.com!newsdst02.news.prodigy.net!prodigy.com!newscon02.news.prodigy.net!prodigy.net!wns13feed!worldnet.att.net!199.45.49.37!cyclone1.gnilink.net!spamkiller2.gnilink.net!gnilink.net!trndny04.POSTED!933f7776!not-for-mail From: Phil Hays <invalid@dont.spam> Subject: Re: Tcl slash backslash User-Agent: Pan/0.14.2.91 (As She Crawled Across the Table) Message-Id: <pan.2007.05.04.03.20.18.130220@dont.spam> Newsgroups: comp.arch.fpga References: <1178229309.357531.173510@p77g2000hsh.googlegroups.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 38 Date: Fri, 04 May 2007 03:20:18 GMT NNTP-Posting-Host: 71.112.129.56 X-Complaints-To: abuse@verizon.net X-Trace: trndny04 1178248818 71.112.129.56 (Thu, 03 May 2007 23:20:18 EDT) NNTP-Posting-Date: Thu, 03 May 2007 23:20:18 EDT Xref: prodigy.net comp.arch.fpga:130490 X-Received-Date: Thu, 03 May 2007 23:20:19 EDT (nlpi060.nbdc.sbc.com) Udo wrote: > Hello all, > > I'm using XP and paths are separated with backslashes. But Tcl uses > slashes. How do you handle that, are there any tricks? I'm working > mostly with ISE 9.1, but looking for a common solution. Yes, I suggest you use "file join". This standard Tcl command creates an OS correct path for any OS. Some examples: To see what it does puts [file join foobar doodoo try.this] To make a "bld" directory at the same level file mkdir [file join ".." bld] To change default to this directory cd [file join ".." bld] To add a few files to a Xilinx project from a source directory at the same level xfile add [".." src foobar.vhd] xfile add ["..] src snafu.v] -- Phil HaysArticle: 118812
The blocks are useful if you want to follow a top down design methodology. When you use the blocks it is akin to creating a "block diagram" sketch of your system before the entire design is fleshed out. You can export each block as VHDL or Verilog file which you can fill in later. The symbols are useful if you are usiing a bottom up design flow. You would create your VHDL, have a symbol created and then hook it up in the schematic editor. The schematic editor allows you to mix blocks and symbols. Hope this helps, Subroto Datta Altera Corp. "davew" <David.Wooff@gmail.com> wrote in message news:1178211448.906410.300480@n59g2000hsh.googlegroups.com... > I'm a fairly experienced user of Quartus but I've never considered > using "blocks" in block design files i.e. my design hierarchy consists > of only symbols with a mixture of Verilog and graphic design modules > "underneath" each symbol. I have never seen a need to use them. > > My question is: does anyone routinely use blocks in their designs and > what are the advantages/disadvantages of doing so? > > It seems to me that they must be there for a good reason. I just > can't see what that reason is and i think I may be missing out on > something potentially useful. > > When I say block I mean using the "block" tool not the "symbol" tool. > Blocks are or can be connected together with "conduits" whereas I > think symbols can only be connected with "bus" and "node" connections. >Article: 118813
On Apr 26, 9:37 am, Bob <rjmy...@raytheon.com> wrote: > I've asked for help once before on this topic and was directed to look > at Ap Note #367. > Unfortunately, when I unzip the example designs, I didn't find a > walk-through or readme > file that describes how to go through each example (am I missing > something?). > > I am using a Stratix II part and need to be able to monitor a input pin, > after power-up/ > reconfiguration is complete, to switch between two different sets of > dividers (this pin > will tell the FPGA that one of two input clocks are going to be used). > From Ap Note 367 > and the ALTPLL_RECONFIG Megafunction User's Guide, it appears that this > external > state machine/logic needs to determine if a reconfigure is required and > if so, issue a 1 clock > pulse on the reconfig pin of the ALTPLL_RECONFIG line, wait for the > reconfiguration to > be done, and then issue an asynchronous reset. (The asynchornous reset > also needs to be > sent even if the reconfig is not needed). > > None of the documentation that I've seen so far shows examples on how to > do this. I've > seen included drawings that just show interconnection between the > ALTPLL_RECONFIG > and ALTPLL -- nothing else is given. > > Does anyone have a step-by-step example with code and/or drawings that > explains how > to really design with the ALTPLL_RECONFIG and ALTPLL megawizard > functions? Hi Bob, Here is some info from our PLL applications team that hopefully helps you. See the Stratix II errata for information on cases when you should reset the PLL after a PLL reconfiguration: http://www.altera.com/literature/ds/esstx2fpga.pdf Under "Stratix II FPGA Device Family Issues", see "PLL Reconfiguration Issue". It describes several scenarios and in which cases a PLL reset is required, as well as how long the reset should be held, etc. This information has not been fully updated in the Application Note. Aside from how to apply areset, the best places to look for info on PLL reconfiguration are: In AN 367, the section titled "Reconfiguring the C0 Counter" gives a step by step description of how to reconfigure the PLL to change the C0 clock output. The first design example is essentially a design setup with the simulation vectors to show this process: http://www.altera.com/literature/an/an367.pdf The Stratix-II clock and PLL HandBook chapter describes what the various counter settings mean and how different settings result in different multiply/divide values. See the "Hardware Features" section entitled "Clock Multiplication & Division": http://www.altera.com/literature/hb/stx2/stx2_sii52001.pdf Hope this helps, Regards, Vaughn Betz AlteraArticle: 118814
Hello, Atom is a new high-level hardware description language embedded in the functional language Haskell. Atom compiles circuit descriptions in conditional term rewriting systems down to Verilog and VHDL for IC simulation, verification, and synthesis. Programming in Atom feels a lot like object oriented design because module interfaces use methods, instead of just wires and bits. We've used Atom successfully on several different "test" designs including bus arbitration, packet routing, memory interfaces, DSP, serial interface controllers, and error correction coding. In fact, an early version of Atom compiled the 802.11an LDPC codec posted to opencores.org. The language is a bit in flux, and the documentation, tutorial, and examples are pretty sparse. But if you're interested in new ways to design hardware, and your not intimidated by Haskell, give Atom a try. It's free. http://funhdl.org/wiki/doku.php/atom -TomArticle: 118815
On 2007-05-04, Ben Jones <ben.jones@xilinx.com> wrote: > Many people's simulations involve multiple components, so what is or isn't > true inside an FPGA/CPLD is not the whole story. As soon as you have an > external pull-up on a line that might clock a FF (e.g. IIC) you're asking > for trouble if you use the "clock'event and clock='1'" style. IIRC, I heard of one user who had problems with an ASIC-style pad level library that transitioned from 0 to 1 via X. So if the designer used this pad for a clock pin, lets just say the simulation didn't quite work out as expected if rising_edge(clk) was used :) The ASIC vendor's recommendation was to use the clk'event style statements instead. /AndreasArticle: 118816
On 4 Mai, 02:37, mludwig <gye...@gmail.com> wrote: > I just wanted to try the JTAG Loader tools provided with PicoBlaze and > I cannot run neither hex2svf.exe, nor hex2svfsetup.exe. I get "The > system cannot execute the specified program" message in the Windows XP > Command Prompt. Am I missing something here? Has anybody been able to > run these tools and program the instruction ROM via JTAG? > > Thanks, they do work check if maybe some DLL are missing AnttiArticle: 118817
Hi, My name is Bryan from Xilinx Asia Pacific. I have on hand a Spartan 3A Starter Kit . However, I was trying out Multiboot Demo Config option 4 which is a video pass through demo that does not seem to work out though. I hook up a camera through a composite cable to a video decoder peripheral which is connected to the starter kit via J17 connector. In addition a LCD monitor is also connected via VGA port to the Starter Kit. No image appears on the monitor when config 4 was run. I thought I was supposed to see images captured by the camera on the LCD. Can anyone help me with this? Also I would like to ask is it possible to port a design within the Spartan 3A Starter Kit PROM to another Spartan 3A Starter Kit PROM. If it is possible, what are the steps needed to be done? Thank youArticle: 118818
On 4 Mai, 09:26, "Bryan" <s...@xilinx.com> wrote: > Hi, My name is Bryan from Xilinx Asia Pacific. I have on hand a Spartan 3A > Starter Kit . However, I was trying out Multiboot Demo Config option 4 which > is a video pass through demo that does not seem to work out though. I hook > up a camera through a composite cable to a video decoder peripheral which is > connected to the starter kit via J17 connector. In addition a LCD monitor is > also connected via VGA port to the Starter Kit. No image appears on the > monitor when config 4 was run. I thought I was supposed to see images > captured by the camera on the LCD. Can anyone help me with this? > > Also I would like to ask is it possible to port a design within the Spartan > 3A Starter Kit PROM to another Spartan 3A Starter Kit PROM. If it is > possible, what are the steps needed to be done? > > Thank you Dear Bryan, can you please tell us where you have found ANY reference that the S3astarter demo designs support video input from J17? maybe those demos are available for Xilinx employees, but from Xilinx public website I see no such demos, or any reference to any video input designs for s3a starterkit board. http://www.xilinx.com/products/boards/s3astarter/files/s3ask_out.pdf there are only video demos that take text and images either from BRAM of NOR Flash, there are absolutly NO DEMOS that use DDR2 memory on the s3a starterkit. AnttiArticle: 118819
"Paul" <pauljbennett@gmail.com> wrote in message news:1178208971.772258.206100@h2g2000hsg.googlegroups.com... > Ken, > > Just out of curiosity, what is your timeline on this project?? > You've been asking about this for months on here! (That's what all > your DDR interface questions were about, no?) You remembered my posts! Ok, anyway, well actually I had started with this project for my attachment which lasted for about 2-3 months and it nearing its end and don't forsee completing it. And next year, I had another full-fledged project assignment which will take about ,taking on the safe side, about 10months? So I thought of trying to progressing on for on my current project design (trying to learn how it works) or maybe even create my own video scaler myself on a cheaper 3E starter kit than the 1600E inrevium board that i'm using now. Hmm, well, not sure on the input data format. I would like to scale a composite video but if i can scale RGB format, I would be satisfied as I'm still really new in this field. Sync timing, hmm I did some tiny demo using other people's design which had a hv sync generator, maybe have to study it more. Input & output resolutions and frame rates? I would like to start with 640x480 and 60Hz since it seems basic enough to start with this (though i would like to cater to lower resolution with progress) Gabor mentioned that he did it with Spartan 2e 400 which took in two 640 x 480 inputs, stores them in single-data-rate SDRAM and then combines them into a scaled 1024 by 768 output at 60 fps. > How accurate do your interpolations need to be? Think basic 1- > dimensional DSP.. how do you upsample a signal? insert zeros between > samples and LPF, right? Or do the same thing in the F-domain by zero > padding the ends of the FFT and inverse-FFT'ing. Either of these > methods in 2 dimensions is going to be a lot of computation and a lot > of taking stuff in and out of memory in different orders. DDR > memories like you to take stuff out in the same order you put them > in... they slow down big time when you try to jump around.. So if you > do this, you will need to some up with some clever methods of read out > pieces from DDR in the incorrect order, and then re-reading from a > local, smaller, block ram in the order you actually want. This will > take careful planning and a lot of simulation, even an experienced > designer would have a tricky time with this and probably get it wrong > in simulation the first shot. Woah, ok I'm totally lost in here. But no problem, I will take note of these points and consult my profs or someone First step i got to take will just be a simple fixed resolution scaling of one resolution set, like you said 1280x960. Well I'm not sure if i will be lent a expensive board with the 1600E on it or the starter kit. Oh I saw that the starter kit does have a DAC and also an ADC. Oh and it does have a Hirose FX2 connector then maybe I can add the digilent video decoder for S video, Thanks alot Paul for providing the considerations that I will need to take note and the immense amount of advices. Btw, just a side note though, for my current project, I have reduced the Htaps and Vtaps to 4 & 3. Minimum frequency is about 177Mhz, above the minimum requirement os 167Mhz. Now i'm just stuck with how to assign the pins (headers, h v coefficients, seq lut address,....) and how to actually use this scaler. Hmm Gabor, even a scaler for HDTV on a Spartan 3e?!... oh btw, combining two 640x480 to a scaled 1024x768, isn't the usual way to interpolate from a single 640x480 source to a 1024x768? oh and regarding SDRAM, i should have enough on even a starter kit with 512Mbit SDRAM available. And aliasing factor, sub-sampling, and lowpass at below f/2...hmm ok will take notes of these too, Jan Thanks alot guys for the help!~ much appreciated :)Article: 118820
"Paul" <pauljbennett@gmail.com> wrote in message
news:1178222002.399673.176480@q75g2000hsh.googlegroups.com...
> Rising_edge / Falling edge only matter if you're using non '0' / '1'
> values in your simulation... U -> '1' is not a rising edge with
> "rising_edge" but is a rising edge if you use 'EVENT. But U, H, X, L,
> etc... only exist in simulation, no such thing inside your FPGA, so
> assuming you setup your simulation to reflect reality there's no
> difference.
Many people's simulations involve multiple components, so what is or isn't
true inside an FPGA/CPLD is not the whole story. As soon as you have an
external pull-up on a line that might clock a FF (e.g. IIC) you're asking
for trouble if you use the "clock'event and clock='1'" style.
I will conceed that this doesn't affect the majority of users. But it still
makes for a nasty trap if you write code that someone else might use in a
different context without delving into the internals to find out how your
clock edges are detected.
As others have pointed out, they're also easier to read and make more sense
to the uninitiated.
My apologies to non-VHDL programmers who are all no doubt wishing we would
take this over to comp.lang.vhdl... :-)
Cheers,
-Ben-
Article: 118821On 28 Apr, 09:50, Eric Smith <e...@brouhaha.com> wrote: > Francesco <francesco_poder...@yahoo.com> writes: > > I'm trying to move my domain from my old provider to a newone (cheap) > > Don't know why ... but this operation seems impossible because my > > hosting has expired before I ask to transfer my domain??? > > Once a domain is actually expired, you have to renew it with the > original registrar before you can transfer to a new registrar. > > And after you renew it, I think you have to wait a while (30 days? > 90 days?) before you can transfer it. I'm not sure why. > > The transfer will involve renewing it for an additional year. Eric, I will create a new webdomain this week end. I will post in this forum the name of the domainArticle: 118822
<Amine.Miled@gmail.com> wrote in message
news:1178228433.558317.69290@h2g2000hsg.googlegroups.com...
> Hi everybody,
> After synthesizing my architecture using Synplify pro, i received
> several same warning like:
> ... hdl\FSM_Write.vhd":65:7:65:8|Pruning Register ......
> what does it mean Pruning register?
> i noticed that it doesn t affect the behviour of my architecture.
> I found in one forum that it means that the register was removed, is
> it true???? i don t think so, because i need that register in my
> architecture.
Yes, "pruning register" means that it is removing a register from the
design. Think of the synthesis tool as a diligent gardener, carefully
removing stray branches from the mildly overgrown shrub that is your design.
Reasons it might do this are:
(1) The register doesn't drive any other logic, and so is unnecessary
(2) The register is a duplicate of another register and only one is needed
(3) The regsiter's value can be shown never to change during operation
(4) ...maybe some other reasons I forgot about.
The synthesis tool is "guaranteed" not to break the functional correctness
of your circuit when pruning registers. That is, if you simulate what comes
out of Synplify, you'll find it does the exact same thing that your original
code did. If it *doesn't*, then you have found a bug in Synplify and you'll
need to complain to Synplicity about it. That's pretty unlikely though.
Cheers,
-Ben-
Article: 118823On May 4, 10:13 am, Antti <Antti.Luk...@xilant.com> wrote: > On 4 Mai, 02:37, mludwig <gye...@gmail.com> wrote: > > > I just wanted to try the JTAG Loader tools provided with PicoBlaze and > > I cannot run neither hex2svf.exe, nor hex2svfsetup.exe. I get "The > > system cannot execute the specified program" message in the Windows XP > > Command Prompt. Am I missing something here? Has anybody been able to > > run these tools and program the instruction ROM via JTAG? > > > Thanks, > > they do work check if maybe some DLL are missing > > Antti Hmmm, no mention of required libraries in the user guide. Do these tools need Xilinx ISE? I have 9.1SP3 webpack installed.Article: 118824
On Fri, 4 May 2007 06:26:28 +0000 (UTC), Andreas Ehliar <ehliar@lysator.liu.se> wrote: >IIRC, I heard of one user who had problems with an ASIC-style pad level >library that transitioned from 0 to 1 via X. So if the designer used >this pad for a clock pin, lets just say the simulation didn't quite work >out as expected if rising_edge(clk) was used :) The ASIC vendor's >recommendation was to use the clk'event style statements instead. I don't doubt your recollection; but if you're right, that's probably the silliest thing I've heard in a long time. At the very least the library vendor should have provided options to allow the X to be suppressed. The idea of an X appearing on a *clock* in sim is absurd. It's even more absurd in Verilog, where you don't have the choice: @(posedge clock) gives you an event on BOTH 0->X and X->1. I'm sure that would have worked really well in gate-level sim :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z