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On Mar 29, 10:52 pm, "John McCaskill" <junkm...@fastertechnology.com>
wrote:
> On Mar 29, 12:45 am, "Allen" <lphp...@gmail.com> wrote:
>
>
>
>
>
> > On Mar 25, 8:39 pm, "John McCaskill" <junkm...@fastertechnology.com>
> > wrote:
>
> > > On Mar 25, 12:32 am, "Allen" <lphp...@gmail.com> wrote:
>
> > > > On Mar 23, 8:33 pm, Zara <me_z...@dea.spamcon.org> wrote:
>
> > > > > On 23 Mar 2007 05:13:46 -0700, "Allen" <lphp...@gmail.com> wrote:
>
> > > > > >hi all,
>
> > > > > >first, i am sorry for my poor English.
>
> > > > > >i use EDK 7.1i and ISE 7.1i.
>
> > > > > >imported custom peripheral with PLB Master Interface ( not from IFIP )
> > > > > >into my .xps project after overcame several problems.
>
> > > > > >In the step " generate netlist " there has no error or warning.
>
> > > > > >but in the step "Generate Bitstream",i got a error message "ERROR!!
> > > > > >NgdBuild:455 plb_M_ABUS<62> has multiple driver(s)": return code 2
> > > > > >abort.
>
> > > > > >already search this problem in xilix's answer database and tried
> > > > > >modify the parameter of C_BaseAddr, but it is still stuck here.
>
> > > > > >does anyone meet this problem before?
>
> > > > > >thanks in advance.
>
> > > > > I always got that messaghe when I had some signal with two outputs
> > > > > connected to it. That seems your case, in your plb address bus, master
> > > > > interface.
>
> > > > > Best regards,
>
> > > > > Zara- Hide quoted text -
>
> > > > > - Show quoted text -
>
> > > > Thanks for your reply.
>
> > > > so it might mean something wrong during import of custom peripheral?
>
> > > > but in 64-bit PLB protocol, the address width is 32-bit.
>
> > > > i already use (C_PLB_AWIDTH-1) to replace with constant "31" in my
> > > > port declaration.
>
> > > > do anything i could try to solve this problem?
>
> > > > thank you :-)
>
> > > The PLB address width is 32 bits. However, the way that all the bus
> > > signals are connected to the PLB IP is that they are concatenated
> > > together. So if you look at the MPD file for the PLB you will see that
> > > it defines the bus width to be 32 bits times the number of masters:
>
> > > PORT M_ABus = M_ABus, DIR = I, VEC = [0:
> > > (C_PLB_NUM_MASTERS*C_PLB_AWIDTH)-1]
>
> > > So the signal plb_M_ABUS<62> is bit 30 of the second master. Look to
> > > see if your core has been assigned the second master slot on the PLB
> > > bus. Assuming that is the case, find what two sources are driving bit
> > > 30 of the address.
>
> > > Assuming that you left the name of your EDK project as system.xmp,
> > > when you tell EDK to generate a netlist it will create a top level hdl
> > > file named either system.vhd or system.v depending on your tool
> > > settings. You can look at this file to see how EDK has connected the
> > > cores to the PLB.
>
> > > It has been a while since I had to find a multi source signal, but I
> > > think that XST will produce a warning about it in its report and tell
> > > you what the multiple soures are. Look in the synthesis report file
> > > for the appropriate core and see if it tells you what the source of
> > > the problem is.
>
> > > Since you are creating your own interface design instead of using the
> > > IPIF, are you using the bus functional models in your simulations? I
> > > use these, and they make the job much easier. I think it was not
> > > until EDK 8.1 that they were integrated into EDK itself, but I was
> > > able to use the CoreConnect tool kit directly from IBM in some of our
> > > early stuff. The bus monitors will tell you as soon as your core has
> > > done something wrong, so you do not have to track the source of the
> > > problem back from when the symptoms show up.
>
> > > Regards,
>
> > > John McCaskillwww.fastertechnology.com-Hidequoted text -
>
> > > - Show quoted text -
>
> > Thanks for your reply. :-)
>
> > Where i could see the second master is who( power pc or custom
> > peripheral ... etc)?
> > I don't know where to check this.
>
> While there may be an easier way, you can just look at a PLB master
> signal that is not a vector. For example, if you look at plb_M_RNW in
> your system.vhd you will see that it is defined as:
>
> signal plb_M_RNW : std_logic_vector(0 to 2)
>
> The entire vector is an input to the plb_wrapper. plb_M_RNW(0) will go
> to PLB master 0, plb_M_RNW(1) will go to PLB master 1, etc.
>
>
>
> > I opened the system.vhd to see who connect to the plb_M_Abus.
> > "PowerPC" have 2 ports and Custom peripheral has 1 port connect to the
> > plb_M_ABus.
> > Next step, I am going to find the XST report file to see who drive the
> > plb_M_ABUS<62>.
>
> No offense intended, but with just the PowerPC, and your new custom
> peripheral on the PLB bus the odds are that your peripheral is the
> source of the problem. Take a look at the synthesis report for it.
> In EDK, in the "Project Information Area" pane, and the Project tab,
> expand the "Report Files" selection. Find the one for your peripheral
> and look through it. I think there should be a warning about multiple
> sources driving a destination at this point. If you do not see it
> there, try looking through the implementation/xflow.log file in the
> "Log Files" section.
>
>
>
> > I didn't run the simulation of this platform. I heard the "bus
> > functional model" before, but I don't understand how to use it. Would
> > you like to give any information about this one?
>
> Take a look at:
>
> http://www.xilinx.com/ise/embedded/edk6_3docs/bfm_simulation.pdf
>
> This link is for the EDK 6.3 version of the documentation, but you
> should have a more recent version in your EDK distribution at $EDK/doc/
> bfm_simulation.pdf.
>
> One of the main things that I like about using the bus functional
> models is that the bus monitors tell you when a error occurred in the
> simulation, and what the error was. This saves you the effort of
> having to search backwards from where the symptoms of the error show
> up to figure our what has gone wrong.
>
> > In addition the error"NgdBuild 455", there are several warnings "SFF
> > Primitive", i didn't find this on the Xilinx answer database.. maybe
> > this warning has something to do with the error.
>
> > Thank you very much~
>
> Regards,
>
> John McCaskillwww.fastertechnology.com- Hide quoted text -
>
> - Show quoted text -
Thank in advance.
I check the synthesis report and I found something in implementation/
xflow.log file
ERROR:NgdBuild:455 - logical net 'plb_M_ABus<62>' has multiple
driver(s):
pin G on block ppc405_0/XST_GND with type GND,
pin G on block dma_mci_top_0/XST_GND with type GND,
pin P on block ppc405_0/XST_VCC with type VCC,
pin G on block plb2opb/XST_GND with type GND,
pin O on block plb2opb/plb2opb/I_BGO_addrAck with type LUT4,
pin G on block plb_bram_if_cntlr_1/XST_GND with type GND,
pin P on block plb_bram_if_cntlr_1/XST_VCC with type VCC
There are 7 driver to drive this node and the dma_mci_top is the
custom peripheral.
I have no idea about this situation. how come does it? I only import
the custom peripheral and create a platform.
Does it any problem happend at the process of "Import Custom
Peripheral" ?
'cause, during the import procedure, I need to set some bus parameter,
like C_PLB_NUM_MASTER...etc.
I try to find document on the Xilinx website, but I didn't find any
tutorail about the Import procedure.
Would you like to give me any hints for solving this problem.
Thank you very much.
Article: 117826"Mark McDougall" <markm@vl.com.au> wrote in message news:461c2d6d$0$13131$5a62ac22@per-qv1-newsreader-01.iinet.net.au... > PeterK wrote: > >> My very first project is a PWM in Quartus II 7.0. I've drawn up a >> block diagram with a 17 bit lpm_counter going into a 5 bit >> lpm_compare. All I want is the top five bits of the counter to go >> into the comparator. After several days of trying I still have no >> idea how to split the 17 bits to just use the top five bits. With a >> normal bus connection it compiles with a Width mismatch error. > > Prediction: One day you'll be *sooooo* sick of trying to maintain > schematics that you'll bite the bullet and start to learn VHDL/Verilog... > > Regards, > > -- > Mark McDougall, Engineer > Virtual Logic Pty Ltd, <http://www.vl.com.au> > 21-25 King St, Rockdale, 2216 > Ph: +612-9599-3255 Fax: +612-9599-3266 I think that you might be right. I haven't yet learned how to integrate the stuff I've learned in "Circuit Design with VHDL" with the Altera block schematics. Up until this month I mostly did C++ programming using emacs in a shell window. Then I got handed a NIOS II devkit and a September delivery deadline. At least "Fisher Price - My First PWM" now works many thanks to Subroto. PeterArticle: 117827
Hi Dmitriy,
"Dima" <Dmitriy.Bekker@gmail.com> wrote in message
news:1176265910.032854.228420@w1g2000hsg.googlegroups.com...
> Hello,
>
> I am working with the ML410 board and the V4FX60 FPGA. For the past
> week and a half, I've been having problems meeting timing and I just
> can't figure out why.
Thanks for the detailed information. Perhaps you could also post some of the
failing paths from the timing report? Otherwise we're all a bit in the dark.
Cascading DCMs in the way you've described does tend to increase jitter on
the resulting clock nets, which can often eat into your timing budget. A few
questions:
(1) How full is your device?
(2) Which version of EDK are you using; and, in particular:
(3) ...which version the apu-fpu core?
Cheers,
-Ben-
Article: 117828if Xilinx software doesnt know "what todo" how should an regular user know? professional programmers should think not use this kind of error messages in any released software. lets hope xilinx hires a few sometimes in the near future to improve the software quality.Article: 117829
On 11 Apr., 04:41, "motty" <mottobla...@yahoo.com> wrote: > I have a webcase open since 3/20. Though I have been given decent > support I find that I get one and only one email from Xilinx per > day...at most. Even if it is a simple response, there is no > communications for at least 24 hours. For instance, this morning I > received an email from my support worker. Since I wanted some more > explanation/other options, I immediately replied. I have not heard > anything since. This is pretty much how all the cases I have opened > have proceeded. > > I understand that these guys are probably overloaded with cases, but > my company has an XPA which supposedly gives us better support > options. I was just wondering if this is the way thigs always work? > Maybe all emails are parsed through some type of system that queues > things such that the workers don't see them immediately. I don't > know... there are approx 1.000 webcases opened per week. they get assigned to lowest support level at start. you may need to pay for "platinum support" to get quicker response i think, somewhere on xilinx web used to be such info. The normal webcases are not handled as priority, need to pay $$$ sure sometimes can escalate the webcase in normal case also. but i never have understand the policy fully. think even if pay for support there is only promise that they respond within 24 hours try changing your contact options to PHONE so you can get immediate feadback AnttiArticle: 117830
Hello I need to create a dual port ram from my DDR-RAM from within hardware. But I can't figure out how to make it work. So my question, is there anybody here who already made something like that and can help me out? I don't have the time to fully search it out myself? You can contact me at wouter. vanhauwaert at gmail.com (msn also), icq: 51491154 TIA, WouterArticle: 117831
Hi, I my case it was always depend on the topic of my problem how long it took, to get contacted by an Xilinx engineer. But after all I never waited that long. Bye HelmutArticle: 117832
In news:1176218252.321023.223500@q75g2000hsh.googlegroups.com timestamped 10 Apr 2007 08:17:32 -0700, "fpgabuilder" <fpgabuilder-groups@yahoo.com> posted: "[..] Actually SystemC is open-source [..] [..]" The SystemC(R) standard is available without paying money and the reference implementation (as opposed to every SystemC(R) library's implementation) is open source. Regards, Colin Paul GlosterArticle: 117833
On Apr 11, 1:56 am, "nezhate" <mazouz.nezh...@gmail.com> wrote: > Hi all, I'm designing a small project which uses the primitive FIFO_16 > of virtex 4. The problem is: > This FIFO uses an asynchronous reset, which resets all flags and > internal registers of FIFO. Reset signal doesn't reset data in and > data out. In my design, I have a synchronous reset and when it occurs > I need to do not have an output data from FIFO. Is it enough to add > some code lines, for example in the top module: > if (RST) > data_out_top_module<=0; > else > data_out_top_module<=data-out-fifo; > Or there exist another solution? > Thanks I'm not familiar with Virtex FIFOs, but I've used FIFO chips. When the FIFO is reset, its flags show that the FIFO is empty. You may get garbage when reading an empty FIFO, or you may get the previously read value. No data is written into the FIFO unless the WR pin is active. So, I'm not sure why you want to zero out data_in and data_out. -Dave PollumArticle: 117834
On Apr 11, 5:39 am, "Helmut" <helmut.leonha...@gmail.com> wrote: > Hi, > > I my case it was always depend on the topic of my problem how long it > took, to get contacted by an Xilinx engineer. > But after all I never waited that long. > > Bye Helmut My experience has been pretty much like the OP's. I think the engineers that handle the web cases by e-mail are in the far east or south Asia. I'm in the U.S. So unless you want to try corresponding in the middle of the night, it's hard to get more than one mail each way per day. Take a look at the time the mail was sent from Xilinx support (if you're using Outlook you may need to look at the full headers to get this information). HTH, GaborArticle: 117835
On Apr 11, 3:58 pm, "Dave Pollum" <vze24...@verizon.net> wrote: > On Apr 11, 1:56 am, "nezhate" <mazouz.nezh...@gmail.com> wrote: > > > Hi all, I'm designing a small project which uses the primitive FIFO_16 > > of virtex 4. The problem is: > > This FIFO uses an asynchronous reset, which resets all flags and > > internal registers of FIFO. Reset signal doesn't reset data in and > > data out. In my design, I have a synchronous reset and when it occurs > > I need to do not have an output data from FIFO. Is it enough to add > > some code lines, for example in the top module: > > if (RST) > > data_out_top_module<=0; > > else > > data_out_top_module<=data-out-fifo; > > Or there exist another solution? > > Thanks > > I'm not familiar with Virtex FIFOs, but I've used FIFO chips. When > the FIFO is reset, its flags show that the FIFO is empty. You may get > garbage when reading an empty FIFO, or you may get the previously read > value. No data is written into the FIFO unless the WR pin is active. > So, I'm not sure why you want to zero out data_in and data_out. > > -Dave Pollum what I want is to zero out data_out. In my case I have : If (RST) reg_b<=0; assign a_wire = data_out_fifo ^ reg_b. // I must get a_wire equal to 0 when RST=1 when reset occurs, fifo outputs the previously read value. Is there any way to do not get this previously read value?Article: 117836
On 11 Apr., 14:39, "nezhate" <mazouz.nezh...@gmail.com> wrote: > On Apr 11, 3:58 pm, "Dave Pollum" <vze24...@verizon.net> wrote: > > > > > On Apr 11, 1:56 am, "nezhate" <mazouz.nezh...@gmail.com> wrote: > > > > Hi all, I'm designing a small project which uses the primitive FIFO_16 > > > of virtex 4. The problem is: > > > This FIFO uses an asynchronous reset, which resets all flags and > > > internal registers of FIFO. Reset signal doesn't reset data in and > > > data out. In my design, I have a synchronous reset and when it occurs > > > I need to do not have an output data from FIFO. Is it enough to add > > > some code lines, for example in the top module: > > > if (RST) > > > data_out_top_module<=0; > > > else > > > data_out_top_module<=data-out-fifo; > > > Or there exist another solution? > > > Thanks > > > I'm not familiar with Virtex FIFOs, but I've used FIFO chips. When > > the FIFO is reset, its flags show that the FIFO is empty. You may get > > garbage when reading an empty FIFO, or you may get the previously read > > value. No data is written into the FIFO unless the WR pin is active. > > So, I'm not sure why you want to zero out data_in and data_out. > > > -Dave Pollum > > what I want is to zero out data_out. > In my case I have : > If (RST) > reg_b<=0; > assign a_wire = data_out_fifo ^ reg_b. // I must get a_wire equal > to 0 when RST=1 > > when reset occurs, fifo outputs the previously read value. Is there > any way to do not get this previously read value? maybe somethin like if fifo_empy = '1' then data_out <= 0; else data_out <= data_out_fifo; end if; You probably do not only want a 0 during reset but also after reset until something meaningful appears on the FIFOs outputs. Beware: if your FIFO has no fall through capability it will only show meaningful data after you read from it. In that case you need keep a state that tells you whether the output is valid or not. Kolja SulimmaArticle: 117837
On Apr 11, 9:20 am, "comp.arch.fpga" <ksuli...@googlemail.com> wrote: > On 11 Apr., 14:39, "nezhate" <mazouz.nezh...@gmail.com> wrote: > > > > > On Apr 11, 3:58 pm, "Dave Pollum" <vze24...@verizon.net> wrote: > > > > On Apr 11, 1:56 am, "nezhate" <mazouz.nezh...@gmail.com> wrote: > > > > > Hi all, I'm designing a small project which uses the primitive FIFO_16 > > > > of virtex 4. The problem is: > > > > This FIFO uses an asynchronous reset, which resets all flags and > > > > internal registers of FIFO. Reset signal doesn't reset data in and > > > > data out. In my design, I have a synchronous reset and when it occurs > > > > I need to do not have an output data from FIFO. Is it enough to add > > > > some code lines, for example in the top module: > > > > if (RST) > > > > data_out_top_module<=0; > > > > else > > > > data_out_top_module<=data-out-fifo; > > > > Or there exist another solution? > > > > Thanks > > > > I'm not familiar with Virtex FIFOs, but I've used FIFO chips. When > > > the FIFO is reset, its flags show that the FIFO is empty. You may get > > > garbage when reading an empty FIFO, or you may get the previously read > > > value. No data is written into the FIFO unless the WR pin is active. > > > So, I'm not sure why you want to zero out data_in and data_out. > > > > -Dave Pollum > > > what I want is to zero out data_out. > > In my case I have : > > If (RST) > > reg_b<=0; > > assign a_wire = data_out_fifo ^ reg_b. // I must get a_wire equal > > to 0 when RST=1 > > > when reset occurs, fifo outputs the previously read value. Is there > > any way to do not get this previously read value? > > maybe somethin like > if fifo_empy = '1' then > data_out <= 0; > else > data_out <= data_out_fifo; > end if; > > You probably do not only want a 0 during reset but also after > reset until something meaningful appears on the FIFOs outputs. > Beware: if your FIFO has no fall through capability it will only show > meaningful data after you read from it. In that case you need keep a > state > that tells you whether the output is valid or not. > > Kolja Sulimma I think this begs the original question of why there needs to be any known value on the data_out when a FIFO is empty? Resetting the pointers and flags is good enough for anything I can think of. What is downstream from the FIFO that needs zero on the data_out when the FIFO is empty? Is the data itself used to indicate its own validity? What does the OP mean by: I need to do not have an output data from FIFO. Zero is output data as much as any other value. The important thing to happen at reset is for the empyt flag to assert. Just my 2 cents, GaborArticle: 117838
motty, Email me your case number. Often complaints like this are found to be invalid. I will accept for the moment that yours is not. However, looking into these reports has taught me a lesson: most often the webcase does not have the information that is requested by the CAE (customer applications engineer), or no response to multiple emails occur (you would be amazed how many people go on vacation and expect the problem to be fixed when they return), or the customer is unwilling to cooperate and perform the required trouble-shooting that some difficult issues require. Perhaps if you are 'VeryBig&Obnoxious, Inc' you can get away with "I want you to come over here, and fix my problem" but that is something that we are not able to offer to everyone (and we don't appreciate being bashed by a customer, even if you are 'right' by definition). Being respectful and listening and cooperating is guaranteed to solve the problem the fastest. That goes both ways. We have three locations for support, located around the world. Depending on your location, there is a support location that is always awake. We do not route cases to India or China (unless you are in India or China!). This is not about providing the lowest cost service, it is all about solving problems the fastest. After all, here in San Jose, we are "offshore" and "foreign" to more than half of our business. The faster we solve your problem, the sooner you order more parts. AustinArticle: 117839
Ken Soon wrote: >> > Yup I saw this > # RAMs : 24 > 16x64-bit dual-port distributed RAM : 6 > 1920x12-bit dual-port block RAM : 9 > 1920x12-bit registered dual-port distributed RAM : 3 > 4096x36-bit dual-port block RAM : 1 > 4096x9-bit dual-port block RAM : 2 > 8x64-bit dual-port distributed RAM : 3 > Since then I have been playing around with my codes, and I can identify > which instances in the codes are using which kind of RAM. >> > Currently I have tried to change some of the instances to use distributed > ram, but forcing the constraint RAM_STYLE to be pipe_distributed > And, going down the list of instances that uses the block ram, when I change > it for for my 6 horizontal and 3 vertical coeffcient instances, viola, it > immediately dropped down to 39 out of 36 block rams! > Hmm, strange, it dropped so much. This is not strange: block-RAMs have 36bits-wide ports at most. Since you have some very small x64 memories that were previously forced into BRAMs, they ended up costing two BRAMs each. With three 8x64 and six 16x64 RAMs, this is 18 BRAMs recovered right there. > Anyway, next i try to work on some instances to change to use distributed > rams. However, I have to be careful to have a balance of not overshooting > the LUTs i have together with the block rams as well. > Then I worked with some line buffer modules under my top modules and well > after synthesis, everything was well under the resources limit. However, the > problem came i tried to implement it. The user constraint file that belong > trial synthesis had a timing constraint and my design timing was twice over > this constraint. > Then i used the timing analyzer and cross probe the problem and could see > the path looked to be quite long. Distributed RAM is slow unless you give it many output register stages to redistribute: each LUT can provide 16bits and these are patched together with muxes to provide larger memories. Your address signals will also have huge fanout which further contributes to the slowness. Since your 1920x12 distributed RAM probably only absorbed one register, the very long paths you are seeing is from address bits down to some part of the way through the output muxes down to the absorbed FFs and then from those FFs through the remaining address muxes to the destination FFs. > So now, i tried to work on this problem by using some of the optimization > options in the ISE > Under the map properties, I selected map option level as high. The runtime > took really long, in the end, i got this message. > > The router has detected a very high timing score (5245937) for this design. > > I thinking of just trying to meet the timing. but when do or can I set the > option "-xe c". I dont see any dos command line for me anywhere... Do not bother with increasing PAR effort, this will do you no good. You need to either put that 1920x12 RAM in BRAMs or add register stages that synthesis will redistribute within the distributed memory to improve your timing score. Start by adding two register levels to your 1920x12 distributed memory's output and your score will most likely drop from over 5M to possibly under 200k. Add extra registers until your timings are met or improvements stall. After this, you will need to realign your processing pipeline to account for the delays on this large distributed memory. BTW, what was your LUT and slice-FF usage with that last attempt?Article: 117840
Newman, Thanks for writing back. I tried: 1. starting the timer 2. writing 8 samples 3. reading timer 4. dividing timer result by 8 --> This gave me an average write time of 20 cc's. So it did lower it some. It's interesting...I'm finding that it takes 21 cc's to read/write data from/to external SRAM. I would think that the FSL link should be *much* faster since it's accessing memory on-chip. In fact, the mb_ref_guide states a latency of 2 cc's for using non-blocking "put" and "get" operations for transferring data over FSL. Blocking accesses stall until there is space available on the FSL. What I am doing is a very simple design, and there shouldn't be any blocking, at least not from the program I am implementing. There must be some way to get better performance than what I'm seeing. I'm not implementing cache with this design. I looked at main.s and couldn't really make much sense of the assembly code. I did searches for put, get, fsl and found nothing. I would be interested to know how the compiler is translating to machine code as well...is there some option for seeing c-code interspersed with related assembly? I set compiler options to no optimization and create symbols for assembly. Joel On Apr 10, 10:42 pm, "Newman" <newman5...@yahoo.com> wrote: > On Apr 10, 11:34 pm, "Newman" <newman5...@yahoo.com> wrote: > > > > > > > On Apr 10, 12:12 pm, "eejw" <wilder_j...@hotmail.com> wrote: > > > > Sorry...typo > > > > 16-bit word (not "16-byte word") in passing data from MB -> pcore. > > > > On Apr 10, 11:07 am, "eejw" <wilder_j...@hotmail.com> wrote: > > > > > Hello all: > > > > > I have a question regarding using SysGen to create a co-processor > > > > that's used in a microblaze design. I'm using EDK v9.1 through the > > > > base system builder wizard to create a design used on a Xilinx ML401 > > > > dev. board. > > > > > I've already generated a simple pcore and connected that to the > > > > microblaze proc. in EDK. Data are being passed from MB -> pcore and > > > > pcore -> MB through shared memory (using the "from register" and "to > > > > register" in SysGen). > > > > > Using the provided function calls for communicating from MB -> pcore, > > > > I do the following: > > > > > findavg_sm_0_Write(FINDAVG_SM_0_D0,FINDAVG_SM_0_D0_DIN, datasamp[0]); > > > > findavg_sm_0_Write(FINDAVG_SM_0_D1,FINDAVG_SM_0_D1_DIN, datasamp[1]); > > > > findavg_sm_0_Write(FINDAVG_SM_0_D2,FINDAVG_SM_0_D2_DIN, datasamp[2]); > > > > etc. > > > > > To check performance, I start timer, do function call to write shared > > > > memory, then read value from timer. > > > > > So it's just: > > > > > //start timer > > > > findavg_sm_0_Write(FINDAVG_SM_0_D0,FINDAVG_SM_0_D0_DIN, datasamp[0]); > > > > //read count register > > > > > I'm seeing that it takes 28 clock cycles to pass a 16-byte word from > > > > MB -> pcore in this way. This seems *way* too long. > > > > > To improve performance, the API documents that were generated when I > > > > created the pcore suggest to remove this line in the xparameters.h > > > > file: > > > > > #define FINDAVG_SM_0_SG_ENABLE_FSL_ERROR_CHECK > > > > > I did that, but it doesn't help. > > > > > I didn't do anything special regarding connecting my pcore to the MB. > > > > Just added it through the Hardware -> Configure coprocessor... tool in > > > > EDK which connects the pcore to MB through an FSL. > > > > > Has anyone investigated this and can share any words of wisdom? > > > > > thanks, > > > > Joel- Hide quoted text - > > > > - Show quoted text - > > > could start timer > > do 4 writes to different locations > > then read the elapsed value > > divide value by 4 manually > > > it would be interesting to see if the value is still 28 clocks > > does MB have a cache? > > chipscope or simulation would highlight what's going on > > > Newman- Hide quoted text - > > > - Show quoted text - > > findavg_sm_0_Write(FINDAVG_SM_0_D0,FINDAVG_SM_0_D0_DIN, datasamp[0]); > > also, disassemble the write function to see how efficiently it > compiled the instruction > I would think that it should be around 1 assembly op- Hide quoted text - > > - Show quoted text -Article: 117841
On Apr 10, 11:51 pm, "H. Peter Anvin" <h...@zytor.com> wrote: > zcsizma...@gmail.com wrote: > > > How big is your form factor? I think it is still easier to make a > > motherboard for the Virtex-4 Mini module, and add a 5V TTL logic > > converter and the power supplies vs. designing a new board. > > I wouldn't worry about power supplies. That should be your smallest > > problem. > > > Other option is to put a small Spartan II and a uC (with external data > > bus support, e.g. Atmega), and use the dual-port ram inside Spartan to > > share memory between uC and Spartan. > > The form factor is quite big -- 100x160 mm (Eurocard), so space is > largely plentiful. The Virtex-4 mini module is quite expensive, though > ($250), which is okay for a one-off but may be too much for an actual > production run -- I would have to do the math on that. > > I didn't realize that Spartan II was 5 V tolerant. I'm going to have to > see if that is practical to combine with a microcontroller. Still needs > dual power supplies, though If not, a 200,000-gate Spartan II > apparently retails for $26 these days; that FPGA should be large enough > to fit an 8- or 16-bit microcontroller core plus all the logic. > > Anyone has any kind of idea how long Spartan II is likely to remain on > the market? > > -hpa IIRC you can put a simple microblaze (32 bits) design into the Spartan- II, IF you don't need too much code space. But picoblaze (8 bit) can be done as well. Probably that would be the easiest solution, have a block ram in your FPGA logic, and map that RAM into uBlaze.Article: 117842
Just a couple more data points to add regarding performance of FSL... I created a 2-processor microblaze design connected by FSL links. With a simple program and using these functions: microblaze_bwrite_datafsl(data[index],0); microblaze_bread_datafsl(result, 0); from mb_interface.h to pass data from one processor to the other and back, and using the counter to measure performance, I found: 1. takes 9 cc's to write a data sample to FSL (doesn't matter if it's 1 or 99 samples and dividing count result by 99) 2. takes 10 cc's to read a data sample from FSL I tried the "non-blocking" functions as well and found the same results.Article: 117843
Hopefully this all makes sense. The serial version of the CRC is the CRC polynomial. If you take your serial version initialized to 0 and shift in a 1b, the resulting FCS is 00000001x. If you next shift in a 0b the resulting FCS is 00000002x. If you continue this process you will have a table of FCS values that look like this: 0000 0001 0000 0002 0000 0004 0000 0008 0000 0010 0000 0020 0000 0040 0000 0080 0000 0100 0000 0200 0000 0400 0000 0800 0000 1000 0000 2000 0000 4000 0000 8000 0001 0000 0002 0000 0004 0000 0008 0000 0010 0000 0020 0000 0040 0000 0080 0000 0100 0000 0200 0000 0400 0000 0800 0000 1000 0000 2000 0000 4000 0000 8000 0000 As you can tell all we did was shift that first initial bit all the way through each of the 32 flip-flops. But on the 32nd (if you start the count from 0) shift that last bit is fed back into some of the other flop-flops. Thus the next shift in the sequence which corresponds with the power of your CRC polynomial is: 04C1 1DB7 This is your CRC polynomial. You can then continue shifting these values. What this table of values constitutes is the Galois Field for your chosen polynomial. Here are the shifts 32 to 39 in binary. This part of the Galois Field forms a matrix of 8 shifts used to shift in your data one byte at a time. Lets call this matrix Alpha8. 32 1 1 1 0 1 1 0 1 1 0 1 1 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 33 0 1 1 1 0 1 1 0 1 1 0 1 1 1 0 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 34 0 0 1 1 1 0 1 1 0 1 1 0 1 1 1 0 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 35 0 0 0 1 1 1 0 1 1 0 1 1 0 1 1 1 0 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 36 0 0 0 0 1 1 1 0 1 1 0 1 1 0 1 1 1 0 0 0 1 0 0 0 0 0 1 1 0 0 1 0 37 0 0 0 0 0 1 1 1 0 1 1 0 1 1 0 1 1 1 0 0 0 1 0 0 0 0 0 1 1 0 0 1 38 1 1 1 0 1 1 1 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 1 0 0 1 0 1 1 0 0 39 0 1 1 1 0 1 1 1 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 1 0 0 1 0 1 1 0 FCS(x+8)=(FCS(x)*Alpha8)+(NewByte*Alpha8) Of course, the Alpha8 matrix multiplied by FCS(x) is the matrix formed by the Galois Field of shifts 39 down to 8. Thus you can see the first term in the VHDL code you provide NewCRC(0) := D(6) xor D(0) xor C(24) xor C(30); comes from the formula I listed above. D is the new byte and Alpha8 is the first column of values in the matrix: 32 1 33 0 34 0 35 0 36 0 37 0 38 1 39 0 So D*Alpha8 is D(6) + D(0), and modulo addition is an xor so it is D(6) xor D(0). If we the do the same thing for the second part of the equation, FCS(x)*Alpha8 you get C(30) + C(24). Putting it all together is D(6) xor D(0) xor C(30) xor C(24). You do this for each column to get all 32 values for the FCS. "osr" <pra.vlsi@gmail.com> wrote in message news:1176271386.137997.315040@o5g2000hsb.googlegroups.com... > Hi, > > Can anyone plz tell me the theory behind 32bit parallel CRC? i m not > getting the basis on which the 32 bit CRC is being calculated in the > code below.This code is generated from the CRC tool of wesite > www.easics.com.I > refered many ieee papers even then i couldnt get the idea.Plz help me > its urgent. > > > library IEEE; > use IEEE.std_logic_1164.all; > > > package PCK_CRC32_D8 is > > > -- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) > -- data width: 8 > -- convention: the first serial data bit is D(7) > function nextCRC32_D8 > ( Data: std_logic_vector(7 downto 0); > CRC: std_logic_vector(31 downto 0) ) > return std_logic_vector; > > > end PCK_CRC32_D8; > > > library IEEE; > use IEEE.std_logic_1164.all; > > > package body PCK_CRC32_D8 is > > > -- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) > -- data width: 8 > -- convention: the first serial data bit is D(7) > function nextCRC32_D8 > ( Data: std_logic_vector(7 downto 0); > CRC: std_logic_vector(31 downto 0) ) > return std_logic_vector is > > > variable D: std_logic_vector(7 downto 0); > variable C: std_logic_vector(31 downto 0); > variable NewCRC: std_logic_vector(31 downto 0); > > > begin > > > D := Data; > C := CRC; > > > NewCRC(0) := D(6) xor D(0) xor C(24) xor C(30); > NewCRC(1) := D(7) xor D(6) xor D(1) xor D(0) xor C(24) xor C(25) > xor > C(30) xor C(31); > NewCRC(2) := D(7) xor D(6) xor D(2) xor D(1) xor D(0) xor C(24) > xor > C(25) xor C(26) xor C(30) xor C(31); > NewCRC(3) := D(7) xor D(3) xor D(2) xor D(1) xor C(25) xor C(26) > xor > C(27) xor C(31); > NewCRC(4) := D(6) xor D(4) xor D(3) xor D(2) xor D(0) xor C(24) > xor > C(26) xor C(27) xor C(28) xor C(30); > NewCRC(5) := D(7) xor D(6) xor D(5) xor D(4) xor D(3) xor D(1) xor > D(0) xor C(24) xor C(25) xor C(27) xor C(28) xor > C(29) > xor > C(30) xor C(31); > NewCRC(6) := D(7) xor D(6) xor D(5) xor D(4) xor D(2) xor D(1) xor > C(25) xor C(26) xor C(28) xor C(29) xor C(30) xor > C(31); > NewCRC(7) := D(7) xor D(5) xor D(3) xor D(2) xor D(0) xor C(24) > xor > C(26) xor C(27) xor C(29) xor C(31); > NewCRC(8) := D(4) xor D(3) xor D(1) xor D(0) xor C(0) xor C(24) > xor > C(25) xor C(27) xor C(28); > NewCRC(9) := D(5) xor D(4) xor D(2) xor D(1) xor C(1) xor C(25) > xor > C(26) xor C(28) xor C(29); > NewCRC(10) := D(5) xor D(3) xor D(2) xor D(0) xor C(2) xor C(24) > xor > C(26) xor C(27) xor C(29); > NewCRC(11) := D(4) xor D(3) xor D(1) xor D(0) xor C(3) xor C(24) > xor > C(25) xor C(27) xor C(28); > NewCRC(12) := D(6) xor D(5) xor D(4) xor D(2) xor D(1) xor D(0) > xor > C(4) xor C(24) xor C(25) xor C(26) xor C(28) xor > C(29) xor > C(30); > NewCRC(13) := D(7) xor D(6) xor D(5) xor D(3) xor D(2) xor D(1) > xor > C(5) xor C(25) xor C(26) xor C(27) xor C(29) xor > C(30) xor > C(31); > NewCRC(14) := D(7) xor D(6) xor D(4) xor D(3) xor D(2) xor C(6) > xor > C(26) xor C(27) xor C(28) xor C(30) xor C(31); > NewCRC(15) := D(7) xor D(5) xor D(4) xor D(3) xor C(7) xor C(27) > xor > C(28) xor C(29) xor C(31); > NewCRC(16) := D(5) xor D(4) xor D(0) xor C(8) xor C(24) xor C(28) > xor > C(29); > NewCRC(17) := D(6) xor D(5) xor D(1) xor C(9) xor C(25) xor C(29) > xor > C(30); > NewCRC(18) := D(7) xor D(6) xor D(2) xor C(10) xor C(26) xor C(30) > xor > C(31); > NewCRC(19) := D(7) xor D(3) xor C(11) xor C(27) xor C(31); > NewCRC(20) := D(4) xor C(12) xor C(28); > NewCRC(21) := D(5) xor C(13) xor C(29); > NewCRC(22) := D(0) xor C(14) xor C(24); > NewCRC(23) := D(6) xor D(1) xor D(0) xor C(15) xor C(24) xor C(25) > xor > C(30); > NewCRC(24) := D(7) xor D(2) xor D(1) xor C(16) xor C(25) xor C(26) > xor > C(31); > NewCRC(25) := D(3) xor D(2) xor C(17) xor C(26) xor C(27); > NewCRC(26) := D(6) xor D(4) xor D(3) xor D(0) xor C(18) xor C(24) > xor > C(27) xor C(28) xor C(30); > NewCRC(27) := D(7) xor D(5) xor D(4) xor D(1) xor C(19) xor C(25) > xor > C(28) xor C(29) xor C(31); > NewCRC(28) := D(6) xor D(5) xor D(2) xor C(20) xor C(26) xor C(29) > xor > C(30); > NewCRC(29) := D(7) xor D(6) xor D(3) xor C(21) xor C(27) xor C(30) > xor > C(31); > NewCRC(30) := D(7) xor D(4) xor C(22) xor C(28) xor C(31); > NewCRC(31) := D(5) xor C(23) xor C(29); > > > return NewCRC; > > > end nextCRC32_D8; > > > end PCK_CRC32_D8; > > > Thanks >Article: 117844
All, OK, I am wrong (it happens). The first level of support is from China and India fro webcase, where we do not ask our CAEs to work during off their off-hours (no night nor 'graveyard' shifts). Because of that, there is a time zone issue for webcases not in their region. They also handle their local cases, too. Locations providing support are: San Jose Ca., Longmont Co., Dublin Ireland, Hyderabad India, Shanghai China, Tokyo Japan. As with any case, escalation is always possible to the next level (and the next, and so on) if the issue is not getting resolved in a timely fashion. AustinArticle: 117845
Just wondered if anyone here has used these devices... I want to do embedded computer vision applications and it sounds like they are a pretty good fit. But I have no idea about the difficulty of using the tools and getting algorithmic concepts into hardware... any feedback would be great.Article: 117846
Does anyone know of a good point of contact at Element CXI? I am currently doing an evaluation of potential platforms / architectures for an upcoming reconfigurable computing application development effort. Some knowledgeable folks pointed me towards Element CXI. The information presented on the Element CXI web site sounds very interesting, but I have not received responses to email inquiries sent to the addresses listed on their web site. Does anyone know of an appropriate POC at Element CXI, and if so, could I ask for the favor of an email introduction? Thank you, and have a great day! Anne anne.l.atkinson@nasa.gov -or- anneatkinson@yahoo.comArticle: 117847
Hi Ben,
> Thanks for the detailed information. Perhaps you could also post some of the
> failing paths from the timing report? Otherwise we're all a bit in the dark.
Certainly. These are the filing paths from the timing report:
Failing path 1: 266 MHz CPU clock (proc_clk_s)
Constraint: TS_dcm_1_dcm_1_CLKFX_BUF = PERIOD TIMEGRP
"dcm_1_dcm_1_CLKFX_BUF" TS_dcm_0_dcm_0_CLK2X_BUF / 1.33333333 HIGH 50%
-----------------------------------------------------------------------------
Check Worst Case Best Case Timing Timing
Slack Achievable Errors Score
-----------------------------------------------------------------------------
SETUP -0.703ns 5.859ns 24 4342
HOLD 0.380ns 0
0
-----------------------------------------------------------------------------
Failing path 2: 133 MHz FPU clock (apu_fpu_clk_s)
Constraint: TS_dcm_0_dcm_0_CLKFX_BUF = PERIOD TIMEGRP
"dcm_0_dcm_0_CLKFX_BUF" TS_sys_clk_pin / 1.33333333 HIGH 50%
-----------------------------------------------------------------------------
Check Worst Case Best Case Timing Timing
Slack Achievable Errors Score
-----------------------------------------------------------------------------
SETUP -0.698ns 8.896ns 28 8584
HOLD 0.013ns 0
0
-----------------------------------------------------------------------------
Failing path 3: 200 MHz DDR2 clock (clk_200mhz_s)
Constraint: TS_dcm_1_dcm_1_CLK0_BUF = PERIOD TIMEGRP
"dcm_1_dcm_1_CLK0_BUF" TS_dcm_0_dcm_0_CLK2X_BUF HIGH 50%
-----------------------------------------------------------------------------
Check Worst Case Best Case Timing Timing
Slack Achievable Errors Score
-----------------------------------------------------------------------------
SETUP -0.596ns 6.192ns 177 30754
HOLD 0.387ns 0
0
-----------------------------------------------------------------------------
> Cascading DCMs in the way you've described does tend to increase jitter on
> the resulting clock nets, which can often eat into your timing budget. A few
> questions:
The cascading DCMs are mainly for DDR2 clock and its clk_90
counterpart. This is the way they come out of BSB wizard. But path 3
does fail from the start (DDR2 clock). It comes out failing from the
BSB wizard without me changing anything in the design.
> (1) How full is your device?
> (2) Which version of EDK are you using; and, in particular:
> (3) ...which version the apu-fpu core?
(1) The design is not full at all. I am only using 20% of the slices
now.
(2) I am using the latest version of EDK (9.1i with SP1)
(3) I am using the latest apu-fpu core (v3.0)
I found it odd that even without the apu-fpu core, my CPU net fails
when I try to clock it at 266 MHz instead of 300 MHz. All I did there
was change the CLKFX multiplier and divider values (and uncheck
CPMC405SYNCBYPASS)! Is there something I am missing here?
I am also using the MGT protector core, which runs off proc_clk_s.
Would that impact the timing? I will try without it.I did notice it
LOCed one of my DCMs.
Thanks
Dmitriy
Article: 117848Austin, First off, I did not intend for my email to come off as a 'bash' against Xilinx and I hope it wasn't interpreted that way. I purposefully used the language I did such that I didn't seem angry or annoyed. Too bad emotions can't be embedded in email. I appreciate the support and was basically just asking questions of the group to see if my experience was typical or out of the ordinary. Having said that, I have read the email traffic for my case and feel that I have responded in a timely fashion with pretty thorough information and answers to things requested. I will email you the case number so you can review it. I know that the author of the app note was away for a few days, so that delayed things since the CAE needed to ask him questions. I am fine with that. I don't expect things to happen at the snap of my fingers. I don't even mind that the problem is not solved yet. I guess I just find it a little frustrating that I cannot communicate with my CAE in a timely fashion. One email per day is not enough sometimes.Article: 117849
"Anne" <anneatkinson@yahoo.com> wrote in message news:1176313795.460803.304700@q75g2000hsh.googlegroups.com... > Does anyone know of a good point of contact at Element CXI? > Ah, "point of contact". That makes more sense. I thought for a moment you meant POC as in the Neil Young song... :-)
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