Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On Mar 20, 4:34 pm, Taylor Hutt <thutt...@comcast.net> wrote: > I've been using the Xilinx Webpack 8.2i since sometime in November, > and I've become so irritated with their software that I'm about ready > to just become a rabid Xilinx basher. I've maintained projects that targeted both X and A, and Quartus is leaps and heaps better (faster, much less buggy, and subjectively more user friendly). Austin's comment about not "competing with _real_ synthesizer" is odd to say the least. It sounds like an admision of defeat. I'm not an A fan-boy. I'd be most happy if X improved ISE. I can imagine A getting design wins simply because ISE's effect on development time. Time to market is King. TommyArticle: 116926
On Feb 15, 7:40 pm, Thomas Womack <twom...@chiark.greenend.org.uk>
wrote:
> In article <1171576522.086383.317...@h3g2000cwc.googlegroups.com>,
>
> spartan3wiz <magnus.wedm...@gmail.com> wrote:
> >There is a major risk for me missing the point here, but I'll give it
> >ago anyway! The original question takled about the ISE and Dual
> >Cores.... why would you need Dual Core for ISE? It does never use more
> >than one of them anyway!
>
> Because the fast (2.4GHz and above) Core 2Duochips get you 4MB of
> level-2 cache which, if you're using ISE on only one core and not
> doing anything very intensive in the background, is all available to
> the ISE process. Given how much of a boost people saw with 1MB-cache
> versus 512k-cache AMD chips, and how memory-intensive FPGA compilation
> is, I would expect 4MB to be distinctly useful.
>
> Tom
Sorry for pulling a really old thread out for a follow-on, but I
figured it would be better to keep the info together than spread
across a bunch of threads.
I'm sure that you are correct that 4 MB would provide super results,
but even 2 MB appears to be more than enough to allow a laptop to be
overwhelmingly faster than a desktop that was considered unbeatable
when it was brand new:
Pentium 4 at 3.2 GHz with 2 GB of RAM results:
Loading device for application Rf_Device from file '2vp40.nph' in
environment C:\Xilinx\Xilinx9.1i.
"benchmarkT_top" is an NCD, version 3.1, device xc2vp40, package
fg676, speed -6
Device Utilization Summary:
Number of BUFGMUXs 9 out of 16 56%
Number of DCMs 4 out of 8 50%
Number of External IOBs 319 out of 416 76%
Number of LOCed IOBs 319 out of 319 100%
Number of RAMB16s 105 out of 192 54%
Number of SLICEs 13951 out of 19392 71%
Starting Placer
REAL time consumed by placer: 11 mins 54 secs
CPU time consumed by placer: 11 mins 36 secs
Writing design to file benchmarkT_top.ncd
Total REAL time to Placer completion: 12 mins 4 secs
Total CPU time to Placer completion: 11 mins 44 secs
Starting Router
Phase 1: 128932 unrouted; REAL time: 12 mins 42 secs
Phase 4: 20607 unrouted; (1604) REAL time: 14 mins 32 secs
Phase 5: 20609 unrouted; (0) REAL time: 14 mins 40 secs
Phase 7: 0 unrouted; (0) REAL time: 16 mins 9 secs
Phase 8: 0 unrouted; (0) REAL time: 16 mins 54 secs
Total REAL time to Router completion: 17 mins 8 secs
Total CPU time to Router completion: 16 mins 39 secs
All signals are completely routed.
Total REAL time to PAR completion: 17 mins 58 secs
Total CPU time to PAR completion: 17 mins 4 secs
Peak Memory Usage: 792 MB
------ compared to ---------
T7200 (2 GHz mobile version of the Core 2 duo) with 2 GB of RAM
results:
Loading device for application Rf_Device from file '2vp40.nph' in
environment C:\Xilinx\Xilinx91i.
"benchmarkT_top" is an NCD, version 3.1, device xc2vp40, package
fg676, speed -6
Device Utilization Summary:
Number of BUFGMUXs 9 out of 16 56%
Number of DCMs 4 out of 8 50%
Number of External IOBs 319 out of 416 76%
Number of LOCed IOBs 319 out of 319 100%
Number of RAMB16s 105 out of 192 54%
Number of SLICEs 13951 out of 19392 71%
Starting Placer
REAL time consumed by placer: 6 mins 12 secs
CPU time consumed by placer: 6 mins 9 secs
Writing design to file benchmarkT_top.ncd
Total REAL time to Placer completion: 6 mins 20 secs
Total CPU time to Placer completion: 6 mins 14 secs
Starting Router
Phase 1: 128932 unrouted; REAL time: 6 mins 37 secs
Phase 4: 20607 unrouted; (1604) REAL time: 7 mins 31 secs
Phase 5: 20609 unrouted; (0) REAL time: 7 mins 34 secs
Phase 7: 0 unrouted; (0) REAL time: 8 mins 24 secs
Phase 8: 0 unrouted; (0) REAL time: 8 mins 48 secs
Total REAL time to Router completion: 8 mins 54 secs
Total CPU time to Router completion: 8 mins 48 secs
All signals are completely routed.
Total REAL time to PAR completion: 9 mins 25 secs
Total CPU time to PAR completion: 9 mins 4 secs
Peak Memory Usage: 784 MB
Article: 116927Austin wrote: <snip> > One other comment: our synthesis tool (XST) was never meant to compete > with the "real" tools that exist. XST is a vehicle for research into > synthesis, where we have an opportunity to test how synthesis works with > our FPGAs. We share all synthesis ideas and improvements with the > "real" synthesis tool vendors, so that they may add value by performing > more efficient synthesis using our devices. This is in no way an > apology for bugs, but a statement of fact. XST is not intended to > compete with "real" synthesis tools. It is made available in Webpack, > as a means to allow others to get some feeling for the flow, and the > potential. The XST team is dedicated to pioneering improvements, and > they very much like to get feedback. Wow. Didn't Xilinx just add their own XST Simulation flow ? - does that simulation capability, come into the same category, of "never meant to compete with the "real" tools" ? How many staff do Xilinx have working on XST ? - do they concurr with Austin's statements above ? -jgArticle: 116928
i use matlab simulink to produce a wave .I want to make the wave in the .mif or .hex form .so i can load the wave to ROM.how to make a wave into mif or hex form.Thanks!!Article: 116929
Jim, http://www.xilinx.com/products/design_tools/logic_design/synthesis/xst.htm If you read that page, it says what I just did, but in "marketese." I quote: "Xilinx uses XST as a proving ground for many of the innovative optimization ideas that Xilinx engineers have for improving HDL design flows for Xilinx devices. These improvements are then shared with Xilinx third party synthesis partners to ensure that anyone targeting Xilinx FPGAs as their solution can benefit from the best optimization the industry has to offer." In other words, XST is a test vehicle where we are intentionally experimenting, in order to improve. AustinArticle: 116930
Tommy, http://www.xilinx.com/xlnx/xil_ans_display.jsp?sGlobalNavPick=PRODUCTS&sSecondaryNavPick=Design+Tools&iLanguageID=1&getPagePath=15390 Might answer your questions. Doesn't anyone even do a simple search before they type their response? AustinArticle: 116931
On Mar 20, 8:35 pm, Austin <aus...@xilinx.com> wrote: > Tommy, > > http://www.xilinx.com/xlnx/xil_ans_display.jsp?sGlobalNavPick=PRODUCT... > > Might answer your questions. And how is that in any way related to what I wrote? It doesn't address the slowness of ISE, all the many many bugs, and the broken user interface. Doesn't anyone even read the articles they are replying to before they type their response? TommyArticle: 116932
Tommy Thorn wrote: > On Mar 20, 4:34 pm, Taylor Hutt <thutt...@comcast.net> wrote: >> I've been using the Xilinx Webpack 8.2i since sometime in November, >> and I've become so irritated with their software that I'm about ready >> to just become a rabid Xilinx basher. > > I've maintained projects that targeted both X and A, and Quartus is > leaps and heaps better (faster, much less buggy, and subjectively more > user friendly). Austin's comment about not "competing with _real_ > synthesizer" is odd to say the least. It sounds like an admision of > defeat. > > I'm not an A fan-boy. I'd be most happy if X improved ISE. I can > imagine A getting design wins simply because ISE's effect on > development time. Time to market is King. I worked a lot with ISE and only a few months with Quartus. I personally prefer Xilinx's devices but my short experience with Quartus was enough to make me feel like Quartus' synthesis flow is more mature. If I had to devices based on vendor-supplied tools, Quartus' more mature feel would offset my long-time Xilinx device preference. It is quite a shame that Xilinx puts so much (misplaced) effort in revamping their GUI but fail to fix the countless synthesis and GUI crash-bugs. Another annoyance with ISE is the wildly varying synthesis runtimes: running a small design (~20% of a V2P30) after cleaning may complete in 10-15 minutes one time and stall for 10-20 minutes to complete in 30+ the next time. Since these stalled runs often ran for over an hour or even failed to complete overnight a few times, I decided to start killing and restarting synthesis runs that deviated by more than 50% of an average run. As for Austin's comment, I too remember reading that Xilinx cooperates closely with Synplicity to accelerate support for new FPGA features and optimizations. IIRC, that source said ISE exists primarily as an internal research tool, device/technology evaluation, characterization and as a basic vendor-supplied suite for people/companies that do not with to buy separate third-party synthesis packages. If you look at job postings, you will notice that practically 100% of Xilinx-oriented openings where FPGAs are used for complex processing post experience with Synplify as a must, hinting that relatively few serious Xilinx FPGA designs use ISE... this requirement appears to be far less frequent on Altera-oriented postings. I really wish Xilinx would put more effort in making their synthesis tool-chain more stable before reworking GUIs and adding more features. Until then, Synplify is still an option (perhaps more along the lines of necessary) for more serious projects.Article: 116933
Patrick Dubois wrote: > On Mar 19, 4:06 pm, "B. Joshua Rosen" >> The E6700 has a lot of headroom, I'm running mine overclocked to 3GHz >> using the stock Intel cooler and 4G of DDR2 800 RAM slightly underclocked >> to 750MHz (the RAM speed is set to 667 in the BIOS, the core clock is at >> 300 instead of 266 which gives you 752). I'm running the system 24/7 >> doing NC Verilog simulations and Xilinx place and routes. It's been up >> since Dec without any problems. > > I wish I could buy a system that has overclocking potential. > Unfortunately we are mostly limited to Dell machines, which do not > provide any overclocking possibilities in the bios. Maybe I can > convince the IT guy to buy from another supplier. Do you have any > recommendation for a reputable PC builder company which doesn't lock > its bioses as much as Dell does (for a reasonnable price)? If you are a little lucky, you might be able to find an overclocking tool that will enable you to tweak your computer's clock generator. My current computer has a P4P800-VM board whose BIOS lacks bus speed adjustments but I downloaded a clock generator control program for my board's IC and I was able to overclock my P4-3.0 up to 3.5GHz - I overclocked only for burn-in and stability testing for about a week, I am back to stock speed for power/noise-saving. I got the clockgen control utility for my board's chip there: http://www.cpuid.com/clockgen.phpArticle: 116934
Austin wrote: > Jim, > > http://www.xilinx.com/products/design_tools/logic_design/synthesis/xst.htm > > If you read that page, it says what I just did, but in "marketese." > > I quote: > > "Xilinx uses XST as a proving ground for many of the innovative > optimization ideas that Xilinx engineers have for improving HDL design > flows for Xilinx devices. These improvements are then shared with Xilinx > third party synthesis partners to ensure that anyone targeting Xilinx > FPGAs as their solution can benefit from the best optimization the > industry has to offer." > > In other words, XST is a test vehicle where we are intentionally > experimenting, in order to improve. Well, I don't quite take the same meaning from the above web-statement, as I do from your posting : "our synthesis tool (XST) was never meant to compete with the "real" tools that exist." " It is made available in Webpack, as a means to allow others to get some feeling for the flow, and the potential." I see nothing in the web statement than excludes XST being a "real" tool, and in fact, you could read it that XST will always be "out ahead", because the _others_ have to follow the XST lead. Your posting moves XST into the "not for real designs"/ [as is, where is] pigenhole, which is frankly startling. Do those that work on XST really believe that, and apply that work-ethic to quality, and get given meagre resources by management that match the 'never meant to compete with the "real" tools' claim ? Where does that leave your CPLD customers, for example ? -jgArticle: 116935
On Tue, 20 Mar 2007, Peter Alfke wrote: > Dmitry, whatever timing poblems you have has nothing to do with the > BlockRAM itself. > It is a synchronous device (think of it as a flip-flop or register) > with a data and address input set-up time below 1 ns, and no hold time > requirement. Clock-to-out (for reading) can be up to 3 ns. In the past I've had no problems using the blockRAM for similar tasks, so these problems really came as a surprise. In fact, the code has evolved from the older version (which never had such issues). I am trying now to redo the transition step-by-step to see where the problems start. Unfortunately, at this point my trust in tools is not too great, especially since XST will not properly synthesize dual-port blockRAM coded according to the templates distributed with the ISE (examples_v9.zip). > I hope you use a global clock for clocking the BRAM and the adjacent > logic... The data acquisition logic as well as BRAMs are clocked by a DCM which drives a BUFG. Here is the timing constraint for the DCM input clock: NET "clkp" TNM_NET = FFS(*) "clkp"; TIMESPEC "TS_clkp" = PERIOD "clkp" 3.8 ns HIGH 50 %; -- Dmitry TeytelmanArticle: 116936
On Wed, 21 Mar 2007, Duane Clark wrote: > dimtey@moc.liamg wrote: >> ... >> So here is the problem: the data is written correctly into the SRAM, but >> not into the block RAM. It is a timing problem - errors go away if I lower >> the clock frequency. >> ... > > Show the actual clock constraints you are using. The data acquisition logic and BRAMs are clocked by a DCM driving a BUFG. The DCM divides the input clock by 2 (using CLKDV output). Here is the timing constraint on the DCM input clock: NET "clkp" TNM_NET = FFS(*) "clkp"; TIMESPEC "TS_clkp" = PERIOD "clkp" 3.8 ns HIGH 50 %; -- Dmitry TeytelmanArticle: 116937
Is he? First Austin admits Cyclone 3 is lower power than S3E or V5. Then he tells us to stop using XST for real designs. All in one day. Please, someone from Altera send him a fruit basket. Ricky Sticky.Article: 116938
Guy Eschemann wrote:
> Hi,
> is there a way to get the Xilkernel to run with a C++ application? I
> didn't find any option for this in the XPS "Software Platform
> Settings".
> The problem I'm having is that my thread function ("TSK_Main", which
> is declared in the C++ application) cannot be called from libxil.a,
> which is a C library. This is the error message that I'm getting while
> trying to build the C++ application:
> ../../ppc405_0_sw_platform/ppc405_0/lib/libxil.a(init.o):(.sdata+0x0):
> undefined reference to `TSK_Main'
> Maybe someone knows a workaround for this?
This seems to be a linker problem. The naming conventions for c and c++
object files are different. You can declare C function in C++ with:
extern "C" {
... TSK_Main(...);
}
or vice versa
extern "C++" {
... TSK_Main(...);
}
> Many thanks,
> Guy.
>
Article: 116939Wojciech Zabolotny <wzab@mail.cern.ch> writes: > The nodelist file, required to run multiple par instances contains just > two lines: > xlx1 > xlx2 When I did this on several years ago on our multi-cpu SUN's I just listed the hostname multiple times using a mix of upper and lower case letters , e.g. xlx xLx xLX Xlx would run four processes on the machine xlx. I think the last time I did this was around 2002 (Alliance 4.1) so I don't know if it still works... Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 116940
Hi All, Xilinx "par" utility allows to run a few place and route processes in parallel on different machines. However my problem was - how to utilize fully dual core processor on my workstation. Finally I have found quite nice solution: Let's assume, that ISE is installed in the directory /home/user/Xilinx I'm calling ISE from the script of the following form: #!/bin/bash export PAR_AUTOMNTPT="/" export PAR_M_SETUPFILE="/home/user/Xilinx/settings.sh" . /home/user/Xilinx/settings.sh ise The nodelist file, required to run multiple par instances contains just two lines: xlx1 xlx2 where xlx1 and xlx2 are fake host names defined in the /etc/hosts as aliases to the localhost: [...] 127.0.0.1 localhost xlx1 xlx2 [...] Of course to allow runing of par on the emulated hosts you need also to setup ssh for paswordless login (the utilities called below will ask you some questions, which you should answer reasonably; see the appropriate man pages for reference): $ssh-keygen $eval `ssh-agent` $ssh-add $ssh-copy-id user@xlx1 $ssh-copy-id user@xlx2 The above recipe works for me with ISE9.1i on Debian GNU/Linux etch/testing. -- HTH & Regards, Wojtek Zabolotny wzab@ise.pw.edu.plArticle: 116941
"Brandon Jasionowski" <killerhertz@gmail.com> wrote in message news:1174428437.044909.243800@e1g2000hsg.googlegroups.com... > Hello, > > I have a design on a SX55 that contains of two complex (real > +imaginary) datapaths. I've been trying to debug the code in Chipscope > Did you try Modelsim?Article: 116942
Ellipsis(...) is a defined stuff in ANSI-C. I doubt if it is so in SystemVerilog.Article: 116943
without being any expert on the topic, have you considered that bad PCB layout (ground bounce, crosstalk, too long traces, no termination and so on) might be the cause of the noisy data? PCB layout is very important at high frequencies > 25Mhz and with fast risetimes.Article: 116944
I have to generate a block ram in xilinx. The data width is not fixed and it will be changed according to the requirement of project. I have noticed that the data width in the block ram has been designed to be the 2's exponential size. Sometimes the data width I needed was not exactly the 2's exponential size. Is there a way to make the data size not the 2's exponential size exactly? Like 18bit width. Thank you.Article: 116945
msg wrote: > Herbert Kleebauer wrote: > Do you have electronics recycling centers in your region? In > the U.S., these places accumulate vast quantities of serviceable > (usable) laptops which would be ideal platforms for the ongoing > hosting of the DOS software, and one can obtain quantities of > the machines for next to nothing. The problem is not the money, but the time of the students. The system must be very easy to use so the students can built the simple CPU at gate level in 10 hours including the time to learn the tools. And we don't want to use old hardware (we want to replace our old PC's). It would be ideal if the software would run on an actual OS (XP or maybe VISTA) so we wouldn't need any own hardware at all and could use the already existing computers in an electronic classroom (which also isn't in the first place a question of money but of available free rooms). > Also, it would be an interesting experiment to try running > the software on a VMWare MSDOS VM (a no-cost experiment); please > report the results! I hoped somebody already has done this and I could get some information.Article: 116946
Symon wrote: > If it's OK, I have an observation. I wonder why these students are being > taught design methods on design tools and FPGA parts that most folks on this > newsgroup haven't used for a long time. The schematic vs. HDL wars have long > since died down because modern FPGA designs are generally 'better' > implemented using HDLs. This is an exercise to a lecture about computer organization. The student have just learned how to make a truth table, minimize logic functions and design simple state machines. In this exercise they should use this knowledge to implement a little bit more complex design. And what can be more interesting than designing your own CPU. Therefore VHDL isn't any alternative, they are only allowed to use D-FF's and simple gates like AND,OR,NAND,NOR. We could stop the course after simulating the design, but it is much more motivating when at the end your CPU is running in hardware. But this hardware has to be a simple hardware (not one of this complex multilayer FPGA prototyping boards) so they see that there is no hidden technology and they even could make the same board at home with an cheap soldering iron. > p.s. I HATE Viewlogic. I wasted a day on a legacy design a while back > because a wire had the wrong shaped dot on it. The worst part was the bloody > software guy spotted the mistake! Maybe you didn't use the DOS version. I suppose this software was made by hardware engineers to support there work. An it was so good that other people also wanted it. But with the success of the tool the company hired software engineers and these people can destroy any perfect usable SW in nearly no time. I installed the Windows version of WorkView when it was available, but after testing immediately deleted it. The same happened a few years before with the Daisy CAD system.Article: 116947
cs_posting@hotmail.com wrote: > On Mar 20, 11:23 am, Herbert Kleebauer <k...@unibwm.de> wrote: > > The last > > version of XILINX ISE software which supports XC3000 FPGA's > > isn't an alternative (and I'm not sure whether it will > > run on W2k/XP) because the system must be extremely easy to > > use so the students are able to design and implement a simple > > CPU in about 10 hours (including the time to learn how to use > > the schematic entry and simulation tool). > > As a suggestion, drop the schematic entry approach and introduce a > hardware design language such as Verilog, or VHDL, or some academic > invention that can be translated - these are much more powerful and > extensible to real world applications. They are also much more > portable. As I explained in the other reply, that isn't an alternative.Article: 116948
Jim Granville wrote: > What are the prime teaching targets: learning FPGA flows, or > learning shematic entry ? Nothing of both. The goal is, to use a handful of FlipFlops and gates to implement a design for which you only get the specification. It's just a replacement for a prototyping board with many TTL gates. > Isn't '5 years old', actually new on your time scales ? > Get the Atmel tools and try them Atmel only offers a place and route tool. Therefore I asked if somebody can suggest a simple to use design software (with a schematic entry) for the Atmel FPGA's. > > - has anybody experience with ATMEL's AT40K20 and can suggest > > development software (it must be a schematic entry, no VHDL > > because the students have to "see" the processor at gate level. > > What about simpler HDLs, like CUPL or ABEL ? > With those, you can 'see' the AND and OR terms ? > What about 'seeing' the result in the report files - is that > gate-level enough ? That's like a city map which doesn't use graphics but only textual description of the street position and connections. You will never get a feeling for the layout of the city whereas a fast glance on the graphical city map shows you all. Sure, if you use one of the modern navigation systems you don't need any overview of the city, you are told when to turn left or right. This may be is the best way if you only want to go from position A to position B, but if have to understand how the city is organized, then this is completely inappropriate. > > 2. Was somebody able to run Viewlogic (DOS version) in a virtual > > PC emulation. The problem is, the virtual PC must provide > > the proper graphics mode, mouse type and support a physical > > dongle on the virtual parallel port. > > Keys on virtual parallel ports ?! Nope... Then it should be legal to remove the copy protection from the software.Article: 116949
John Adair wrote: > > Going sideways on what you are looking for it is worth looking at a > couple of ideas from our product line to allow the easy use of modern > FPGAs. The first is our Craignell family > http://www.enterpoint.co.uk/component_replacements/craignell.html > which operate from 5V, in a DIL format, and are fully 5V tolerant. At > the moment we do 32,36,40 pin versions but I expect to have 28 and 48 > pin versions added to the range. Maybe a few others if someone gives > us a good reason. > > Almost a bigger brother our product Darnaw1 is waiting in our lab for > a couple of days test before it goes into mass manufacture. This is a > 2.54mm pitch PGA style module that lets you use a XC3S1200E/1600E > Spartan. This module is 3.3V tolerant and operates from a single 3.3V > input. The module also has spi flash and sdram to allow the > implementation of fairly powerful processor applications. Sounds interesting. Are there any data sheets available?
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z