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On Mon, 28 Nov 2005 03:15:36 -0600, alastairlynch@blueyonder.co-dot-uk.no-spam.invalid (al99999) wrote: >Thanks for all your help. One quick last question, is it possible to >internally connect the pins, or do I need to physically wire them up >external to the fpga? Thanks again, > >Alastair You could bring the signal in on 1 pin, and then setup 8 other I/Os as bi directional, and send the signal out on all 8, and then bring it back in on those 8, with the IDELAY stuff. Doing this will make the external pins wiggle, so they would all have to be "no connection" externally. Overall, I would not recommend this structure, as you will not have good control of the delay to each of the output circuits, and this would therefore add to the error in timing. I think it is best to distribute the signal on your PCB. PhilipArticle: 92351
Frank wrote: > I have some digital waveforms, during the idle interval, it's zero, while in > active > mode, some patterns are output. This waveform is send through DAC (TI > DAC290x-EVM) and ADC (Analog AD9218). I am expecting a clean > zeros during the idle interval, however the ADC output are not. How can I > correct this problem? How does it compare with the analog signal? What is the magnitude of your error? IF there an AC component to your reading during idle? If the error is small, it is probably system noise. -- ThadArticle: 92352
Monica wrote:
> We are confused how FPGA drives logic on the pins that we donot use in
> design.Are we missing something?
By default, some versions of quartus route signals
through unused pins to save internal resources.
> Can anybody please give us a hint how to solve this problem?
One way is to declare and describe exactly what
you expect these pins to do:
a <= '0';b <= '0'; c <= '0';...
Or
c <= a and b and ...;
The other way is to change the synthesis
default setting for unused pins.
-- Mike Treseler
Article: 92353Frank wrote: > When my DAC output is from 0-1V, and is fed into 10-bit AD9218 which > is set to binary mode, what binary value will I get when the input is -10mV? If your DAC is really set to produce outputs from 0-1V, any apparent negative voltages are necessarily analog noise. This isn't a question about bit values. There are straight binary, offset binary, and two's-complement binary. If you want details, point me to relevant data sheets. Jerry -- Engineering is the art of making what you want from things you can get. ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻArticle: 92354
> HI group, > > I am searching for some technique which can give me instruction count > and cache hits/misses for a configuration created using Xilinx FPGA. > I have bitstream corresponding to that configuration. > My objective is to get the following statistics such as instruction > count and cache hits/misses for any application executing on the system > configuration downloaded on FPGA. > That's a very strange question. Instruction count and cache misses are related to processors and do not apply to FPGAs per se. You can implement a processor as soft-core in the FPGA and than it's easy to add all your measurement registers in the FPGA. MartinArticle: 92355
I am looking to buy either a new or used copy of the HDL Chip Design book by Douglas Smith. Email me if you have a copy that you want to sell. Thanks ToriArticle: 92356
Hi Monica, in Quartus II software, select Assignments in the menue selection, there you select "Device". Now a settings window pops-up, press the "Device & Pin Options..." button. Another window pops-up. One of its tabs is called "Unused Pins". That is what you are probably looking for. Alternativ another smart and good way is of course Mike's hint of assigning unused pins directly to a specific signal, e.g. 0. HTH HenningArticle: 92357
Tori, Just in case you didn't know about these places... http://www.alibris.com/ http://www.bookpool.com http://www.allbookstores.com/ Also, eBay, Amazon. HTH, Syms. "Tori" <tori_a9@yahoo.com> wrote > I am looking to buy either a new or used copy of the HDL Chip Design > book by Douglas Smith. >Article: 92358
Hi, thanks for your code. I think I've found a solution: The read and write pointers will be implemented in gray code. Then I'll decode them to binary code and multiply by 18. The multiplication should be a simple addition, so there is no big resource using. (*18 = *16 + *2) But I've a last question: If I compare the two gray coded pointers, no glitch can appear on the full or empty signals? Or do I have to consider something else? Thanks, MichaelArticle: 92359
Martin Schoeberl wrote: >>HI group, >> >>I am searching for some technique which can give me instruction count >>and cache hits/misses for a configuration created using Xilinx FPGA. >>I have bitstream corresponding to that configuration. >>My objective is to get the following statistics such as instruction >>count and cache hits/misses for any application executing on the system >>configuration downloaded on FPGA. >> > > That's a very strange question. Instruction count and cache > misses are related to processors and do not apply to FPGAs > per se. You can implement a processor as soft-core in the > FPGA and than it's easy to add all your measurement registers > in the FPGA. I think the poster wants to know these statistics for the embedded PowerPC processor. This is actually very important for users who want to optimize their PPC code. Perhaps one of our Xilinx regulars can provide some hints. --- Joe SamsonArticle: 92360
Phil Hays wrote: > This is fairly simple, put in a binary counter or similar safe > statemachine with more than enough counts (or states) to make sure > that the reset is released, have it hold synchronous reset to the > reset of the design until count complete, then release it. Example in > VHDL follows: > > > use ieee.numeric_std.all; > entity > ... > architecture > ... > Signal reset : std_logic := '1'; > Signal count : unsigned(3 downto 0) := "0000"; > begin > -- > -- This counter is used to hold all statemachines in reset for the > -- first 8 or so clocks after the end of configuration. > -- > RESET_STATE: process(clk) > begin > if rising_edge(clk) then > reset <= count(3); > if count(3) = '1' then > count <= count + 1; > end if; > end if; > end process; > (rest of code) > > This is not safe as presented, as you can't guarantee all the flip-flops in the counter will be released from reset on the same clock cycle. To make this robust, the power up reset has to be registered by clk and that local synchronous reset used to reset the counter. In Xilinx FPGAs, it is easier and more compact to use the SRL16 as a shift register to delay the reset, and it avoids the reset signal time of arrival issue inside the reset circuit.Article: 92361
Martin Schoeberl wrote: > For Xilinx I only know those RAMB16_S9_S36 components where > the memory size is part of the component name. Is there a > a Xilinx block RAM component where I can specify the size? > > Thanks, > Martin > > There is for Virtex4: the Ramb16 component sets the aspect ratio with generics/attributes. It, however, is not backwards compatible with the earlier families. You can write a single file that uses generate to select the appropriate BRAM size based on input widths or generics. Once written, it can be used in many projects, so hopefully you can ammortize the coding effort over many projects. Once done, the generates are transparent to the end user unless he decides he has to look under the hood to see what the generic RAM you created has under the hood.Article: 92362
A demo long ago made me think things were messed up and the FAE couldn't explain things at that demo. It occurred to him later that there was a separate step to associate the original signal name database with the chipscope signal order. He thought it *should* be part of the normal tool flow for just his reason but it's still a separate step. Look back through your GUI menu items and see if anything makes sense along these lines. I've been using Synplicity's Identify tool myself so I can't supply much more guidance for chipscope outside this one memory. "Nju Njoroge" <njoroge@stanford.edu> wrote in message news:1132875537.745126.325130@g47g2000cwa.googlegroups.com... > Hello, > > I have a ChipScope ILA and ICON instantiated on the top-level MHS file > like this: > > BEGIN chipscope_icon > PARAMETER INSTANCE = chipscope_icon_0 > PARAMETER HW_VER = 1.00.a > PORT control0 = control0 > END > > BEGIN chipscope_ila > PARAMETER INSTANCE = chipscope_ila_0 > PARAMETER HW_VER = 1.00.a > PARAMETER C_DATA_SAME_AS_TRIGGER = 0 > PARAMETER C_DATA_IN_WIDTH = 256 > PARAMETER C_NUM_DATA_SAMPLES = 2048 > PARAMETER C_TRIG0_TRIGGER_IN_WIDTH = 32 > PARAMETER C_TRIG0_UNIT_MATCH_TYPE = "range with edges" > PORT CHIPSCOPE_ILA_CONTROL = control0 > PORT TRIG0 = chipscope_ila_0_TRIG0 > PORT CLK = sys_clk_s > PORT DATA = chipscope_ila_0_DATA > END > > BEGIN my_pcore > ... > PORT debug_port = chipscope_ila_0_DATA > ... > END > > The issue I'm having is with how the ILA is interpreting the > bit-ordering of the DATA input. chipscope_ila_0_DATA is a 256-bit bus > declared as [255:0] inside my pcore and in its MPD file as well. > Because the waveform output are not making any sense, I set 4 bits in > the bus high. These bits are [157:154] in my debug_port. In the > ChipScope wave viewer, they are bits [221:218]. Now, I suspected that > maybe the ILA is reversing the ordering, but when you switch the order > (bit 255 becomes 0), [157:154] should be [98:102]...What could > ChipScope be doing with the ordering of the bits? > > Thanks, > > NN >Article: 92363
Thanks for that Subroto, I have tried two things. (1) I have removed all the library packages (LEON specific) from my codec core leaving what appears to be an ordinary piece of VHDL code, and just tried compiling that. It has stopped complainig about missing libraries but now I am getting errors like "object std_logic used but not declared". Is this not declared in "ieee.std_logic_1164.all" ? Do you have any idea why I am getting this error? It even had a problem with the entity declaration? (2) I tried pasting all the library packages into the VHDL for the codec core. I searched through the hierarchy to make sure the packages were placed in the correct order. This yielded some success after I commented out as much of the LEON bits I recognized. Do you know how to comment out large sections of VHDL code, other than by doing it line by line? Bryan Subroto Datta wrote: > This may be related to the way in which the VHDL files are ordered. Please > refer to this post as it may be relevant. > > http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/32e686e201ce78ab/57040b828259c463?lnk=st&q=group:comp.arch.fpga+author:subroto&rnum=121&hl=en#57040b828259c463 > > Hope this helps, > Subroto Datta > Altera Corp. > > "Bryan" <altras@yahoo.com> wrote in message > news:0sSdnQzX7ftqbOneRVn-rw@giganews.com... > >I am currently doing a research project that involves simulating a > > oggvorbis codec on quartus2 V5. > > > > My source files were taken from a "oggonachip" porject. They developed > > their system on the LEON platform and simulated it using TSIM. > > > > My problem is on porting the codec core (VHDL code) to Quartus it keeps > > falling over during compilation. The error message states that it cannot > > find the library files which of course I have already added to the > > project. > > > > Can anyone give some insight into why these library files are invisible to > > Quartus? > > > > Any help would be appreciated. > > > > Bryan > > > > > >Article: 92364
Check out XAPP545: Statistical Profiler for Embedded IBM PowerPC http://direct.xilinx.com/bvdocs/appnotes/xapp545.pdf Paul Joseph Samson wrote: > > Martin Schoeberl wrote: > >>HI group, > >> > >>I am searching for some technique which can give me instruction count > >>and cache hits/misses for a configuration created using Xilinx FPGA. > >>I have bitstream corresponding to that configuration. > >>My objective is to get the following statistics such as instruction > >>count and cache hits/misses for any application executing on the system > >>configuration downloaded on FPGA. > >> > > > > That's a very strange question. Instruction count and cache > > misses are related to processors and do not apply to FPGAs > > per se. You can implement a processor as soft-core in the > > FPGA and than it's easy to add all your measurement registers > > in the FPGA. > > I think the poster wants to know these statistics for the embedded > PowerPC processor. This is actually very important for users who want to > optimize their PPC code. Perhaps one of our Xilinx regulars can provide > some hints. > > --- > Joe SamsonArticle: 92365
altras@yahoo.com wrote:
> (1) I have removed all the library packages (LEON specific) from my
> codec core leaving what appears to be an ordinary piece of VHDL code,
> and just tried compiling that.
Did you try simulating it first?
> Do you know how to comment out large sections of VHDL code, other than
> by doing it line by line?
Modelsim : Edit, Comment Selected
Emacs: vhdl-comment-uncomment-region
-- Mike Treseler
Article: 92366
Hi,
I would synchonise the gray output of each domain first using two
register stages in series and apply the gray to binary conversion AFTER
the synchronisation. This will give you a glitch safety good enough for
any industial environment. If the synchronisation does glitch, then only
in the single bit which the receiving clock domain might perceive as
changing. (If you synchronise the converted value, the receiving clock
domain could observe multiple simultaneous changes)
Something like the VHDL pseudo-code below:
signal count_clka..
signal count_clkb..
signal counta_sync1_clkb, counta_sync2_clkb..
signal countb_sync1_clka, countb_sync2_clka..
-- synchronising clka to the clkb domain
process (clkb, rst_n)
variable v_counta_sync_binary...
variable v_countb_clkb_binary...
begin
if (clkb'event and (clkb = '1')) then
-- convert the local counter
v_countb_clkb_binary := f_gray_to_bin(count_clkb);
-- convert the synchronised remote counter
v_counta_sync_binary := f_gray_to_bin(counta_sync2_clkb);
-- do the comparison stuff between v_countb_clkb_binary and
-- v_counta_sync_binary
-- e.g. setting up the new values for full/empty etc.
. . . .
-- update the synchronising stages
counta_sync1_clkb <= count_clka;
counta_sync2_clkb <= counta_sync1_clkb;
. . . .
end process;
-- and of course a similar process for the other direction
Article: 92367Hi all, I just bought an ML403 board (more precisely I bought the PowerPC and MicroBlaze Development Kit) but the 8 GPIO Switches (near to the config address switch) are simply not present on the board. On the PCB I see its emplacement and even the protection resistors ... but no switch. Is it simply an error? Or was there a hardware bug related to these swithes and they were simply deleted? Some reference designs (the web server for example) use these switches. Mehdi.Article: 92368
Some words of wisdom from an old FIFO designer: In a FIFO, you can use any addressing scheme you want, binary, LFSR, Gray, or whatever, as long as the write logic agrees with the read logic. If you want to compare two asynchronous values for identity, make sure they advance in a Gray fashion (i.e. only one bit changes). Otherwise you will see glitches at the output of your dentity comparator. If you Gray-code an incrementing or decrementing binary counter, only one bit will change. But if you use that encoding for anything else ( e.g. for "jumpy" binary values), the output will most likely change several bits per transition, and the Gray advantage is not there. The best way to convert from binary to Gray is to XOR the D-inputs (not the outputs) of adjacent binary counter bits, and register the XOR output. That keeps the two representations always in synch. And, as we know, "Gray" is the inventor's name, and is spelled with an "a". ( I misspelled it once, and never again!) Peter AlfkeArticle: 92369
Hi again! I just found on the docs that these switches are not installed on the ML403 board. Mehdi.Article: 92370
Thank PeteS very much for your help. I got it. Still I want to ask whether there is someone who have successfully boot from flash or have some documents or examples to show the method. Thank you AthenaArticle: 92371
I'm using a Xilinx V2Pro part with the 6.2.03i s/w release and I'm
seeing the
following unconstrained path in the timing report:
================================================================================
Timing constraint: Unconstrained period analysis for net "clk_conv"
Delay: 3.073ns (data path - clock path skew +
uncertainty)
Source: u0clk_trig_if/trig_conv0 (FF)
Destination: u0clk_trig_if/trig_conv1 (FF)
Data Path Delay: 3.073ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: clk_conv rising at 0.000ns
Destination Clock: clk_conv rising at 2.450ns
Clock Uncertainty: 0.000ns
Data Path: u0clk_trig_if/trig_conv0 to u0clk_trig_if/trig_conv1
Location Delay type Delay(ns) Physical
Resource
Logical
Resource(s)
-------------------------------------------------
-------------------
SLICE_X32Y0.YQ Tcko 0.419
u0clk_trig_if/trig_conv0
u0clk_trig_if/trig_conv0
SLICE_X25Y9.BY net (fanout=2) 2.428
u0clk_trig_if/trig_conv0
SLICE_X25Y9.CLK Tdick 0.226
u0clk_trig_if/trig_conv1
u0clk_trig_if/trig_conv1
-------------------------------------------------
---------------------------
Total 3.073ns (0.645ns logic,
2.428ns route)
(21.0% logic,
79.0% route)
In my .ucf file, I have set the period on clk_conv, so I don't see why
I'm getting this unconstrained path. In fact, in another section of the
timing
report, I see:
================================================================================
Timing constraint: TS_clk_conv = PERIOD TIMEGRP "clk_conv" 2.450 nS
HIGH 50.000000 % ;
4 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold
errors)
Thus, I believe the constraint on clk_conv is entered correctly, but
for some reason
the tools appear to ignore the constraint on some of the registers
driven by the
clock.
My Verilog code has the registers trig_conv1 and trig_conv0 in the same
always
block with the proper clock edge. The code seems straight forward, so
I don't
see how the coding style could cause this.
Any ideas?
Thanks
John Providenza
Article: 92372"Thad Smith" <ThadSmith@acm.org> wrote in message news:438b1300$0$245$892e0abb@auth.newsreader.octanews.com... > Frank wrote: > > > I have some digital waveforms, during the idle interval, it's zero, while in > > active > > mode, some patterns are output. This waveform is send through DAC (TI > > DAC290x-EVM) and ADC (Analog AD9218). I am expecting a clean > > zeros during the idle interval, however the ADC output are not. How can I > > correct this problem? > > How does it compare with the analog signal? What is the magnitude of > your error? IF there an AC component to your reading during idle? If > the error is small, it is probably system noise. > > -- > Thad > Thank you Thad. I have a 4 channel oscilloscope and can see three ADC pins only. My digital signal is 20MS/s, 10us idle and 30us active. I channel of DAC is fed into oscilloscope and Q channel to ADC. From what I saw, during idle interval, bits 4,5,6 (0~9) have level changes during the idle and active interval. I am setting DFS/GAIN pin to low for ADC board, and the DAC's I channel waveform lies between -20mV~20mV (idle) ~ 0.8V(active) on oscilloscope.Article: 92373
Ray Andraka <ray@andraka.com> wrote: >This is not safe as presented, as you can't guarantee all the flip-flops >in the counter will be released from reset on the same clock cycle. Then please show how it fails. If bit 0, the LSB, is released last, then it works. None of the other bits can go high until bit 0 goes high. Agree? If bit 1, the next bit, is released last, then the bit 0 goes high first, reset is released, then it works. Agree? Even if two clocks could come into the LSB FF before the release of reset to the next bit, then the count sequence would be: 0000 0001 0000 0001 0010 0011 etc And it works. Same thing for each bit up to the MSB. > In Xilinx >FPGAs, it is easier and more compact to use the SRL16 as a shift >register to delay the reset, and it avoids the reset signal time of >arrival issue inside the reset circuit. I disagree. SRL16's are wonderful for logic, but have horrible metastable charactistics. This really is a metastable problem, so SRL16's are a bad idea. Use slice FFs to make a shift register. Or use a SRL16, and follow it with FFs. -- Phil Hays to reply solve: phil_hays at not(coldmail) dot com If not cold then hotArticle: 92374
>There can be a problem, when DONE is released by the FPGA, if its risetime >is too slow. From what I understand, this is only a problem if there are >more than one FPGA's DONE pins tied together. Who/what gets confused if DONE rises slowly? Slow relative to what? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.
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Compare FPGA features and resources
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