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I guess we have the same questions ! How to compile soft projects How to analyze linking, obj files, linkerscripts, elf content .. Transfering code to external memory Jump to external memory execution I'm looking for answers, I have no answers yet ! "googlie" <suncream777@hotmail.com> a écrit dans le message de news: 1132914552.225700.11800@g14g2000cwa.googlegroups.com... > Maybe you can you use xmd. Look at the documentation pdf for more > information. I'm a student and I'm also trying to set data on ddr but > i'm using powerpc. Can you help with it? >Article: 92276
I will contact you if i have further information. But how can you simple write and read to ddr?Article: 92277
Anyone experienced a bit error in a configuration PROM? Our design contains a XC18V02 that configures a XCV300 in master serial mode. The design has worked flawlessly for many years, but in recent time three individuals have suddenly stopped configuring on power up. The first two where considered "accidents" and the PROM were simply reprogrammed, after which the units (so far) worked flawlessly. When it happened a third time (three strikes and OUT), it became an issue. Read-back through JTAG revealed a single bit error in the PROM. All EEPROMS are from the same batch, marked: XILINX XC18V02 VQ44AEN0117 F1178746A C Has this happened to anyone else?Article: 92278
Not so long ago (about 3-4 years) I had this problem with the XC18V02 configuring a ( I believe) Spartan target. I had single bit errors, too. It seemed to be a batch issue, but it was painful while it lasted. Fortunately, it occurred on my pre-production units so all the faults were within our own lab. Cheers PeteSArticle: 92279
Hello,
I'm currently working on a partial reconfiguration project, but I've got
some problems during the active and assembly phase.
I'm working with ISE 6.3i without any service pack and with ML310. I
also tried other ISE version (e.g. different service packs for ISE 6.3i
or ISE 7.1.04i), but got the same or other error messages. Other people
working in this field also told me to stay with ISE 6.3i.
The first problem occurs in the active implementation phase. When I try
to generate the partial bitstream bitgen produces the following error
message:
Running DRC.
WARNING:DesignRules:367 - Netcheck: Loadless. Net busmacro2/TNET(3) has
no load.
WARNING:DesignRules:577 - Netcheck: The signal GLOBAL_LOGIC1 was
unexpectedly
found to be routed outsite the route area for a Module in partial
reconfiguration mode.
WARNING:DesignRules:577 - Netcheck: The signal GLOBAL_LOGIC1 was
unexpectedly
found to be routed outsite the route area for a Module in partial
reconfiguration mode.
ERROR:DesignRules:10 - Netcheck: The signal "FFake_Gnd" is completely
unrouted.
ERROR:DesignRules:10 - Netcheck: The signal "FFake_Vcc" is completely
unrouted.
ERROR:DesignRules:580 - Blockcheck: The component PWR_VCC_0 was found to be
placed outside of the area infered by a range constraint. It is
likely that a
COMPGRP preference for a Module was modified prior to place instead of
modfifying the range constraint prior to map.
WARNING:Bitgen:25 - DRC detected 3 errors and 3 warnings.
Obviously some signals were not completely routed, but I've got no
warning and no error during PAR.
These signals are used to connect LUTs with the busmacros. The LUTs
create constant '0' and constant '1' signals.
So can someone explain why this error happens and how I can solve this
problem?
I read in a thesis that I should disable DRC (option "-d") in this phase
to get the bitstreams. If I do so, I get the following error message in
the assembly phase (also during PAR):
FATAL_ERROR:Guide:basgitaskphyspr.c:372:1.28.20.3:286 - A previous
module has
placed the comp: user_add/PWR_VCC_0 on the same site: SLICE_X43Y159
where the
current guide comp PWR_VCC_155 also needs to be placed. There exists at
least two guide files that contain logic 0/1 signals being driven
from the
site location. Process will terminate. To resolve this error, please
consult the Answers Database and other online resources at
http://support.xilinx.com. If you need further assistance, please open a
Webcase by clicking on the "WebCase" link at http://support.xilinx.com
OK, what can I do to avoid that these components are placed on the same
site?
Thanks in advance,
David
Article: 92280Seems I was a bit quick to post this question, there was a thread about such an issue some years back (XC18VXX PROM Corruption). It seems Skyhawk172L (nice plane by the way, me I fly Pipers mostly...) had identical problems. I also had a '1' flipped to a '0'. No conclusive answer as to what might be the cause though.Article: 92281
How do I create an embedded subsystem from the ISE? I have done it from EDK and exported it to ISE and Back again it works fine. But if I Create a new module of type "Embedded Processor" in ISP I don't get it to work. Here is what I did. Created a project in ISE with a topmodule called top.vhd. Created a new submodule of type "Embedded Prosessor" called MyBlaze. (from ISE) XPS opened and I created a prosessorsystem containing: 1 MicroBlaze, 2 lmb_bram_if_cntlr, 1 bram block and 2 gpios. With the external ports: Clock_in, Reset_in, opb_buttons_GPIO_in and opb_leds_GPIO_d_out. If I put the prosessorsystem as a submodule in my design I get mainly these errors: "Undefined symbol 'Clock_in'", "Undefined symbol 'Reset_in'", "Undefined symbol 'opb_buttons_GPIO_in'", "Undefined symbol 'opb_leds_GPIO_d_out'" and "IN mode Formal Clock_in of MyBlaze with no default value must be associated with an actual value." Can anybody help me? RaymondArticle: 92282
Okashii wrote: > Yes, it is done by a right shift :) But I want to do normal non-power-of-2 > division. I heard it is pretty nasty. > > "Stephane" <stephane@nospam.fr> wrote in message > news:dm6kv2$ngt$1@ellebore.extra.cea.fr... > > Okashii wrote: > >> Hi, I realize that using XST division and mod is only possible when the > >> divisor is power of 2. May I know whether is there any way of getting > >> around this problem? Does the usage of std_numeric solve this problem, or > >> do I have to write my own algorithm to do this? Is there any predefined > >> package somewhere that can do this for me? Division in general is hard, but often your requirements may make it easier, for example, you might want to divide by a constant, or perhaps you have a lot of clock cycles to use (or you don't care about the speed) etc. Often one attempts to change the system architecture to avoid the need for division altogether. What are you trying to do? Regards, AllanArticle: 92283
Hello, I am have a verilog project which runs on both an altera board, a xilinx board and the (excellent) Icarus simulator. To keep my code to a minumum I want to use conditional compilation e.g. to cater to the different i/o on the 2 boards or use proprietary features of the synthesis tools. I can pass a macro value to Icarus on the command line, which I can ifdef against in my code, but I cannot work out how to do the same in either Quartus or ISE (latest free versions) so that in my code I could say things like `ifdef XILINX .... If there are predefined macros, both vendors are keeping them pretty close to their chest. I can't be the first person facing this but I have been scratching my head over it for a couple of weeks. How do other people solve this? Cheers MarkArticle: 92284
"Martin Schoeberl" <mschoebe@mail.tuwien.ac.at> writes: > So I will bite the bullet and use two vendor specific VHDL files. > However, there is one open issue: I want the memory size be > configurable via a generic. This is possible with Alteras > altsyncram. > > For Xilinx I only know those RAMB16_S9_S36 components where > the memory size is part of the component name. Is there a > a Xilinx block RAM component where I can specify the size? > Nope. I've been beating them up on this for years now - they just can't seem to grasp why I wouldn;t want to use Coregen for all my RAM needs! Grrr! (Another) Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.trw.com/conektArticle: 92285
"Martin Schoeberl" <mschoebe@mail.tuwien.ac.at> writes: > >> > >>For Xilinx I only know those RAMB16_S9_S36 components where > >>the memory size is part of the component name. Is there a > >>a Xilinx block RAM component where I can specify the size? > >> > > NO, but you can use GENERATE (assuming VHDL) to switch between > > different bram geometries Aurelian > > > Really, that's it? Not very comfortable - a plus for Quartus. > > Perhaps one in this group has already done this coding effort > and can provide the VHDL file? > I have done some, although I haven't covered all the various options - unfortunately within work time, so I can't post them :-( I based it on the ideas in David Kessner's Free-IP RAM library if that helps... I can't seem to find it out there on the web anymore. The wayback machine has it though... http://web.archive.org/web/20040519060445/http://www.free-ip.com/ http://web.archive.org/web/20040605072636/www.free-ip.com/ramlib/index.html Sorry to be no more help! Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.trw.com/conektArticle: 92286
coregen will give you a core that you can simulate with XilinxCoreLib. HTH Okashii wrote: > I'm trying to simulate the behaviour of integer division in C, so its 32bit > by 32bit division with both operands unknown. I don't care about speed or > number of clock cycles though. Do you know of any links or reference where I > can find the algorithm for that? Thanks in advance. > > <allanherriman@hotmail.com> wrote in message > news:1132924046.370605.46860@z14g2000cwz.googlegroups.com... > >>Okashii wrote: >> >>>Yes, it is done by a right shift :) But I want to do normal >>>non-power-of-2 >>>division. I heard it is pretty nasty. >>> >>>"Stephane" <stephane@nospam.fr> wrote in message >>>news:dm6kv2$ngt$1@ellebore.extra.cea.fr... >>> >>>>Okashii wrote: >>>> >>>>>Hi, I realize that using XST division and mod is only possible when >>>>>the >>>>>divisor is power of 2. May I know whether is there any way of getting >>>>>around this problem? Does the usage of std_numeric solve this problem, >>>>>or >>>>>do I have to write my own algorithm to do this? Is there any >>>>>predefined >>>>>package somewhere that can do this for me? >> >>Division in general is hard, but often your requirements may make it >>easier, for example, you might want to divide by a constant, or perhaps >>you have a lot of clock cycles to use (or you don't care about the >>speed) etc. >> >>Often one attempts to change the system architecture to avoid the need >>for division altogether. >> >>What are you trying to do? >> >>Regards, >>Allan >> > > >Article: 92287
Hi, I'm trying to use PLB GEMAC in EDK 7.1, but I don't manage to make standalone application test (provided in EDK) work. As BSB doesn't support PLB GEMAC, we attached it to the rest of the system manually. To do that we looked at the PLB GEMAC example of the ml300 board. AS we do not have a 62.5 MHz in our board we used a 125 MHz external clock, and then we obtained the 62.5 MHz to feed the dcm required by the plb gemac ip. We tried to keep the signal as 'clean' as possible. Is there anyone who have faced the same problem? I would appreciate any suggestion! Thanks a lot MarcoArticle: 92288
I need some information on the type of chips (FGPA, ASICetc) that sits on a mobile phone. We have to implement an algorithm on a mobile phone, and we are not sure what are the kinds of chip configurations available. My early research tells me that FGPA's are reconfigurable but are energy intensive, and can be boarded only in standard size. Whereas ASIC chips are not reconfigurable..but they consume low energy..resulting in higher battery lifes. Are there more kind of implementations? Are there some good internet resources that can give me a good introduction. I would also appreciate if someone could tell me some other relevant usenet groups for such kind of discussions. RohitArticle: 92289
Hi,
I've read the VHDL FAQ 4.2.21 "How to Convert Between Enumeration and
Integer Values". Anyway, I have questions to these function:
function slv2pec (
signal id : std_logic_vector(2 downto 0))
-- signal id : std_logic_vector(natural range <>))
return pattern_edge_comb_t is
begin
-- Error: No feasible entries for infix operator "<".
-- assert (pattern_edge_comb_t'high < 4) -- Line 89
-- report "Conversation error (wrong assumptions)."
-- severity error;
return pattern_edge_comb_t'val(to_integer(unsigned(id))); --L91
end function slv2pec;
with:
type pattern_edge_comb_t is (
unknown,
and_comb,
or_comb,
xor_comb);
I would like write the signal as unconstrained, but I get a syntax
error on this. Furthermore the assert is very usefull.
** Error: (89): No feasible entries for infix operator "<".
** Error: (89): Type error resolving infix expression "<".
Last, I get the synthesis error using xst:
line 91: Attribute is not authorized : 'val'.
How can I resolve this problems?
Thanks and Regards,
Olaf
Article: 92290
Hi,
EDK does all this stuff that you want on the background and u
can just keep clicking buttons...Here are the answers to your questions
.=2E.
1 ) How to compile soft projects --
I guess you know this..in the EDK GUI, just hit
the applications tab and add a software project (add all the source and
the header files )
The other way is when you create is a simple EDK
7=2E1 project, it creates two sample Software Projects (TestApp_Memory
and TestApp_Peripheral) ..So you can just replace the the source files
in either of the projects
2) How to analyze linking, obj files, linkerscripts, elf content
.=2E
I dont' know the complete answer to this
question but..I mean you have the source for the Linker Script, and
your own sources.. I dunno if there is any other specific reason that
you need the content of the elf file for.
3) Transferring code to external memory
This is not a big deal at all.. When hit the
applications tab and highlight your software project, there will be an
option which says Generate Linker Script. So just click on that and a
Window will pop up... In that window change all the contents to
DDR_SDRAM ( or whatever your external memory ) ..Before you do this
make sure that you have DDR ( or external memory in your system )
4) Jump to external memory execution
Thats what u do in the Linker Script....
Feel free to e-mail me in case you have any other
questions...
--
Parag
sjulhes wrote:
> I guess we have the same questions !
>
> How to compile soft projects
> How to analyze linking, obj files, linkerscripts, elf content ..
> Transfering code to external memory
> Jump to external memory execution
>
> I'm looking for answers, I have no answers yet !
>
>
> "googlie" <suncream777@hotmail.com> a =E9crit dans le message de news:
> 1132914552.225700.11800@g14g2000cwa.googlegroups.com...
> > Maybe you can you use xmd. Look at the documentation pdf for more
> > information. I'm a student and I'm also trying to set data on ddr but
> > i'm using powerpc. Can you help with it?
> >
Article: 92291
Hi,
Do you want to write to the DDR from any of the Buses (OPB , PLB )
or from the PowerPC
--
Parag
googlie wrote:
> I will contact you if i have further information. But how can you
> simple write and read to ddr?
Article: 92292
Hi,
if I synthese the followng code (substract using two's-complement and
adder) using xst and then have a look to the RTL schematic, the co
output is on ground and a 16bit adder is infered. The carry out (co)
is the interesting signal for me. Did I wrote wrong code (TB not yet)?
How to correct it? BTW, is there a way to 'tune' this entities
especially to avoid such castings and conversations?
Thanks
Olaf
---8<---
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is
generic (
WIDTH : natural := 16);
port (
a, b : in std_logic_vector(WIDTH-1 downto 0);
sum : out std_logic_vector(WIDTH-1 downto 0);
co : out std_logic);
end entity adder;
architecture rtl of adder is
signal tmp : std_logic_vector(WIDTH downto 0);
signal a_i, b_i : natural range 0 to 2**WIDTH;
begin
a_i <= to_integer(unsigned(a));
b_i <= to_integer(unsigned(b));
tmp <= std_logic_vector(to_unsigned(a_i + b_i, tmp'length));
sum <= tmp(WIDTH-1 downto 0);
co <= tmp(WIDTH);
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity subtractor is
generic (
WIDTH : natural := 16);
port (
a, b : in std_logic_vector(WIDTH-1 downto 0);
diff : out std_logic_vector(WIDTH-1 downto 0);
co : out std_logic);
end entity subtractor;
architecture rtl of subtractor is
-- two's-complement
signal b_2c : std_logic_vector(WIDTH-1 downto 0);
begin
b_2c <= std_logic_vector(to_unsigned(to_integer(unsigned(not b)) +
1, b_2c'length));
adder_i : entity work.adder
generic map (
WIDTH => WIDTH)
port map (
a => a,
b => b_2c,
sum => diff,
co => co);
end architecture rtl;
Article: 92293Hi all, is there a way to access the phase accumulator in Xilinx DDS 5.0? (preferably from VHDL) I'd like to determine the carrier phase between two modulated signals by phaselocking an NCO on each one and then subtracting the phase accumulators. Given that there is a great DDS already, I dislike reinventing it just to tap an internal signal. BTW the register interface is nice if I want to setup everything with a microcontroller. But --- in a pure hardware environment it is clumsy to multiplex frequency word and phase modulation to a 32 bit data bus + address line + WE, knowing the first thing to happen is that they will be demultiplexed again into different registers. In addition, the update rates are halved and potentially simultaneous frequency/phase updates need to be scheduled. (Options for DDS 5.1???) best regards, GerhardArticle: 92294
Hi folks, We have laid out a board for XC4VFX20-10FF672, but can't get a single sample. The local distributors have been promising us parts for ages, but now are saying that they can't get any... The design uses MGTs, but at this point we will accept samples even with the non-functioning MGTs as soon as everything else is working... Can anyone help please? It is a very important project for us. Thanks, -- ======================= Mikhail Matusov Hardware Design Engineer Square Peg Communications Tel.: +1 (613) 271-0044 ext.231 Fax: +1 (613) 271-3007 http://www.squarepeg.caArticle: 92295
On Fri, 25 Nov 2005 21:39:32 -0800, "Okashii" <nordicelf@msn.com> wrote: >I'm trying to simulate the behaviour of integer division in C, so its 32bit >by 32bit division with both operands unknown. I don't care about speed or >number of clock cycles though. Do you know of any links or reference where I >can find the algorithm for that? Thanks in advance. Since you don't care about speed or number of clock cycles: 1) Set a counter to zero 2) Copy the dividend to an Accumulator 3) If Accumulator is less than divisor, go to step 7 4) Subtract divisor from Accumulator 5) Increment counter 6) Goto step 3 7) Counter is Quotient, Accumulator is remainder This is called division by repeated subtraction. Are you still sure that you don't care about speed :-) If you want more precision, you can extend the accumulator at the LSB end, and scale the divisor (divide it by a convenient constant) as well. For example, you could add 12 zero bits at the LSB end of the Accumulator, and divide the divisor by 4096 (which requires exactly zero logic and zero time). The Counter also has to be 12 bits longer, and the algorithm will take 4096 times as long to run (which you don't care about). The result will be 12 bits more accurate. There will be a binary point between the 13th and 12th bit (from the LSB end) of the counter. The stuff to the left of the binary point is the integer part of the quotient, and the stuff on the right is the fractional part. The remainder in the accumulator also has this format. Philip =================== Philip Freidin philip.freidin@fpga-faq.org Host for WWW.FPGA-FAQ.ORGArticle: 92296
i recently bought the v4 extreme DSP development kit and am trying to get a linux PCI device driver for it. up till now nallatech and xilinx have been very unresponsive (im at a university!). I was wondering if someone on the board could send me one if they have it... If you have a device driver for the BenOne motherboard card, that should do as well. thanksArticle: 92297
Yes, it is done by a right shift :) But I want to do normal non-power-of-2 division. I heard it is pretty nasty. "Stephane" <stephane@nospam.fr> wrote in message news:dm6kv2$ngt$1@ellebore.extra.cea.fr... > Okashii wrote: >> Hi, I realize that using XST division and mod is only possible when the >> divisor is power of 2. May I know whether is there any way of getting >> around this problem? Does the usage of std_numeric solve this problem, or >> do I have to write my own algorithm to do this? Is there any predefined >> package somewhere that can do this for me? > > do you know how a division by a power of two is done in hardware?Article: 92298
I'm trying to simulate the behaviour of integer division in C, so its 32bit by 32bit division with both operands unknown. I don't care about speed or number of clock cycles though. Do you know of any links or reference where I can find the algorithm for that? Thanks in advance. <allanherriman@hotmail.com> wrote in message news:1132924046.370605.46860@z14g2000cwz.googlegroups.com... > Okashii wrote: >> Yes, it is done by a right shift :) But I want to do normal >> non-power-of-2 >> division. I heard it is pretty nasty. >> >> "Stephane" <stephane@nospam.fr> wrote in message >> news:dm6kv2$ngt$1@ellebore.extra.cea.fr... >> > Okashii wrote: >> >> Hi, I realize that using XST division and mod is only possible when >> >> the >> >> divisor is power of 2. May I know whether is there any way of getting >> >> around this problem? Does the usage of std_numeric solve this problem, >> >> or >> >> do I have to write my own algorithm to do this? Is there any >> >> predefined >> >> package somewhere that can do this for me? > > Division in general is hard, but often your requirements may make it > easier, for example, you might want to divide by a constant, or perhaps > you have a lot of clock cycles to use (or you don't care about the > speed) etc. > > Often one attempts to change the system architecture to avoid the need > for division altogether. > > What are you trying to do? > > Regards, > Allan >Article: 92299
Hey Xilinx, before you bought RocketChips you should have checked their company website better. They had some photos of their recent work there. http://www.ov-10bronco.net/users/merlin/Flight/kaboom.htm "...we have LOS of signal..."
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