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Messages from 92600

Article: 92600
Subject: Xilinx FPGA - Behaviorial Model Transferred Instead of Place-and-routed Model
From: "Chloe" <chloe_music2003@yahoo.co.uk>
Date: 2 Dec 2005 00:37:54 -0800
Links: << >>  << T >>  << A >>
Calling all FPGA experts!

I'm currently using Xilinx ISE 7.1i with the ModelSim XE III/Starter
6.0a simulator. The FPGA which I am downloading my design onto is a
Spartan IIE (it's on the Spartan IIE LC Development Kit, with an
XC2S300E device).

After synthesizing, implementing and programming the design onto the
FPGA, I tested the outputs of the FPGA on the development kit using a
digital oscilloscope. However, I was not getting the signals I wanted.
After simulating the design on ModelSim, and comparing the simulated
outputs with the actual FPGA outputs, I realised that the behavioral
model of the design was somehow transferred onto the FPGA, instead of
the place-and-routed model.

I checked the synthesis report, but there were no errors. There were
some warnings, but they were unimportant (certain ports were assigned
but not used), thus, neglected at the moment. There were also no timing
violations. I also checked all the reports under "Implement Design",
and there were no errors.

Can anyone tell me why the behavioral model was transferred onto the
FPGA instead of the place-and-routed model? Is that even possible? Can
anyone advise me on the methods of overcoming this problem?

I'd be happy to provide any extra information you need.

Thanks very much in advance. 

Regards,
Chloe


Article: 92601
Subject: Re: Ethenet Multiplexers
From: "Simon Peacock" <simon$actrix.co.nz>
Date: Fri, 2 Dec 2005 22:09:30 +1300
Links: << >>  << T >>  << A >>
There's no real point when you can buy a switch IC for $20.  Its less than
the cost of the FPGA and includes the PHY.

We actually use a Marvell ... which will even allow clocks to be sourced
from the FPGA instead of the other way around.  Its so simple and gives 4
ports + CPU + FPGA... no need to even worry.  That way you don't have to
worry about filtering, forwarding, VLANs, priorities etc.

P.S. Almost all Ethernet switching IC's are under NDA as the companies are
paranoid about someone stealing their design.

Simon


<kedarpapte@gmail.com> wrote in message
news:1133417075.151227.174060@g44g2000cwa.googlegroups.com...
> Hi All,
>
> Can anyone please tell me about some good links or documents paprs etc.
> on Implementing Ethernet Multiplexers using FPGAs
>
> THanks & Regards
> Kedar
>



Article: 92602
Subject: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
From: "Simon Peacock" <simon$actrix.co.nz>
Date: Fri, 2 Dec 2005 22:14:10 +1300
Links: << >>  << T >>  << A >>
You will probably find that the 'Carry' uses the dedicated Carry logic.. it
therefore can support only one function.
Two support more.. one has to be done in LUT's that makes it harder.

You could build your own by hand coding LUT's... its a bit of a pain but tit
can be more optimal than writing A <= A + B; in VHDL.

Simon



<juendme@yahoo.com> wrote in message
news:1133474129.086453.274910@g14g2000cwa.googlegroups.com...
> Such pins do exist (see Table 1.; signals A_SIGNED and B_SIGNED),
> although I have no idea what exactly those signal do (thanks to
> incomplete documentation). Because if you look into any digital design
> textbook, you'll see that the adder/subtracter circuit is exactly the
> same for both signed and unsigned numbers. The only difference is that
> carry is not an indication of the error in the result for signed
> numbers, but you need overflow.
>
> And going back to table 2, what are the 2 extra bits in the result
> (P=Q+2) in rows 2 and 3? Carry and ....? Could it be overflow? But then
> why isn't P=Q+2 an option when both inputs are signed?
> Xilinx, thanks for incomplete and confusing documentation!
>
> In contrast, Altera's lpm_add_sub readily provides both carry and
> overflow outputs. It also provides a parameter to specify whether the
> numbers are signed or unsigned, and explains what effect that paramter
> has on the operation of the circuit (it only affects the behavior of
> the overflow output, nothing else).
>



Article: 92603
Subject: Virtex 4 IDELAY implementation
From: tky127@hotmail-dot-com.no-spam.invalid (kyeyk)
Date: Fri, 02 Dec 2005 03:15:43 -0600
Links: << >>  << T >>  << A >>
Hi,

I'm currently doing some tests on an ML461 board, using IDELAY to
shift in some DDR signals. I am shifting 80 signals in groups of 8.
Unfortunately, some signals do not get shifted, i.e. some of the
IDELAY module do not seem to respond to INC & CE. I'm seeing this
in chipscope. I have tried (1) instantiating a single IDELAYCTRL, then
let the tool replicate the rest and (2) instantiating all IDELAYCTRL
and manually assigning them to the 
appropriate regions. It didn't help. 

Has anyone encountered such behaviour?

I also found this on the xilinx website:
http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=20125

Does this mean that I have to invert the clock going into the IDELAY
block?

Thanks in advance


Article: 92604
Subject: Re: Download old Quartus versions (4.0, 4.1)
From: "Simon Peacock" <simon$actrix.co.nz>
Date: Fri, 2 Dec 2005 22:47:28 +1300
Links: << >>  << T >>  << A >>
The problem is if there is a sloppy timing that might cause a problem,
changing the design will only bring it out.. Murphy's law.. oh.. and it also
adds... you will only find the sloppy timing 5 minutes before the shipping
dead line.

Or, of course, the design won't work at a particular temperature and
voltage...

Simon

P.S.. I only have 4.0 and 4.2 sp 1 :-)

<juendme@yahoo.com> wrote in message
news:1133458844.747074.91060@g49g2000cwa.googlegroups.com...
> I so love it when people give advice that the original poster has
> already acknowledged is not needed, instead of answering the question
> that was posed!
>
> I'm also interested in downloading the older versions for performance
> comparison purposes.
> Can someone now answer the original question, or is performance
> comparison across software versions also a bad idea.
>
> BTW, in my experience, Altera's licenses cover all versions of software
> released before the expiry date.
>



Article: 92605
Subject: Re: Help : Code works in synthesizer (silos), but warnings w/ webpack
From: "gallen" <arlencox@gmail.com>
Date: 2 Dec 2005 01:49:02 -0800
Links: << >>  << T >>  << A >>
The only verilog book that I use these days is the Thomas and Moorby
book.  It's very expensive and it wouldn't be particularly useful to
you for synthesis purposes.  It's really about the language itself
which was designed for simulation.  Synthesis is a different ball game
entirely.

Here's some general advice about synthesis:

If you can't visualize the hardware being produced, you probably
shouldn't code it yet.  Remember that behavioral models probably won't
work, and even if they do, they won't work well, or be even close to
optimal.

The best place to start for learning synthesis, is to make a simple
combinational circuit, followed by a complex one, followed by a simple
register, followed by a state machine.

A couple simple combinational circuits might be:
assign out = a & b;  //and AND gate
assign out = s ? a : b; //a 2 to 1 MUX
assign out[3:0] = a[2:0] + b[2:0]; //a 3-bit adder

A complex combinational block uses an always statement for
combinational purposes:
reg out;
always @ (ina or inb or inc or ind)
begin
  out = 1'b0;
  if(ina) out = inb;
  if(inc) out = ind;
end

A simple register (or flip-flop) is like this:
reg q;
always @(posedge clk)
  q <= d;
or with reset:
reg q;
always @(posedge clk or negedge rst)
  if(!rst)
    q <= 1'b0;
  else
    q <= d;

I won't give an example state machine, but what I can tell you is that
in documents such as the XST user guide they explain very clearly how
to make them.  Really all they are though is one set of flops, and two
blocks of combinational logic:
combinational logic takes outputs of flops and state machine inputs as
inputs and outputs flops next state
flops register that data
other combinational logic takes output of flops and optionally state
machine inputs as inputs and outputs needed signals.

With those basic constructs almost anything synthesizable is possible.
Other synthesizable constructs are for loops that have a finite number
of iterations (though, personally I've never used this).

It's worth noting that the following combinational constructs are not
synthesizable:
/ -- division is nearly impossible to do combinationally, unless it's a
divide by 2^n
<< and >> -- these are only synthesizable if the shift is by a constant
amount.  These can be done non-constant in completely combinational
logic; this is called a barrel shifter; but it is not supported by
synthesizers.

Here is the XST User guide:
http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/xst/xst0001_1.html

It has a lot of good information.  I particularly recommend the HDL
Coding Techniques Section:
http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/xst/xst0012_5.html#wp234748

Again, good luck.  I wish you the best,
Arlen


Article: 92606
Subject: Re: FPGA : Decimation Filter Implementation
From: "Simon Peacock" <simon$actrix.co.nz>
Date: Fri, 2 Dec 2005 22:53:49 +1300
Links: << >>  << T >>  << A >>
For starters.. you shouldn't mention "reverse-engineer" and "Xilinx core
generator" in here.. this is a monitored group by both Altera and Xilinx...
both will not appreciate it.
(not to mention those of us who make our living from the IP business)

Simon

"bijoy" <pbijoy@rediffmail.com> wrote in message
news:ee927da.-1@webx.sUN8CHnE...
> Hello
>
> I am trying to reverse engineer the
>
> decimation filter core provided by xilinx core-generator.
>
> My requirements are
>
> 1. Input data rate : 8.8 M Hz 2. Decimation ratio : 2 3. Number of taps :
32 4. input and coefficeints width:16 5. symmetric filter Xilinx core
generator uses
>
> One multiplier
>
> Two Block ram to store coefficient and input data clock frequency required
: 70 MHz
>
> How does they achieve this
>
> I am not able to find out a structure that can expoit both decimation and
symmetry of the filter to reduce the multipliers to 1 and clock frequency to
70 MHz.
>
> I want to store the coefficient and input data in block ram so that i can
save slice usage.
>
> Can any one suggest any ideas ?
>
> Thanks bijoy



Article: 92607
Subject: Re: Multi-layer switch network?
From: "Davy" <zhushenli@gmail.com>
Date: 2 Dec 2005 01:59:38 -0800
Links: << >>  << T >>  << A >>
Hi Kolja,

Thank you for your help :-)
But it seems it is hard to understand the idea.

May you please direct me to some reference paper/article about this
subject?

Best regards,
Davy


Article: 92608
Subject: Re: Ethenet Multiplexers
From: kedarpapte@gmail.com
Date: 2 Dec 2005 02:03:57 -0800
Links: << >>  << T >>  << A >>

Hi Simon

Thanks for your reply

can I get the data sheets of such ICS I tried searching on net but it
is not easily available

Regards,
Kedar


Article: 92609
Subject: Re: Ethenet Multiplexers
From: "Simon Peacock" <simon$actrix.co.nz>
Date: Fri, 2 Dec 2005 23:08:35 +1300
Links: << >>  << T >>  << A >>
you should read the message.. its all under NDA.. you have to apply to
Marvell ..
http://www.marvell.com/products/switching/linkstreet/index.jsp

That's their web site.


<kedarpapte@gmail.com> wrote in message
news:1133517837.862016.20540@z14g2000cwz.googlegroups.com...
>
> Hi Simon
>
> Thanks for your reply
>
> can I get the data sheets of such ICS I tried searching on net but it
> is not easily available
>
> Regards,
> Kedar
>



Article: 92610
Subject: Re: Ethenet Multiplexers
From: kedarpapte@gmail.com
Date: 2 Dec 2005 02:51:20 -0800
Links: << >>  << T >>  << A >>
thanks Simon
I had read the message but I was asking in general not specific to
Marvell
Thanks once again

Regards
Kedar


Article: 92611
Subject: Re: Download old Quartus versions (4.0, 4.1)
From: "henn_xxx@trispel.org" <henn2005@trispel.org>
Date: 2 Dec 2005 03:01:49 -0800
Links: << >>  << T >>  << A >>
Hi,

try a look at ftp.altera.com/outgoing/release

You can connect as guest. (E.g. if you are using windows, simply enter
"ftp.altera.com/outgoing/release" on the explorer path). There you will
find lots of old (also 4.0 and 4.1 .. version) and the most up-to-date
version, even earlier than the CD shipments.

Hope this is what you are looking for,

Henning


Article: 92612
Subject: Re: Curious about FPGAs
From: allanherriman@hotmail.com
Date: 2 Dec 2005 03:38:49 -0800
Links: << >>  << T >>  << A >>
clemenr@wmin.ac.uk wrote:
> Hi. I'm curious about exactly what sort of things are done with FPGAs.
> Is the main reason for their use the additional speed over using a
> generic processor, due to clock rate and/or parallelism? Is it mainly
> to make cheaper low-run products? What sort of things can be done with
> them?
>
> As an example, it would be possible to build a digital reverberation
> unit using a *REALLY BIG* FIR filter. If the reverb impulse response
> lasted for say 15 seconds requiring M samples to be buffered, then
> assuming that x[n] is the current sample and that suitable b[0..M]
> coefficients can be found, then the reverb could be calculated as:
>
> reverb[n] = SUM {i=0 to M} x[n - (M - i - 1)] * b[i]
>
> This could be done in fixed point arithmetic.
>
> Given that 15 seconds of 44.1khz sound requires 15 * 44100 = 661500
> past input samples to be cached along with the 661500 b[] coefficients,
> would this be feasible with current FPGAs?

No.  You are trying to do about 29 GMACs.  The *computations* are
possible in 100-200 hardware multipliers, but the memory bandwidth will
kill you.  (661500 coeffs won't fit in the on-chip ram, so you'll have
to use external ram.)  Assuming 16 bit coefficients, the coeff
"bandwidth" is about 470 Gb/s.  You can't do that (yet).

Ask this same question in comp.dsp, and you'll be told there are
frequency domain methods (patented by Lake (now Dolby)) that greatly
reduce the amount of computation required for reverb.  You still might
end up using an FPGA, of course.

Regards,
Allan


Article: 92613
Subject: Spartan3E availability update
From: "Antti Lukats" <antti@openchip.org>
Date: Fri, 2 Dec 2005 13:45:33 +0100
Links: << >>  << T >>  << A >>
Hiho

Spartan3E status:

1) Avnet has sold 400 (maybe a few hundred more) of their 69USD XC3S100E 
based starterkit, now they have 18 in stock if that is sold out then 
leadtime for next order is: 26 weeks !

2) All Spartan3e devices have been removed from Avnet online inventory 
search ?

3) Cesys GmbH can ship from stock 500E based boards
http://www.cesys.com/index.php?language=en&doc=advanced&docparams=USB3FPGA&menuparams=53

4) Xilinx Spartan3e kits are coming... at Christmas?

5) Spartan3 100e 'sample' pack pictures are online at nuhorizon!
I assumed that this product/info remains confidential until officially 
launched by Xilinx, well here is at least the pictures

http://www.nuhorizons.com/products/xilinx/spartan3e/samplepack.html

6) nuhorizon part search on XC3s return page unavailable

Antti



Article: 92614
Subject: Re: Slow FIFO using external SRAM
From: David Tweed <dtweed@acm.org>
Date: Fri, 02 Dec 2005 13:19:56 GMT
Links: << >>  << T >>  << A >>
dp wrote:
> If the purpose is to have the FIFO (and not to build it, say,
> for learning or economic purposes), you can use one of
> the 72XX (IDT used to make them) FIFO chips. They have
> the R/W pointer circuitry inside etc., really convenient
> to use - and you will need no memory address lines out
> of the FPGA, nor will the data necessarily go through it
> (that is, you can just handle the full/empty flags and
> the R/W strobes - and there also is a half full flag).

Yes, but they are of limited size and rather expensive.

I once needed to delay a T1/E1 signal (all three states,
so 1.544 or 2.048 million bit-pairs per second) by up to
tens of milliseconds, continuously adjustable. I ended up
with an external cheap generic CMOS SRAM (128K x 8) and
an Actel ACT2 FPGA to control it. Most of the FPGA runs
synchronously with the output clock at 4x the data rate
(6.176 or 8.192 MHz). For the input data, there's a 4 x 2
shift register that runs at the input clock rate and a
block of logic that passes memory write requests to the
output clock domain.

With 16 clocks per read/write pair, there was plenty of
time to work with and resolve conflicts between reads and
writes. I even did all of the address arithmetic using a
2-bit wide serial data path to save logic.

-- Dave Tweed

Article: 92615
Subject: Re: Virtex-4 FX60 based products are already shipping now !
From: francesco_poderico@yahoo.com
Date: 2 Dec 2005 05:42:04 -0800
Links: << >>  << T >>  << A >>
Antii,
it looks very interesting, but I do not beleave that.
last week we had a meeting with a Silicas sales man and he told us that

FX12 production device (I.e. not a CES part), likely to be on general
availability end of Q1'06.
FX20 production device (i.e. not CES), likely to be on general
availability MidQ3'06
FX40 production device (i.e. not CES), likely to be on general
availability Q3'06

Francesco


Antti Lukats wrote:
> As of PLDA they are shipping __now__ their XpressFX board that has FX60 chip
> on board! Interesting though that there is no pricing or direct order for
> the XpressFX board so maybe PLDA is lying and they are not actually able to
> ship.
> 
> http://xilant.com/content/view/18/1/
> 
> Antti


Article: 92616
Subject: Re: Virtex-4 FX60 based products are already shipping now !
From: "Antti Lukats" <antti@openchip.org>
Date: Fri, 2 Dec 2005 14:53:38 +0100
Links: << >>  << T >>  << A >>
<francesco_poderico@yahoo.com> schrieb im Newsbeitrag 
news:1133530924.724151.161830@z14g2000cwz.googlegroups.com...
> Antii,
> it looks very interesting, but I do not beleave that.
> last week we had a meeting with a Silicas sales man and he told us that
>
> FX12 production device (I.e. not a CES part), likely to be on general
> availability end of Q1'06.
> FX20 production device (i.e. not CES), likely to be on general
> availability MidQ3'06
> FX40 production device (i.e. not CES), likely to be on general
> availability Q3'06
>
> Francesco
>

well yes that matches what I know as well: no MGT silicon via distribution 
til Q3'06 so thats exactly why those pictures of the FX60 based boards are 
so interesting. I know there are several compoanies with ready PCB waiting 
very badly for the FX60, and not getting them and not getting info when 
those parts could be available. And still PLDA claims immediate availability 
of their boards fitted with FX60!

Antti 



Article: 92617
Subject: Re: Spartan3E availability update
From: "Raymund Hofmann" <filter002@desinformation.de>
Date: Fri, 2 Dec 2005 15:26:17 +0100
Links: << >>  << T >>  << A >>

I guess it's because of their Problems with the DCM / DFS in stepping 0

Raymund Hofmann

"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag 
news:dmpfou$5am$03$1@news.t-online.com...
> Hiho
>
> Spartan3E status:
>
> 1) Avnet has sold 400 (maybe a few hundred more) of their 69USD 
> XC3S100E based starterkit, now they have 18 in stock if that is sold 
> out then leadtime for next order is: 26 weeks !
>
> 2) All Spartan3e devices have been removed from Avnet online inventory 
> search ?
>
> 3) Cesys GmbH can ship from stock 500E based boards
> http://www.cesys.com/index.php?language=en&doc=advanced&docparams=USB3FPGA&menuparams=53
>
> 4) Xilinx Spartan3e kits are coming... at Christmas?
>
> 5) Spartan3 100e 'sample' pack pictures are online at nuhorizon!
> I assumed that this product/info remains confidential until officially 
> launched by Xilinx, well here is at least the pictures
>
> http://www.nuhorizons.com/products/xilinx/spartan3e/samplepack.html
>
> 6) nuhorizon part search on XC3s return page unavailable
>
> Antti
>



Article: 92618
Subject: Re: Download old Quartus versions (4.0, 4.1)
From: cs_posting@hotmail.com
Date: 2 Dec 2005 06:42:44 -0800
Links: << >>  << T >>  << A >>
> try a look at ftp.altera.com/outgoing/release

> There you will find lots of old (also 4.0 and 4.1 .. version) and the most up-to-date
> version, even earlier than the CD shipments.

Thank you, that is exactly what we were looking for.  If the design
works or needs to be updated is our problem, but now I can have the
flexibility to use the same versions as my co-worker does for this
project.


Article: 92619
Subject: Re: Curious about FPGAs
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Fri, 2 Dec 2005 14:43:04 -0000
Links: << >>  << T >>  << A >>
Generally a lot than a single processor is the answer. For DSP you can have 
many processing engines running in parallel. If you want to use 
microprocessors you can implement a soft IP microrprocessor like MicroBlaze 
many times within a single FPGA. Most modern FPGAs can have a reasonable 
amount sram memory available  internally for storage, delay, etc. etc.

Cost can vary hugely. Xilinx for instance have low cost Spartan-3 families 
where you can be down to 2-3 for a chip in high volume or you can spend 
2000+ for the largest high end performance Virtex-4.

As you look as if you are from a University or College you may be interested 
in out UAP program. We also have some free seminars coming up that might be 
of interest in January and February. Some basic details on our news/seminar 
webpages if either is of interest.

John Adair
Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 Development 
Board.
http://www.enterpoint.co.uk


<clemenr@wmin.ac.uk> wrote in message 
news:1133509915.483353.303940@g44g2000cwa.googlegroups.com...
> Hi. I'm curious about exactly what sort of things are done with FPGAs.
> Is the main reason for their use the additional speed over using a
> generic processor, due to clock rate and/or parallelism? Is it mainly
> to make cheaper low-run products? What sort of things can be done with
> them?
>
> As an example, it would be possible to build a digital reverberation
> unit using a *REALLY BIG* FIR filter. If the reverb impulse response
> lasted for say 15 seconds requiring M samples to be buffered, then
> assuming that x[n] is the current sample and that suitable b[0..M]
> coefficients can be found, then the reverb could be calculated as:
>
> reverb[n] = SUM {i=0 to M} x[n - (M - i - 1)] * b[i]
>
> This could be done in fixed point arithmetic.
>
> Given that 15 seconds of 44.1khz sound requires 15 * 44100 = 661500
> past input samples to be cached along with the 661500 b[] coefficients,
> would this be feasible with current FPGAs?
>
> Cheers,
>
> Ross-c
> 



Article: 92620
Subject: Re: Virtex-4 FX60 based products are already shipping now !
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Fri, 2 Dec 2005 14:46:27 -0000
Links: << >>  << T >>  << A >>
At the end of the day it depends on who you are. If you are CIS** yes is 
usually the answer.

John Adair
Enterpoint Ltd. - Soon to be Home of Broaddown4. The Ultimate Virtex-4 
Development Board.
http://www.enterpoint.co.uk

"Antti Lukats" <antti@openchip.org> wrote in message 
news:dmpjoi$clf$01$1@news.t-online.com...
> <francesco_poderico@yahoo.com> schrieb im Newsbeitrag 
> news:1133530924.724151.161830@z14g2000cwz.googlegroups.com...
>> Antii,
>> it looks very interesting, but I do not beleave that.
>> last week we had a meeting with a Silicas sales man and he told us that
>>
>> FX12 production device (I.e. not a CES part), likely to be on general
>> availability end of Q1'06.
>> FX20 production device (i.e. not CES), likely to be on general
>> availability MidQ3'06
>> FX40 production device (i.e. not CES), likely to be on general
>> availability Q3'06
>>
>> Francesco
>>
>
> well yes that matches what I know as well: no MGT silicon via distribution 
> til Q3'06 so thats exactly why those pictures of the FX60 based boards are 
> so interesting. I know there are several compoanies with ready PCB waiting 
> very badly for the FX60, and not getting them and not getting info when 
> those parts could be available. And still PLDA claims immediate 
> availability of their boards fitted with FX60!
>
> Antti
> 



Article: 92621
Subject: Re: first time managing a project
From: "Brendan Cullen" <bcullen@xilinx.com>
Date: Fri, 2 Dec 2005 15:26:56 -0000
Links: << >>  << T >>  << A >>
The first training I got in PM was ETP's 10-step approach :
http://www.etpint.com/tensteps.htm.  For software-specific projects I've
found Steve McConnell's ideas helpful : http://www.construx.com/.  Another
consideration is PMP certification wiht PMI : www.pmi.org.  Overall I'd
agree with other posters that tools are far less important than process and
attitude.  PM has many angles, cost, scheduling, quality, etc... Don't
neglect any of them.  One apprach is to consider you (the PM) being pulled
in 4 different directions - scope, quality, time & cost.  You (and your
stakeholders and team members) need to appreciate that those 4 all are
factors.  E.g., if you increase the scope and the other three constraints
remain the same your project will fail.

Brendan


<gretzteam@hotmail.com> wrote in message
news:1133279619.861418.105430@o13g2000cwo.googlegroups.com...
> Hi,
> I just got chosen as 'project manager' for our next project. It seems
> like most people feel 'sorry' for me around here... We are designing a
> moderately large mostly digital asic and the team consists of about 6
> people. I've never managed anything before and most of the people in
> the team are more senior designer than me. Right now, things are
> decided from hallway conversations, and nothing is really written down
> in terms of schedule and who-does-what...
>
> I wonder what tools if any that people use to manage a project. Is
> something like MS-Project any good? I understand that the schedule we
> would put in place will never hold, but I figure it's better to have
> something than nothing. Also, what do people use to track down bugs and
> issues. The chip is divided in 6-7 blocks, each will be assigned to
> one-two person. Where should I gather the information coming out of the
> weekly meeting - schedule slip, bugs to be fixed etc...email?
> ms-project? hallway?
>
> Thanks a lot,
>
> Dave
>



Article: 92622
Subject: Synthesize: Error
From: Simon <oceanfrea@hotmail.com>
Date: Fri, 2 Dec 2005 07:47:29 -0800
Links: << >>  << T >>  << A >>
Hi, if anyone could help me. I had declare real variable in vhdl and everything seems to be working after running simulation using the Xilinx ISE software. However, when i try synthesizing, it prompt error Real operand is not supported in this context. Please if anyone could help. I require floating variables to be declared in my code. Thanks.

Article: 92623
Subject: Re: first time managing a project
From: amyler@eircom.net
Date: 2 Dec 2005 07:51:04 -0800
Links: << >>  << T >>  << A >>
Absolutely, Fergus O'Connell / ETP teach a huge amount of common sense.

Alan


Article: 92624
Subject: Re: Xilinx FPGA - Behaviorial Model Transferred Instead of Place-and-routed Model
From: "Ryan Jones" <ryanjones2@gmail.com>
Date: 2 Dec 2005 08:03:50 -0800
Links: << >>  << T >>  << A >>
Chloe ,

I am pretty sure it is impossible to have the behavioral model
transferred to the FPGA. When you generate the JTAG file it runs
Translate, MAP and PAR first. Most likely, you are using modelsim with
the behavioral model instead of the place and route model. Make sure
you choose simulate post place and route model in your testbench. If
you are then there is some timing discrepency that modelsim is not
noticing that is causing the outputs of the FPGA to differ. Another
possibility is to make sure that you are not loading an old programming
file. This is a common problem. Regenerate the program file, noting the
time when it ran, and make sure the file you program is timestamped
with the same time.

Ryan




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