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"Isaac Bosompem" <x86asm@gmail.com> wrote in message news:1139186254.703000.140870@f14g2000cwb.googlegroups.com... > Hi everyone, I have recently purchased a XC3S200 based board with 256KB > Flash, 256KB platform flash and 32KB SRAM. So out of my interests I > figured I would design a simple SoC as a learning excercise. I have > designed a VGA framebuffer which does 640x480 (but uses pixel doubling > so 320x240x2-bit). A complete framebuffer is ~19KB. > > At this point I decided I would have to read the framebuffer at a line > at a time. A scanline in this mode would need 80 bytes of memory. > > Naturally I decided to infer a block RAM with 8-bit data width (well > 9-bit, but I am not using parity). > > The problem though is that when the Block RAM is 8-bits, you get almost > 2KB of space!! So that means I am wasting more than 90% of the space!! If your frame buffer is in the off-chip SRAM and you want the BlockRAM as the line buffer, don't look at the BlockRAM as wasting 90% of the space. Most people don't end up using all their BlockRAM making this an ideal use. If you implement the buffer in logic to avoid wasting the BlockRAM, you end up wasting 100% of the BlockRAM by not using it rather than the 90% you were concerned about. If you're trying to use the BlockRAMs for other functionality and are concerned about running out of memory *but* you have plenty of logic resources then the 40-45 LUTs (for 8-9 bits at 80 byte depth) is a good tradeoff. > I was looking into using a 8 128x1 distributed RAM and wire them in a > way to extend the data word to 8-bits. I am not certain how much of my > logic resources this would eat up. > > I am fairly new to the FPGA's so I'm not certain if these are the best > methods to buffer such a small amount of memory. > What would you do if you were in my situation? > > Regards > -Isaac Another consideration: if the BlockRAM is used as a single port (you use one address to write during the blanking and that same address to read when it's active) you have a second single-port memory in that same BlockRAM to access the remainder of that 2kByte memory. To share resources like this usually requires that you instatiate the BlockRAM primitive rather than inferring the memory. Another suggestion since you're concerned about reading the data during the blanking period: are you pushing the SRAM near its maximum clock rate? (Probably not if you're doing pixel doubling.) If you increase the clock speed with the DCM, you can increase the data throughput into and out of the external SRAM. The BlockRAM can take in data at the SRAM's maximum rate with ease (as will the SRLs). Using a DCM (Digital Clock Manager, I believe) requires a little more care in your design with the suggestion that you use the 1X clock output from the DCM to "phase match" the higher speed clock to the 1X clock rather than using the input clock that feeds the DCM.Article: 96551
Thanks for the replies everyone, they have been very helpful. Does Lattice provide a vendor-specific monitoring library like Xilinx and Altera?? shawnn@gmail.com wrote: > Hello, > > When doing development using microcontrollers/processors, you can often > find ICEs and ICDs that allow you to set breakpoints. You can stop the > code in execution and view the contents of registers, state of input > pins, etc. > > Suppose I want to do something similar with an FPGA-based design. What > are my options? I know I can output internal signals to output pins and > sniff them using a logic analyzer, but I'm hoping there is a more > elegant solution. I'd like to stop everything at some point and view > all inputs, outputs, registers, etc. > > Can someone point me in the right direction?Article: 96552
Peter Alfke wrote: > The big dedicated players, LSI Logic, Xilinx, Altera, Lattice, Actel, > et.al. are all publicly traded companies. > If you want to check on their success, just watch their relative stock > performance. I bought some XLNX at $44 back in 2002. It immediately tanked, and recovered somewhat, but it's been basically flat below $30 for a year and a half. -aArticle: 96553
<shawnn@gmail.com> schrieb im Newsbeitrag news:1139247241.938636.127450@g44g2000cwa.googlegroups.com... > Thanks for the replies everyone, they have been very helpful. > > Does Lattice provide a vendor-specific monitoring library like Xilinx > and Altera?? > > > shawnn@gmail.com wrote: >> Hello, >> >> When doing development using microcontrollers/processors, you can often >> find ICEs and ICDs that allow you to set breakpoints. You can stop the >> code in execution and view the contents of registers, state of input >> pins, etc. >> >> Suppose I want to do something similar with an FPGA-based design. What >> are my options? I know I can output internal signals to output pins and >> sniff them using a logic analyzer, but I'm hoping there is a more >> elegant solution. I'd like to stop everything at some point and view >> all inputs, outputs, registers, etc. >> >> Can someone point me in the right direction? > yes, included for free ispTrace AnttiArticle: 96554
Gabor wrote: > The usual problem here is hold time violations going from the > fast process to the slow one. If your (expression) in the slow process > uses any outputs of the fast process, then you can have hold time > violations due to the slowclk delay. Note that the skew times in > your timing report are within each clock domain and don't indicate > skew between the two clocks. I see. Thanks the for explanation Gabor. Perhaps I'm better off using John's idea. Regards, Paul.Article: 96555
John_H wrote: > "Isaac Bosompem" <x86asm@gmail.com> wrote in message > news:1139186254.703000.140870@f14g2000cwb.googlegroups.com... > > Hi everyone, I have recently purchased a XC3S200 based board with 256KB > > Flash, 256KB platform flash and 32KB SRAM. So out of my interests I > > figured I would design a simple SoC as a learning excercise. I have > > designed a VGA framebuffer which does 640x480 (but uses pixel doubling > > so 320x240x2-bit). A complete framebuffer is ~19KB. > > > > At this point I decided I would have to read the framebuffer at a line > > at a time. A scanline in this mode would need 80 bytes of memory. > > > > Naturally I decided to infer a block RAM with 8-bit data width (well > > 9-bit, but I am not using parity). > > > > The problem though is that when the Block RAM is 8-bits, you get almost > > 2KB of space!! So that means I am wasting more than 90% of the space!! > > If your frame buffer is in the off-chip SRAM and you want the BlockRAM as > the line buffer, don't look at the BlockRAM as wasting 90% of the space. > Most people don't end up using all their BlockRAM making this an ideal use. > If you implement the buffer in logic to avoid wasting the BlockRAM, you end > up wasting 100% of the BlockRAM by not using it rather than the 90% you were > concerned about. If you're trying to use the BlockRAMs for other > functionality and are concerned about running out of memory *but* you have > plenty of logic resources then the 40-45 LUTs (for 8-9 bits at 80 byte > depth) is a good tradeoff. > > > I was looking into using a 8 128x1 distributed RAM and wire them in a > > way to extend the data word to 8-bits. I am not certain how much of my > > logic resources this would eat up. > > > > I am fairly new to the FPGA's so I'm not certain if these are the best > > methods to buffer such a small amount of memory. > > What would you do if you were in my situation? > > > > Regards > > -Isaac > > Another consideration: if the BlockRAM is used as a single port (you use one > address to write during the blanking and that same address to read when it's > active) you have a second single-port memory in that same BlockRAM to access > the remainder of that 2kByte memory. To share resources like this usually > requires that you instatiate the BlockRAM primitive rather than inferring > the memory. > > Another suggestion since you're concerned about reading the data during the > blanking period: are you pushing the SRAM near its maximum clock rate? > (Probably not if you're doing pixel doubling.) If you increase the clock > speed with the DCM, you can increase the data throughput into and out of the > external SRAM. The BlockRAM can take in data at the SRAM's maximum rate > with ease (as will the SRLs). Using a DCM (Digital Clock Manager, I > believe) requires a little more care in your design with the suggestion that > you use the 1X clock output from the DCM to "phase match" the higher speed > clock to the 1X clock rather than using the input clock that feeds the DCM. Yes I am concerned about potentially running out of on-chip space. It is not a major issue right now. But I would like to see how you guys would handle it and I am very happy with the responses I got! I'm sorry for confusing you guys but I did instance the BlockRAM I did not infer it. I was thinking of allowing external modules to access the rest of the memory through the 2nd port. That would allow me to access the rest of the space in the BlockRAM when I need it in the future. I am not pushing the SRAM to its maximum speed. The SRAM on my board has a 20ns access time, so I get a little less than 50Mhz when taking setup and hold times into account. I might be able to use a lot more of the BlockRAM using that speed but that would require me to utilize the 2nd port making it unavailable to external entities. The framebuffer reader will make use of the 2nd port to stay ahead of the raster counters. I will try and see if a clock multiply will help, thanks for the tip with the DCM. If you had not told me that I would have used the original signal for the parts that run at 25Mhz.Article: 96556
"Isaac Bosompem" <x86asm@gmail.com> wrote in message news:1139254458.451186.266750@z14g2000cwz.googlegroups.com... <snip> > I am not pushing the SRAM to its maximum speed. The SRAM on my board > has a 20ns access time, so I get a little less than 50Mhz when taking > setup and hold times into account. I might be able to use a lot more of > the BlockRAM using that speed but that would require me to utilize the > 2nd port making it unavailable to external entities. The framebuffer > reader will stay ahead of the raster counters. > > I will try and see if a clock multiply will help, thanks for the tip > with the DCM. If you had not told me that I would have used the > original signal for the parts that run at 25Mhz. The multiply makes life much easier. You can even run the entire design at 50 MHz but use a clock enable every-other clock to get 25 MHz processing downline. With the clock-enabled configuration, it might become more obvious how you can still use the BlockRAM at 50MHz without using the second port to do it.Article: 96557
Hi all, Can anyone please explain what is the difference between the following two options (bsb) debug i/f: 1) on-chip hw debug module. 2) xmd with sw debug stub. I would like to know in what cases should I use the 1st option and when should i use the second one. Thanks in advance, Mordehay.Article: 96558
You could look at the BYU work on this. http://splish.ee.byu.edu/projects/LinuxFPGA/index.htm ramesh wrote: > Hi All, > Iam new to xilinx platfrom. > > I was trying to port open source linux on Ml403 board. i tried to > follow the instructions in the below link. > http://www.klingauf.de/v2p/index.phtml > i was getting errors when i was running bZimage. the .elf file was not > getting created. > > Is there an alternative way of acheiving my goal. > Kindly suggest. > Thanks in advance. > > RameshArticle: 96559
gnathita wrote: > Hello, > > I ported linux 2.4_devel to the ml403 board. > > Feel free to ask me about what I did if you need help. > Paula We are about to undertake this effort as well. I would greatly appreciate it you could do a quick write up for this thread regarding your process. Specificlly detailing which document(s) and/or instructions you followed to do the port, URLs for where these can be found, and most importantly where you departed from the starting points, and/or stumbled. We talked to Timesys and MonteVista both about this. The former sounds promising, and if they had an existing port for ML403 as a starting point we would probably just pay for their subscription service. The later did not offer a business model that was compatible with our needs. The business model can make sense for a lot of customers. We are both an ODM and a Design for Hire shop, and the model would work for some but not all of our customers/engagements. I do not intend to comment further on this. Please talk to MonteVista directly if you want to understand the business model, as I do not want to risk misadvising. We are also considering doing this without using an outside service, so your comments will be of value to me in our decision making process. If there are any consultants that have done a Linux 2.4 port to a Xilinx platform (either V2pro or V4FX, located in the greater Boston area, please feel free to drop me an email, and we'll chat offline. We might consider using an outsider to bring some of my guys up to speed, and help with our port and/or drivers. We are excited about the possibilities of Linux on V4FX. We are presently using the ML403 board as the basis for our compute platform, and intend to use Linux. I, like others, am not interested in reinventing the wheel. We are doing the initial development on our projects with ML403 and custom daughterboards. We will then build the completely custom systems. The ML403 is a very well thought out platform. Previously, we would build custom hardware before even starting the application development. For the past four years our compute platform was based on V2/microBlaze and/or V2pro/PPC with homebrewed DOS file system, and no OS. But now that we need to incorporate TCP communications and much more complicated applications support, an OS (specifically Linux) is the direction we are headed. Regards, Erik. --- Erik Widding President Birger Engineering, Inc. (mail) 100 Boylston St #1070; Boston, MA 02116 (voice) 617.695.9233 x207 (fax) 617.695.9234 (web) http://www.birger.comArticle: 96560
On Mon, 06 Feb 2006 02:09:14 GMT, Jonathan Schneider <jon@jschneider.tenreversed> wrote: >For making fine modifications to PCBs, which of Tefzel and Kynar >insulated wired are best to use ? > >Jonn For chunky electronics (DIP ICs), Kynar wire (wire wrap gage 30 AWG) is what I use. It is fairly tollerant of short term touching with a soldering iron, comes in lots of colors, and is typically silver plated, so tinning is easy and thorough. If you avoid any sharp bends in the insulated section of the wire within about 3/8 of an inch from the end of the insulation, the heating of soldering does not tend to cause problems. If you do it any closer to the end of the insulation, it tends to split, revealing more un-insulated wire than you may want. A nice feature of Kynar is that it does not roll-back much when you are soldering. For fine work around SOICs, SMT resistors and caps, and other finer detail boards, I would be lost without Tefzel wire. Among the most important issue of doing rework, is getting the wire the right length, and only stripping as much insulation as necessary. Tefzel wire may also be found as wire with Polyurethane insulation. Tefzel is the trade name for Polyurethane insulated wire. With care the insulation of Tefzel wire will vaporize when you place the tip of the wire into a fresh blob of solder on the end of your soldering iron. With care, by controling how much of the wire you place in the little pool of solder you can strip only as much insulation as you need. I regularly achieve stripping lengths below .030 inches. This also tins the wire. I use 36 AWG Tefzel Wire. You do need good ventilation and airflow over your work area, so you don't breath the vaporized insulation. Tefzel wire of this fine gage can be hard to come by. It used to be readilly available under the name VeroWire, and a google search will still find some vendors that sell it, mostly in Europe. Tefzel is also refered to as self-fluxing wire, since the vaporizing Polyurethane acts as a flux (but not as good as rosin). You may also find it as magnet wire with Polyurethane insulation. Other toys that I have found are a MUST-HAVE for rework: Tweezers (#6) Metcal Soldering iron system Stereo 10X microscope with boom arm Rosin flux in ethyl-alcohol solution .015 inch dia rosin core solder 63/37 Chip-Quik Scalpel with replaceable blades. #11 is my favorite Sharp pointy stick (dental probe) http://www.okinternational.com/product_soldering/smart_heat http://www.hmcelectronics.com/cgi-bin/scripts/brands/Metcal/1 http://dkc3.digikey.com/PDF/T061/1564.pdf http://www.digikey.com/scripts/dksearch/dksus.dll?Detail?Ref=121978&Row=339335&Site=US http://www.chipquik.com/ http://www.digikey.com/scripts/DkSearch/dksus.dll?Detail?Ref=123176&Row=75397&Site=US http://www.greenweld.co.uk/acatalog/Shop_PCBs_86.html Item CDT0279 £10.47 worth will last a very long time if just used fro rework. http://www.verotl.com/products/index.cfm?content_id=7846BCBE-F067-441A-9F53A51D8E4CC6B3 http://www.jaguarind.com/products/wirewrap.html http://www.reawire.com/Default.asp?p=365 Philip Freidin Philip Freidin FliptronicsArticle: 96561
Hi all, I'm using a Virtex-2 FPGA and I wonder how can I efficiently choose one from many wires competing to hold a resource. When 2 wires request the resource at the same time, only the one with higher priority should be taken. I know how to do it attaching all the wires to multiple AND gates. The problem is that those AND gates can be huge if 20+ wires compete. Any ideas? Thanks. Jose.Article: 96562
"JL" <kasty.jose@gmail.com> wrote in message news:1139261804.720854.157990@g44g2000cwa.googlegroups.com... > Hi all, > > I'm using a Virtex-2 FPGA and I wonder how can I efficiently choose one > from many wires competing to hold a resource. When 2 wires request the > resource at the same time, only the one with higher priority should be > taken. I know how to do it attaching all the wires to multiple AND > gates. The problem is that those AND gates can be huge if 20+ wires > compete. > > Any ideas? > > Thanks. > Jose. > Hint: search Priority encoderArticle: 96563
me_2003@walla.co.il wrote: > Can anyone please explain what is the difference between the following > two options (bsb) > debug i/f: > 1) on-chip hw debug module. A hardware module connects to the FPGA's JTAG interface, and to the debug/control signals on the MicroBlaze. No software intervention is required. You can set hardware breakpoints, watchpoints and all that good stuff. > 2) xmd with sw debug stub. A small software handler (stub) is installed in low memory, and communicates via serial (not JTAG) to the XMD utility on the development machine. > I would like to know in what cases should I use the 1st option and when > should i use the second one. Option (1) is to be preferred in almost every case, except if maybe if you cannot spare the logic required for the OPB_MDM debug core. Option(1) allows fast data and software downloads, via XMD we can download a linux kernel in under 20 seconds, via serial it can take up to 15 minutes. There's really no comparison - the HW debug is far superior. Regards, JohnArticle: 96564
Clark, I need your real email address if I am to reply off-list. John Anonymous wrote: > Thanks for the offer. > > I'm actually not doing anything particularly exotic. I just want to embed a > "linux pc" into my fpgas to replace what was traditionally done by custom > control processor designs and software. In my view it should just be a > coregen module that Xilinx provides but it's turning out to be more > involved. > > Anyway my specific wish list is: > 1. linux (2.6 kernel preferred) > 2. Virtex-4 family > 3. gigabit ethernet > 4. sd card (or other portable memory) > 5. power control (reduce clock or sleep processor) > 6. usb gadget driver and USB2.0 > > is the current microblaze/uClinux tree able to do this? > > Thanks, > Clark > > > "John Williams" <jwilliams@itee.uq.edu.au> wrote in message > news:newscache$nsj8ui$7ce$1@lbox.itee.uq.edu.au... > >>Clark, >> >>Anonymous wrote: >> >> >>>My application requires a USB2.0 slave mode. Does anyone know which tree > > is > >>>best for USB gadgets: PPC/Linux or MB/uClinux? >> >>I suggest we take this off-list before we are lynched for being >>permanently off-topic. >> >>Can you email me directly, or discuss on the microblaze-uclinux list? >> >>http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/Mailing_List/ >> >>Thanks, >> >>John >> >> > > >Article: 96565
Hi John, firstly, thank you for the prompt reply.. The issue that got me confused is that even when I select to use option 2 (xmd with sw debug stub) the bsb also instantiate a mdm module in my mhs... why is that ? As I understnaded from your answer it should have used a uart or maybe I'm missing something. Thanks, Mordehay.Article: 96566
me_2003@walla.co.il wrote: > The issue that got me confused is that even when I select to use option > 2 (xmd with sw debug stub) the bsb also instantiate a mdm module in my > mhs... why is that ? It's probably just a "feature" of the XBD (board description) file for your board. Just pretend the SW option isn't there. Default to HW - it's really that simple! JohnArticle: 96567
Thanks again John, I understand that the xmd stub option is not the prefered option but still I would like to understand it properly. You said that the SW stub does not use the jtag so can you elaboarte more regerding the way the xmd_stub connects/communicates with the external world (e.g. gdb). its just that I didnt see any uart or other serial-comm core on the MHS. Thanks for all your help, Mordehay.Article: 96568
"Austin Lesea" <austin@xilinx.com> schrieb im Newsbeitrag news:ds0qj5$3ls28@xco-news.xilinx.com... > I have had customers come to visit. They say "we can't afford to make > ASICs any longer, we need to learn how to use your FPGAs." These are not > little companies. These a multinational corporations with sites around > the world. > Why does the Truman Show at the End come to my mind here ? > My job is tougher because now I have to explain to folks who used to > design ASICs for a living. They KNOW all of the terrible ultra deep > submicron potholes. And they (sometimes) do not give us any credit for > having also experienced all the potholes, and already gotten around them. > They somehow feel that making FPGas is easy. Well, many have tried, and > most have failed. Must be trivial, right? And what pothole did the XC3S200E Stepping 0 DCM hit ? Raymund HofmannArticle: 96569
"Raymund Hofmann" <filter002@desinformation.de> schrieb im Newsbeitrag news:ds8jj0$rhj$1@online.de... > > "Austin Lesea" <austin@xilinx.com> schrieb im Newsbeitrag > news:ds0qj5$3ls28@xco-news.xilinx.com... > >> I have had customers come to visit. They say "we can't afford to make >> ASICs any longer, we need to learn how to use your FPGAs." These are not >> little companies. These a multinational corporations with sites around >> the world. >> > > Why does the Truman Show at the End come to my mind here ? > >> My job is tougher because now I have to explain to folks who used to >> design ASICs for a living. They KNOW all of the terrible ultra deep >> submicron potholes. And they (sometimes) do not give us any credit for >> having also experienced all the potholes, and already gotten around them. >> They somehow feel that making FPGas is easy. Well, many have tried, and >> most have failed. Must be trivial, right? > > And what pothole did the XC3S200E Stepping 0 DCM hit ? XC3S250E, of course Raymund HofmannArticle: 96570
Hello everyone. We are a senior design group from Oregon State University. Our webpage is: http://classes.engr.oregonstate.edu/eecs/fall2005/ece441/groups/g1/ (soon to be updated with Part Numbers and source code) We've nearly ordered all of our parts: Spartan 3 (demo board), RF Oscillator, High Signal Level Upconverting Mixer, I/Q Modulator, Amplifier, Voltage Regulators, DACs, and Transmitters. Our goal is to transmit signals using either 16QAM or BPSK Modulation. Our plan is to * model functions using vhdl * build a prototype circuit * synthesize our code onto fpga * analyze results using various scopes Currently working on a more accurate block diagram showing component connection. feel free to respond with questions/comments/concerns.Article: 96571
me_2003@walla.co.il wrote: > Thanks again John, > I understand that the xmd stub option is not the prefered option but > still I would like to understand it properly. You said that the SW stub > does not use the jtag so can you elaboarte more regerding the way the > xmd_stub connects/communicates with the external world (e.g. gdb). its > just that I didnt see any uart or other serial-comm core on the MHS. You should read Chapter 15 of the Embedded Systems Tools Reference Manual (est_rm.pdf) If you choose xmdstub as your debug option, it's still your responsibility to request a UART in your system. Then, in the EDK, you select that uart as the debug peripheral. JohnArticle: 96572
Why not use the GNU radio and USRP? http://www.gnu.org/software/gnuradio/ All the tools are free, the usrp is only about $500, and it has two transmit and two receive. -Clark <zhangweidai@gmail.com> wrote in message news:1139266177.622935.100410@z14g2000cwz.googlegroups.com... > Hello everyone. > > We are a senior design group from Oregon State University. > Our webpage is: > http://classes.engr.oregonstate.edu/eecs/fall2005/ece441/groups/g1/ > (soon to be updated with Part Numbers and source code) > > We've nearly ordered all of our parts: Spartan 3 (demo board), RF > Oscillator, High Signal Level Upconverting Mixer, I/Q Modulator, > Amplifier, Voltage Regulators, DACs, and Transmitters. > > Our goal is to transmit signals using either 16QAM or BPSK Modulation. > > Our plan is to > * model functions using vhdl > * build a prototype circuit > * synthesize our code onto fpga > * analyze results using various scopes > > Currently working on a more accurate block diagram showing component > connection. feel free to respond with questions/comments/concerns. >Article: 96573
Thanks for your help John... Best regards, Mordehay.Article: 96574
Austin Lesea wrote: > Jim, > > It has to do with current creating a magnetic field, and how the > magnetic fields interact. > > Imagine I have a rectangular loop (tall and skinny), divided down the > middle by a sheet of glass. > > On either side of the glass I have a scale (made of plastic) to see how > much the wire pulls away from the glass as the current increases in the > loop. > > At some point, I add a third wire on one side of the glass in parallel. > It is some distance away from the glass, more so that the first set of > wires. > > What I claim is that the force of the third added wire will be less than > that of the first wire, and the force of the first on the same side of > the glass wire will be somewhat less, but will not be 1/2. In fact with > the BART rail spacing, it would be 2/3 and 1/3. Yes, but in your first example, you claimed DC Current diffences, not forces (kg) on the wires ?! > > At DC. > > Guess what? Current creates a field, a field tells current how to flow. > > I think Faraday discovered this? I await your real examples, with hard data. So far, I have placed this in the urban myth box. Some reality checks, from my old, trusty University Physics book: Force on wire = Current * Length * B(Field) B near a long wire = MUo * Current / 2*Pi*R so yes, B falls off inversely with distance. MUo is small, at 4*pi*10e-7 weber/amp-meter ( that's why you need many turns, and small air gaps, in a motor ) Motors start with a force, and then the 'moving wire in magnetic field' law (Lenz's law to some) creates a back-emf, that reduces the current, by reducing the apparent voltage. Now to the Hall effect, (some have quoted as the cause) : Vxy = Current x B(Field) / n * e * thickness Their worked example applied a massive 1.5 weber/m2 to a 20mm x 1mm copper strip and the resulting Hall voltage, across the copper strip was 22uV So, yes, it is an effect, but no, I cannot see it causing a large shift in DC current balance due to the field set up by a single wire. Seems time and the urban myth effect have confused the B field variation ( which DOES fall off with 1/R ), with the DC current, and we are still unclear on the details of what exactly failed westinghouse. So, as to DC current in the inner BGA Balls being a fraction of their outer neighbours, show me some proof. [and remember, this is DC, not AC ] Perhaps a high quality thermal image, good enough to show the ball temerature profiles, due to DC current ? -jg
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