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Jose, how fast do you need the answer? ns or perhaps even clock cycles? Peter AlfkeArticle: 96576
Alan Myler wrote: > > Cyclone is not compatible with PCI 5v, the voltage transients > exceed 5v and will damage the device. > > You will need to use IDT Quickswitch or similar device to > limit the input voltage to your Cyclone in a 5v scenario. > > Google for PCI and quickswitch, you should find a Xilinx > app's note on the subject. > ... or look a the schematics for the Altera Cyclone PCI development kits. -hpaArticle: 96577
Thanks,can i have your msn,and I have some question to ask! Why should i need the Power-on and hardware reset protocol and the Bus idle protocol,I think only i just need are the - PIO data-in and data-out command protocol - Ultra DMA read/write of a block Do the registers transfer use the pio protocal?Article: 96578
zhangweidai@gmail.com wrote:
> Our goal is to transmit signals using either 16QAM or BPSK Modulation.
> Our plan is to
> * model functions using vhdl
matlab first?
> * build a prototype circuit
finish all sims first?
-- Mike Treseler
Article: 96579>MUo is small, at 4*pi*10e-7 weber/amp-meter >( that's why you need many turns, and small air gaps, in a motor ) You can get motion from single turns as long as you use a enough current. The Exploratorium has (had?) an exhibit with several 1 inch dia wires running vertically reasonably close to eachother. They were attached at top and bottom but not constrained in between. 6 or 8 feet high. You step on a switch and it dumps a lot of current into the wires. They move. (I forget the details. It's been a few years since I saw it.) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 96580
Where can I find the ata device bus function model for simulation?Thanks!Article: 96581
Hi all, I am new to Verilog and want to build a 2's Complement Shifter. I found %displayb(8'b0001_1000>>2); //Output 0000_0110 %displayb(8'b1001_1000>>2); //Output 0010_0110 So >> is unsigned shift. How can I build a signed (2's Complement) shift based on >>? i.e. I want 8'b1001_1000>>2 //Output 1110_0110 Any suggestions will be appreciated! Best regards, DavyArticle: 96582
hi all! I'm using NiosII with StratixII. i wanted to get interrupts from a micro controller of 7.393MHz Oscillator which generates half the oscillator clock. Nios works at 50Mhz. so what modification i need to do on niosArticle: 96583
Hi expert fellows :) ,
I would like to get some advices on making a cheap usb analyzer with an
cheap FPGA board :
-i only target loww speed / full speed at the moment
- i woudl proceed like this :
* cut an existing USB cable, insert a breakoutinteh middle
* connect D+ & D- (and GND) to the FPGA pins (i guess impedance aspects
are OK since FPGA pin input Z is ~ infinite...)
* build the analyzer design using the opencore's USB PHY Core & USB 1.1
Function Core
* the design would intercept all USB trafic and would store it onchip ,
with the possibility of retrieving it on the PC
The main Questions concerns
- electric level : i plan to only use D+ using LVTTL but ....
- NRZI tackle : how can i rebuild the USB clock from it ?
Any advice welcome !
Have a nice day.
Article: 96584On 6 Feb 2006 22:14:32 -0800, the renowned "Davy" <zhushenli@gmail.com> wrote: >Hi all, > >I am new to Verilog and want to build a 2's Complement Shifter. > >I found >%displayb(8'b0001_1000>>2); //Output 0000_0110 >%displayb(8'b1001_1000>>2); //Output 0010_0110 > >So >> is unsigned shift. >How can I build a signed (2's Complement) shift based on >>? >i.e. I want 8'b1001_1000>>2 //Output 1110_0110 > >Any suggestions will be appreciated! >Best regards, >Davy Verilog 2001 has >>> (signed shift operator) Best regards, Spehro Pefhany -- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.comArticle: 96585
hi all! I'm using NiosII with StratixII. i wanted to get interrupts from a micro controller of 7.393MHz Oscillator which generates half the oscillator clock. Nios works at 50Mhz. so what modification i need to do on niosArticle: 96586
a wrote: > module latch(v1,v2,v3,c1,c2); > input v1,v2,v3,c1,c2; > //output b; > reg a,b; > always @ (*) > begin > a=v1; > if (c1) b=a|v2; > if(c2) b=v3; > end > endmodule I just ran a similar code through ise 8.1i, and here is the funny observation: ISE 8.1i: I took this one through ise: . `timescale 1ns / 1ps . module latch(a,b, c,d,e); . input a,b; . output c,d,e; . reg c,d,e; . always @(*) . // always @(a or b ) . begin . if ( a ) begin . c = a; . e = a; . end . if ( b ) begin . d = b; . e = b; . end . . end . endmodule For C, it puts a LD with D tied to VCC, gate tied to A For D, it puts a LD with D tied to VCC, gate tied to B ( only connection for B) for E, it puts a LDP with Aset floting ( according to schematic) D tied to VCC, and gate tied to A Any comments Xilinx experts ? Thanks in advance!Article: 96587
Davy wrote:
> How can I build a signed (2's Complement) shift based on >>?
> i.e. I want 8'b1001_1000>>2 //Output 1110_0110
How about
12'b1111_1001_1000>>2
or
{ 32{b[7]}, b } >> 2
Article: 96588Hi , Do you have any kind of documentation or any URL where i can find how to port linux on ML403? Ramesh gnathita wrote: > Hello, > > I ported linux 2.4_devel to the ml403 board. > > The zImage. that you get is fine for loading into the Virtex4 ppc. The > only thing you need to do is "cp" it to another directory with the .elf > extension. > > I integrated it with my download.bit into an .ace file and it works ok > both for the reference design and for my custom design (a basic one). > > Feel free to ask me about what I did if you need help. > PaulaArticle: 96589
Hi
How to map a desgin on to FPGA by using qautus tool.i am
knew to this one .to map a desgin in to FPGA .what are the things we
need.?i want to target a desgin on FPGA stratixII.,pls give
information?
thanks
venkat
Article: 96590> Thanks,can i have your msn,and I have some question to ask! I don't use msn (and I'm no service hotline) but my e-mail is valid > Why should i need the Power-on and hardware reset protocol after power up you want to have the drive in a defined state and you want to find out if and when the drive is ready for your commands ... > and the Bus idle protocol that is what you do with the bus in the gaps between PIO or UDMA transfers ... nothing much but still there is a diagram for that > Do the registers transfer use the pio protocal? the PIO protocol *only* gives you acces to the registers ... by reading, writing and reading registers (over PIO) you can do data transfers ... data can be transfered by multiple access to a register (easy case) or by a DMA burst ... that is why you should follow the implementation order described ... ... and maybe you should just start reading the spec bye, MichaelArticle: 96591
WHY do Verilog users post in this newsgroup ? Rgds Andr=E9sArticle: 96592
To be on the safe side, sample the interrupt request with a D flip-flop clocked by the Nios' clock, and connect the output to the Nios' interrupt line. AvishayArticle: 96593
I need the answer within clock cycles. One clock cycle would be great,
although I can bear a few more. I didn't mention that the priority
encoder or whatever solution should be parametrizable in VHDL. Just as
background information, I'm developing a bus where all modules (DMA,
CCD cameras, etc) can request a long write to SDRAM at any moment.
Since the transfer is quite long, over 512 words, I don't care if the
arbiter takes a few cycles to resolve who will be granted the bus.
I'm trying this now:
signal requests : std_logic_vector(m-1 downto 0);
signal resolved : std_logic_vector(m-1 downto 0);
process(i_Clk, i_Rst, first_level)
variable found : std_logic;
begin
if (i_Rst = '1') then
resolved <= (others=>'0');
elsif (i_Clk'event and i_Clk = '1') then
found := '0';
for y in 0 to m-1 loop
if (requests(x) = '1' and found = '0') then
resolved <= ext(requests(y downto 0), m);
found := '1';
end if;
end loop;
end if;
end process;
It synthesizes well, although I don't know if that is good coding
practice. It seems to work at behavioral and post-place&route
simulations.
I'm just a bit worried about the efficiency of that construct. Do you
think it will become a headache if I don't express it in another way?
Do you think it could grow too big for something like 30 wires
requests?
Regards.
Jose.
Article: 96594by doing that can i b able to get regular pattern interrupts. i.e i want to get a sequence of interrupts with some delay.Article: 96595
Simon you're right. To solve this problem it is suggested to upgrade to the Designer 6. The other option is, to install xilinx ise 7.1 which is the option i chose. NilsArticle: 96596
H. Peter Anvin wrote: > ... or look a the schematics for the Altera Cyclone PCI development kits. > > -hpa Finding is better than looking.... ftp://ftp.altera.com/outgoing/devkit/PCI_DK_2C35/schem_cii_pcidevbd_b.pdf Karl.Article: 96597
Greetings FPGA Group,
I'm attempting to input an LVDS clock signal into a SoC design. This
development is based on a NuHorizons SP3 board with a Spartan-3
(xc3s1500-fg676-4). Although it supports primitives for input
differential clock signals through the usage of, for example, the
IBUFGDS_LVDS_25 component, when I do instantiate such blocks, Bitgen
reports a couple of non-informative warnings and finally generates the
stream. However the result corrupts all the internal signals of the
SoC...
The warnings only show up with the Spartan-3 family. All works fine,
and no warnings are displayed if using a Virtex family device. These
warnings as following pop-up during the bit-generation (using ISE
7.1i):
WARNING:Bitgen:74 - Unknown primitive "DRIVE_0MA" for site "IOB4".
WARNING:Bitgen:74 - Unknown primitive "DRIVE_0MA" for site "IOB5".
Any help, hint, or even pointers to successful implementations of LVDS
clocks inputs on a Spartan 3, will be mostly appreciated.
Thanks in Advance,
Antonio Roldao Lopes
I've isolated the code that generates such warnings and produced a
simple test-bench, here it goes...
-- LVDS BLACK BOX
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity LVDS_BOX is
port(nRESET : in std_logic;
CLK_T : in std_logic;
CLK_I : in std_logic;
CLK_O : out std_logic);
end LVDS_BOX;
architecture Behavioral of LVDS_BOX is
signal CLK : std_logic;
signal s : std_logic;
begin
U0: IBUFGDS_LVDS_25 port map (I=>CLK_T,IB=>CLK_I,O=>CLK);
process(nRESET, CLK)
begin
if nRESET = '0' then
s <= '0';
elsif rising_edge(CLK) then
s <= not s;
end if;
end process;
CLK_O <= s;
end Behavioral;
-- TEST BENCH LVDS BLACK BOX
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY Tb_LVDS_BOX IS
END Tb_LVDS_BOX;
ARCHITECTURE behavior OF Tb_LVDS_BOX IS
COMPONENT LVDS_BOX
PORT(
nRESET : IN std_logic;
CLK_T : IN std_logic;
CLK_I : IN std_logic;
CLK_O : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL nRESET : std_logic := '0';
SIGNAL CLK_T : std_logic := '0';
SIGNAL CLK_I : std_logic := '1';
--Outputs
SIGNAL CLK_O : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: LVDS_BOX PORT MAP(nRESET,CLK_T,CLK_I,CLK_O);
-- Generate Differential Clock Signal
CLK_T <= not CLK_T after 100 ns;
CLK_I <= not CLK_I after 100 ns;
tb : PROCESS
BEGIN
-- Reset System
nRESET <= '0';
wait for 400 ns;
nRESET <= '1';
-- Stop Simlation, the ugly way!
wait for 1 us;
report "Done" severity Failure;
END PROCESS;
END;
Article: 96598Once you have installed Quartus, go to the Help Tutorial and the Help PDF Tutorials. These should help you get started. More information is available on the Altera web site at http://www.altera.com/literature/lit-qts.jsp Start with the Introduction to Quartus II Manual to get a good idea of all the capabilities in the Quartus II Software. The Quartus II Handbook goes into these topics in more detail. - Subroto Datta Altera Corp "venkat" <kvs_456skec@yahoo.com> wrote in message news:1139305071.305160.194480@g14g2000cwa.googlegroups.com... > Hi > How to map a desgin on to FPGA by using qautus tool.i am > knew to this one .to map a desgin in to FPGA .what are the things we > need.?i want to target a desgin on FPGA stratixII.,pls give > information? > thanks > venkat >Article: 96599
Hello, I have the following system: - A Spartan 3E 500 FPGA - Some internal BRAM memory - An external SPI flash The external SPI flash contains the instruction code. However I can't use a bootloader because the internal BRAM memory is not big enough for all the code. We don't use an external memory because price is important for this design (every $ counts). I would like to have the Microblaze fetching code from the SPI flash. The problem is that I have to use the OPB SPI interface for this and this interface is not a 'real' memory interface. Has anyone had a similar problem? How did you solve it? Thanks and best regards, Karel
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