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Hi Antti, thank you for you answer. Since you have successfully fulfilled the function and have the experience to do the experiment, you surely know the detail about how to programme flash memory. Would you please kindly provide me some materials and explain it in detail to me. Would you please give me some general example projects to me? I met some problems when using tools->program flash memory. My flash are two chips of "AT49BV162A" which are controlled by emc and there are two sram(each of them is 512K bytes) together with them. During my experiment there is always an infromation "DeviceIoControl LPT_WRITE_CMD_BUFFER Failed", then the project is always running without stop. I also want you to explain to me the different meanings of "flash memory properties" and Scratch Pad Memory Properties". what are they two repectively used for? Thank you very much. Best regards. LinaArticle: 92701
Hi all, I'm looking for ideas why a design using 43 DSP48s as multipliers might not fit a V4LX25 with 48 DSPs... Symptoms are PAR failing with ten PLACE:119 warnings and a PLACE:120 error. Most of the DSP48s are cascaded, but only in pairs (for 24x<16 mults), so it doesn't look like AR20093 and AR20851 should apply. I'm not (knowingly ) using BUFRs, so I don't think 20511 applies. And I can't see any other AR that seems relevant; nor comp.arch.fpga posts. The design does use some RAMB36_36 blocks (I need wide I/O and not much depth); so I wondered about the Spartan-3 RAMB/Mult packing restriction, but I haven't seen any similar warnings about V4... Before I try floorplanning the DSPs, has anyone seen any similar failures? - BrianArticle: 92702
Hi, all. I want to use a fifo(Xilinx IPCore) outside microblaze(of course inside the chip). Now , I use GPIO of microblaze to control fifo. The problem is the empty and full signal of fifo is synchronous to read/write clock .And the read/write clock is simply offered by GPIO. That cause the empty and full keep the state at last read/write operation. So I cannot use these signal to generate interrupt to tell microblaze to operate fifo. I think use EMC can solve the problem above. Am I right? Or, is there the better way to control fifo by microblaze ? Any suggest is welcome ! Many thanks !Article: 92703
On Mon, 5 Dec 2005 05:21:00 -0800, Simon <oceanfrea@hotmail.com> wrote: >Well, the intention of my vhdl code is to use floating numbers both positive and negative for multiplication. This is part of my entire neural computation. Seems like real variables are not synthesizable. Intresting to hear that David Bishop has a synthesizable REAL package, do u know where can i get it? Thanks. here http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/files.htmlArticle: 92704
I answered the unfriendly original posting with a constructive suggestion: Use the XOR of four accessible signals, which would fit into a single LUT. Specifying a single LUT doesn't look like a big manual effort to me... Peter AlfkeArticle: 92705
c d saunter wrote: > Greetings All, > > For the OS X readers out there, I found this article to be very usefull for enabling Spotlight > indexing of source files - it needs to be repeated for each extension (.vhdl, .vhd, etc.) > > http://www.macosxhints.com/article.php?story=2005052015041510 > > Cue Intel and XST on DarWine?... Now all we need to do is to convince Brands A, M and X to port their tools to OS X and we can finally dump our virus- and spyware-ridden PCs FOR GOOD. -aArticle: 92706
"Peter Alfke" <alfke@sbcglobal.net> schrieb im Newsbeitrag news:1133801967.244529.88170@g49g2000cwa.googlegroups.com... >I answered the unfriendly original posting with a constructive > suggestion: > Use the XOR of four accessible signals, which would fit into a single > LUT. > Specifying a single LUT doesn't look like a big manual effort to me... > Peter Alfke > Hi Peter, yes, you did even more than that in friendly manner to an unfriendly poster! It can not be expected that some core generator provides all possible cores and options to all the wishes we might have. If the intent of the OP was to design an efficient ALU then he pretty much needs to look at the FPGA primitives in order to understand what actual hardware resources will be used to implement what he needs. Antti PS there is nothing wrong with Xilinx people, and Xilinx software(coregen) does in most cases all that is reasonable, if something that 'could be useful' feature is missing there are or could be reasons for that missing feature.Article: 92707
ISE 8.1 release was planned for mid nov, now its mid december soon, I wonder if it is known how much more the ISE 8.1 release is delaying? Xilinx is advertising ISE webcast on Dec 14, I wonder if that will only cover soon to be obsoleted 7.1 or be focused on 8.1? Actually I am more waiting for the EDK 8.1 in the hope DDR2 support is added, but as EDK 8.1 release was projected 4 weeks after ISE 8.1 release I guess the EDK 8.1 actuall release date is slipping also :( most likely into 2006? AnttiArticle: 92708
I second that! I would love to see Brand X (you know who you are) to port their tools to OS X. It seems that alot fo the tools are Java based, it should be that hard. Furthermore, since they compile for X11 /Linux, porting (in theory) shouldn't be all that hard. Now that MAC is switching to Intel, that adds some warm fuzzies to porting. I would even just like to have the command line tools! That should be very easy to port! I really like the Mac system and hope to see the tools available soon -Eli Andy Peters wrote: > c d saunter wrote: > >>Greetings All, >> >>For the OS X readers out there, I found this article to be very usefull for enabling Spotlight >>indexing of source files - it needs to be repeated for each extension (.vhdl, .vhd, etc.) >> >>http://www.macosxhints.com/article.php?story=2005052015041510 >> >>Cue Intel and XST on DarWine?... > > > Now all we need to do is to convince Brands A, M and X to port their > tools to OS X and we can finally dump our virus- and spyware-ridden PCs > FOR GOOD. > > -a >Article: 92709
Dear Mr. Alfke, Thank you for your constructive suggestion. However, after 15 posts on this thread, I only got philosphical opinions, and answers to questions I did not ask. I still didn't get my questions answered. I repeat them again: What does the width P=Q+2 mean? And why is the available width (and the availability of overflow) different when only one number is signed, as opposed to both numbers being signed? What do signals A_SIGNED and B_SIGNED do? How do they affect the functionality of the core? IMHO, answers to these questions should be an integral part of the Adder/Subtracter specification referenced above. If you can show me that these questions are already answered in the specification, I will take back whatever I said. In the meantime, I still stick to my original question: What's wrong with Xilinx people? Cheers, FredArticle: 92710
Simon, I am asking the right persons who did some inventions before and might have good experiences with the problem I have met and I am asking for their advices. I didn't leak any information about my inventions. Never! But for advices I would like to ask and don't know well. How do you know a better layer who, for example, is the first time dealing with your knowledge area? When you ask layers, they always have advice for you, even though they are a novice one, or their knowledge is in different area. Weng Simon Peacock wrote: > You are asking the wrong people.. you need to ask a patent attorney. They > are better at filling in the grey areas which is what you want... After > all.. if what you were doing was smart.. it would already be done.. and if > it is.. you had better have a better attorney then they do :-) > > besides.. you are asking a public domain news group.. therefore anything you > try to patent later and have describe here has been released into the public > domain before the patent has been applied for :-) > > Simon > >Article: 92711
So should I assume that since BaseX is going away, that the WebPack will now support System Generator? RyanArticle: 92712
Fred, http://www.xilinx.com/ipcenter/catalog/logicore/docs/C_ADDSUB_V1_0.pdf I invite everyone to read the pdf describing the core. Especially pages 2, 3 and 4. Doesn't seem to be any mysteries here (to me). For example, it clearly states that if the result of the operation will generate a signed result (because one or both of the operands is signed), then signs are then automatically included.... P and Q are defined on page 3 in Figure 1, note 1. Perhaps "what is wrong with Xilinx people" is that we do not understand what it is you are asking. Austin juendme@yahoo.com wrote: > Dear Mr. Alfke, > > Thank you for your constructive suggestion. However, after 15 posts on > this thread, I only got philosphical opinions, and answers to questions > I did not ask. I still didn't get my questions answered. I repeat them > again: > > What does the width P=Q+2 mean? And why is the available width (and > the availability of overflow) different when only one number is signed, > as opposed to both numbers being signed? > > What do signals A_SIGNED and B_SIGNED do? How do they affect the > functionality of the core? > > IMHO, answers to these questions should be an integral part of the > Adder/Subtracter specification referenced above. If you can show me > that these questions are already answered in the specification, I will > take back whatever I said. > > In the meantime, I still stick to my original question: What's wrong > with Xilinx people? > > Cheers, > > Fred >Article: 92713
OK. Thanks Joe.
Well I don't really understand what the difference between OCLK and CLK are
so I now have them both connected to the fast 7x clock and I am now seeing
different signals on the q lines.
I also added a delay to the second DCM.
Here is the new code:
-- Company: Ai Vision
-- Engineer: Brad Smallridge
-- Create Date: 17:34:16 10/24/05
-- Design Name: LVDS
-- Module Name: top - Behavioral
-- Project Name:
-- Target Device: ML40x
-- Tool versions: 7.1.4
-- Description: Accepts LVDS Channel Link / Camera Link
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
port(
sys_rst_in : in std_logic; -- D6
gpio_exp_hdr2 : in std_logic_vector( 9 downto 0); -- HDR2 diff
gpio : out std_logic_vector( 3 downto 0) ); -- LEDs
end top;
architecture Behavioral of top is
signal reset1 : std_logic;
signal reset2 : std_logic;
signal reset3 : std_logic;
signal reset4 : std_logic;
signal cam1_xclk : std_logic;
signal cam1_clk7xdiv2 : std_logic;
signal cam1_lock7xdiv2 : std_logic;
signal cam1_clk7x : std_logic;
signal cam1_lock7x : std_logic;
signal cam1_x0 : std_logic;
signal shift1 : std_logic;
signal shift2 : std_logic;
signal q : std_logic_vector(6 downto 0);
signal test_counter_3 : std_logic_vector( 9 downto 0);
component dcmfx2
port(
clkin_n_in : in std_logic;
clkin_p_in : in std_logic;
rst_in : in std_logic;
clkfx_out : out std_logic;
clkin_ibufgds_out : out std_logic;
clk0_out : out std_logic;
locked_out : out std_logic );
end component;
component dcm_140_280
port(
CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK2X_OUT : out std_logic;
LOCKED_OUT : out std_logic );
end component;
begin
reset1 <= not sys_rst_in;
cam1_dcmfx2 : dcmfx2
port map(
clkin_n_in => gpio_exp_hdr2(6), -- 40 MHz
clkin_p_in => gpio_exp_hdr2(7), -- Differential pair
rst_in => reset1,
clkfx_out => cam1_clk7xdiv2, -- 140MHz
clkin_ibufgds_out => open,
clk0_out => cam1_xclk, -- 40 MHz
locked_out => cam1_lock7xdiv2 );
reset_delay_SRL16 : SRL16
generic map (
INIT => X"0000")
port map (
Q => reset2,
A0 => '1', -- 16 clock delays
A1 => '1',
A2 => '1',
A3 => '1',
CLK => cam1_clk7xdiv2,
D => cam1_lock7xdiv2 );
reset3 <= not( cam1_lock7xdiv2 and reset2 );
cam1_dcm_140_280: dcm_140_280
port map(
CLKIN_IN => cam1_clk7xdiv2, -- 140 MHz
RST_IN => reset3, -- from SRL16
CLK0_OUT => open,
CLK2X_OUT => cam1_clk7x, -- 280 MHz
LOCKED_OUT => cam1_lock7x );
cam1_x0_ibufd_inst : IBUFDS
port map (
O => cam1_x0,
I => gpio_exp_hdr2(1),
IB => gpio_exp_hdr2(0) );
x0_iserdes_master : ISERDES
generic map (
BITSLIP_ENABLE => FALSE, -- TRUE FALSE
DATA_RATE => "SDR", -- DDR SDR
DATA_WIDTH => 7, -- DDR 4,6,8,10 SDR 2,3,4,5,6,7,8
INIT_Q1 => '0',
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "MEMORY", -- model - "MEMORY" or "NETWORKING"
IOBDELAY => "NONE", -- delay chain "NONE","IBUF","IFD","BOTH"
IOBDELAY_TYPE => "DEFAULT", -- tap delay "DEFAULT",
"FIXED","VARIABLE"
IOBDELAY_VALUE => 0, -- initial tap delay 0 to 63
NUM_CE => 1, -- clock enables 1,2
SERDES_MODE => "MASTER", -- "MASTER" or "SLAVE"
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0')
port map (
O => open,
Q1 => q(0),
Q2 => q(1),
Q3 => q(2),
Q4 => q(3),
Q5 => q(4),
Q6 => q(5),
SHIFTOUT1 => shift1,
SHIFTOUT2 => shift2,
BITSLIP => '0',
CE1 => '1',
CE2 => '1',
CLK => cam1_clk7x,
CLKDIV => cam1_xclk,
D => cam1_x0,
DLYCE => '0',
DLYINC => '0',
DLYRST => '0',
OCLK => cam1_clk7x,
REV => '0',
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SR => reset3 );
x0_iserdes_slave : ISERDES
generic map (
BITSLIP_ENABLE => FALSE, -- TRUE FALSE
DATA_RATE => "SDR", -- "DDR" "SDR"
DATA_WIDTH => 7, -- DDR 4,6,8,10 SDR 2,3,4,5,6,7,8
INIT_Q1 => '0',
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "MEMORY", -- model - "MEMORY" or "NETWORKING"
IOBDELAY => "NONE", -- delay chain "NONE","IBUF","IFD","BOTH"
IOBDELAY_TYPE => "DEFAULT", -- tap delay "DEFAULT",
"FIXED","VARIABLE"
IOBDELAY_VALUE => 0, -- initial tap delay 0 to 63
NUM_CE => 2, -- clock enables 1,2
SERDES_MODE => "SLAVE", -- "MASTER" or "SLAVE"
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0')
port map (
O => open,
Q1 => open,
Q2 => open,
Q3 => q(6),
Q4 => open,
Q5 => open,
Q6 => open,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
BITSLIP => '0',
CE1 => '1',
CE2 => '1',
CLK => cam1_clk7x,
CLKDIV => cam1_xclk,
D => '0',
DLYCE => '0',
DLYINC => '0',
DLYRST => '0',
OCLK => cam1_clk7x,
REV => '0',
SHIFTIN1 => shift1,
SHIFTIN2 => shift2,
SR => reset3 );
led_test_counter_3_process:process(cam1_clk7x)
begin
if( cam1_clk7x'event and cam1_clk7x='1') then
if( reset3='1' ) then
test_counter_3 <= (others=>'0');
else
test_counter_3 <= test_counter_3+1;
end if;
end if;
end process;
gpio(0) <= q(0); -- OK -- looks like image data
gpio(1) <= q(5); -- OK
gpio(2) <= test_counter_3(9); -- OK
gpio(3) <= cam1_lock7x; -- OK
end Behavioral;
Article: 92714On Mon, 05 Dec 2005 11:50:27 -0800, Austin Lesea <austin@xilinx.com> wrote: >Fred, > >http://www.xilinx.com/ipcenter/catalog/logicore/docs/C_ADDSUB_V1_0.pdf > >I invite everyone to read the pdf describing the core. > >Especially pages 2, 3 and 4. > >Doesn't seem to be any mysteries here (to me). > >For example, it clearly states that if the result of the operation will >generate a signed result (because one or both of the operands is >signed), then signs are then automatically included.... > >P and Q are defined on page 3 in Figure 1, note 1. > >Perhaps "what is wrong with Xilinx people" is that we do not understand >what it is you are asking. > >Austin Actually there is something which can be quite confusing to the uninitiated in that document. In at least two places the "Output width" refers one to "Table 2" for specification (one of the referals is in table 2 itself on page 6, the other is on output width description page 3). These referals should say "Figure 1" instead. I think someone should review that document for accuracy.Article: 92715
Finding a patent attorney with FPGA experience might be difficult. One way to find one, I suppose, is to look at some of the prior art, and see if the attorney is close by and still in practice. The more work you do on your own, the cheaper it is in attorney fees. I don't see anything wrong with Weng asking questions to the group. He didn't reveal any innovation and was just asking about a procedural matter of patent writing. I am not even so sure that revealing the innovation would void his opportunity to patent the idea, only put him at risk for someone beating him to file, and he already has a provisional patent. I believe that the "offer for sale" still triggers starts a one year deadline to get your patent filed. And then after that there is a one year deadline to get you foreign patents. As to Weng's original question about provisional patents, I am not able to answer. When I applied for patents, provisional patents didn't exist. Brad Smallridge w w w . a i v i s i o n. c o m "Simon Peacock" <simon$actrix.co.nz> wrote in message news:4393db05@news2.actrix.gen.nz... > You are asking the wrong people.. you need to ask a patent attorney. They > are better at filling in the grey areas which is what you want... After > all.. if what you were doing was smart.. it would already be done.. and if > it is.. you had better have a better attorney then they do :-) > > besides.. you are asking a public domain news group.. therefore anything > you > try to patent later and have describe here has been released into the > public > domain before the patent has been applied for :-) > > Simon > > > "Weng Tianxiang" <wtxwtx@gmail.com> wrote in message > news:1133550146.547748.109980@g14g2000cwa.googlegroups.com... >> Hi Brad, >> Thank you for your response. >> >> 1. Yes, the 'legal' should change to 'acceptable'. >> >> 2. I agree with your opinion: "If you want a simpler and easy to follow >> explanation using the >> equation notation, you can put it in the preferred embodiment section. >> " >> The question arises when the logic equation in LUT is described in the >> preferred embodiment section, but their correspondent logical circuits >> are not described in a provisional patent application. When I file for >> regular patent application later, claims would be invalid because the >> appropriate circuits are not described in provisional patent >> application. >> >> So I want to know if there is an approved patent with logical equation >> in its claims or if there is someone having experienced similar >> scenario, but was declined by USPTO. >> >> Thank you. >> >> Weng >> > >Article: 92716
Antti Lukats schrieb: > if you write some construct that does add and sub and provides __separate__ > outputs for carry and borrow, then how should that be written in order to be > recognized for core extraction and what should the coregen actually > implement? Maybe it could be implemented the way Peter suggested? With a single LUT? Kolja SulimmaArticle: 92717
On Mon, 5 Dec 2005 15:21:07 +0000 (UTC), Brian Drummond <brian_drummond@btconnect.com> wrote: > >Hi all, > >I'm looking for ideas why a design using 43 DSP48s as multipliers might >not fit a V4LX25 with 48 DSPs... [...] >The design does use some RAMB36_36 blocks (I need wide I/O and not much >depth); so I wondered about the Spartan-3 RAMB/Mult packing restriction, >but I haven't seen any similar warnings about V4... And a definitive statement that there are no shared routing problems. >Before I try floorplanning the DSPs, has anyone seen any similar >failures? Some progress: floorplanning the DSPs yields different errors; I have been caught by the shared C bus into the subsequent addition logic. It seems XST has been aggressive enough in packing adders into the DSP blocks to make the resultant design unfittable. Since XST is told the target device, and must be aware of this basic limitation, I regard this as an XST bug. XST counts and reports the DSPs used; it must be equally easy to count the independent C buses... Yes I know: open a webcase. Well, if I can spare another day soon to make an easy testcase, I will. Meanwhile, there must be some way to control XST's use of DSP blocks; if I can find it in Answers, panic over. - BrianArticle: 92718
Brian Drummond wrote: > Hi all, > > I'm looking for ideas why a design using 43 DSP48s as multipliers might > not fit a V4LX25 with 48 DSPs... > > Symptoms are PAR failing with ten PLACE:119 warnings and a PLACE:120 > error. > > Most of the DSP48s are cascaded, but only in pairs (for 24x<16 mults), > so it doesn't look like AR20093 and AR20851 should apply. I'm not > (knowingly ) using BUFRs, so I don't think 20511 applies. And I can't > see any other AR that seems relevant; nor comp.arch.fpga posts. > > The design does use some RAMB36_36 blocks (I need wide I/O and not much > depth); so I wondered about the Spartan-3 RAMB/Mult packing restriction, > but I haven't seen any similar warnings about V4... > > Before I try floorplanning the DSPs, has anyone seen any similar > failures? > > - Brian A couple of possibilities: First, check to make sure you don't have a C port conflict. The two DSP-48's in a single DSP48 slice share the C-Port, so either both must use the same value on the CPort, or one must not use the CPort. The software looks for a specific combination of controls for the CPort to flag it as unused. If you don't match the template, it may not allow the two DSP48's to occupy the same slice. The magic incantation for a disabled CPORT is Cport input bits all equal '0', CREG attribute=0, CEC control='1' and RSTC control='1'. The tools supposedly look at the opmode to determine if the CPort is used or not: if it is a static opmode (all opmode bits connected to constants), then it should determine the Cport is unused without the magic incantation. If any bits of the opcode are not static, then the magic incantation is required. The second possibility is that if you are using ISE7.1, you have to have service pack 4. The earlier service packs had a bug with placement of instantiated DSP48s. If you are not using service pack 4, upgrade to it before you do anything more. Ironically, ISE6.3 didn't have the placer bug. I wound up using 6.3 exclusively until SP4 for 7.1 was released because of this issue. A third possibility is that the placer doesn't do a very good job figuring out placement of DSP48's, especially when there are some cascaded. Since you have over half of them utilized, there is a good chance you will have to put LOCs on them to get a suitable placement solution. There is no packing issue between DSP48's and RAMB16's. They are not co-located like they were in S3 and V2.Article: 92719
You can file for a US patent up to a year after having divulged the idea. That grace period does not apply to foreign filing. There you lose the right to file immediately after divulging. So, foreign filing is more demanding, not less. As far as equations vs LUTs, I think it makes no difference. But equations may be more widely understood. BTW, the OP is confusing in the example, using a logic equation that is actually AND and OR... Peter Alfke (with about 30 patents, but all filed by company patent lawyers)Article: 92720
MK, Thanks, I can refer this back to the document folks to look into. Austin mk wrote: > On Mon, 05 Dec 2005 11:50:27 -0800, Austin Lesea <austin@xilinx.com> > wrote: > > >>Fred, >> >>http://www.xilinx.com/ipcenter/catalog/logicore/docs/C_ADDSUB_V1_0.pdf >> >>I invite everyone to read the pdf describing the core. >> >>Especially pages 2, 3 and 4. >> >>Doesn't seem to be any mysteries here (to me). >> >>For example, it clearly states that if the result of the operation will >>generate a signed result (because one or both of the operands is >>signed), then signs are then automatically included.... >> >>P and Q are defined on page 3 in Figure 1, note 1. >> >>Perhaps "what is wrong with Xilinx people" is that we do not understand >>what it is you are asking. >> >>Austin > > > Actually there is something which can be quite confusing to the > uninitiated in that document. In at least two places the "Output > width" refers one to "Table 2" for specification (one of the referals > is in table 2 itself on page 6, the other is on output width > description page 3). These referals should say "Figure 1" instead. > I think someone should review that document for accuracy. >Article: 92721
Eli Hughes (emh203@psu.edu) wrote: : I second that! I would love to see Brand X (you know who you are) to : port their tools to OS X. It seems that alot fo the tools are Java : based, it should be that hard. Furthermore, since they compile for X11 : /Linux, porting (in theory) shouldn't be all that hard. Now that MAC is : switching to Intel, that adds some warm fuzzies to porting. I would : even just like to have the command line tools! That should be very easy : to port! : I really like the Mac system and hope to see the tools available soon Amen to that. The tools do (did?) run under Wine, and Wine is supported on the BSD and X11 layers of OS X (google for DarWine) - in fact it is possible to try the 'X' tools now under Wine on an x86 build of Darwin (free OS X BSD core) - I'm tempted to give that a go... With the Spotlight feature in OS X 10.4, the Mac has far surpassed any other platform I've used for writing code - it's really nifty selecting a signal name in a diagram, right clicking for 'search is spotlight' and instantly getting a list of all source files, data sheets and my own docs that reference it... I know FPGA dev is a small market and not worth much oulay for supporting odd platforms, but historically EDA tools favooured powerhouse Unix boxes, which coincedentally the Mac now is... ChrisArticle: 92722
"Simon Peacock" <simon$actrix.co.nz> wrote in message news:4393ddf2@news2.actrix.gen.nz... > '...' is a pause as opposed to '.' a stop. Even text to speech recognises > this. I will try to refrain... maybe > Yeah, sorry, I was just being a smartass. There's an interesting Wikipedia article all about the ellipsis. http://en.wikipedia.org/wiki/Ellipsis > > But reverse engineering can be done to anything. A copyright message is > all > you need to 'stop' it but that isn't usually enough. I myself have been > designing for 20+ years and have purposefully released things as GPL so > they > can be public. Other stuff (hardware and software) is most defiantly not > public. I have some rather flash UARTS, Ethernet Interfaces and E1 units. > These add value to both my pay-packet each month and to my companies > standing. They also make sure that each company review, there is a reason > to keep me employed. I've also started studying towards a BE-Tech and > possibly a Masters. So why do I think its not OK to copy? There are > multiple reasons above. > > The only time I would recommend breaking a copyright is when the company > is > defunct and you need to do an update but even then someone might have > walked > away with the copyright/patent. > > Simon > OK, but if 'reverse engineering' is just finding out how something works, then that's fine, yes? For example, books are copyrighted, but you can still read them. As to what you then do with the knowledge you gain, I guess that's where the line between good and evil is. If you read a copyrighted electronics text book, it's ok to use the knowledge you gain to design electronics, or even to write your own textbook, provided you don't copy verbatim. If you reverse engineer a FIR filter, it's ok (legally and morally?) to use the knowledge you've gained to create your own, provided it's not a direct copy. Maybe! In the US, maybe the DMCA has some ramifications as to the legality of reverse engineering. Interesting subject, I guess there's not a black and white answer. Cheers, Syms.Article: 92723
First of all, the document you referenced does NOT contain any more
information than the one I've referenced. It's just an older version of
the document I have referenced, and since I am using the newer version
of the core, that is the version of the document I'm looking at.
Second, since obviously not everyone here knows enough about binary
arithmetics to understand my questions, let me illustrate on an example
of adding/subtracting 2 3-bit signed numbers:
Using 2's complement representation, we can represent the following
numbers with 3 bits:
0 = 000
1 = 001
2 = 010
3 = 011
-4 =100
-3 =101
-2 =110
-1 =111
What is the lowest result we can get by adding/subtracting two 3-bit
signed numbers? Obviously:
-4 + -4 =
100
+ 100
=1000 = (-8 if all 4 bits are considered, or 0 if only 3 bits are
considered)
To store the valid result, we only need 4 bits.
What is the highest number we can get by adding/subtracting two 3-bit
signed numbers? Obvioulsy:
3+3 =
011
+ 011
= 0110 (6 if all 4 bits are considered, otherwise -2 if only 3 bits are
considered)
To store the valid result we again need at most 4 bits.
Now let's go with the terminology in the Core specification
(http://www.xilinx.com/ipcenter/catalog/logicore/docs/addsub.pdf ):
N=2, M=2 (because both numbers are three bits wide, so the range of
indices is 2:0).
Therefore, Q = MAX (N,M) = 2. Now, according to the specification, the
result can have width of [Q+1:0], which is [3:0] = 4 bits if both
numbers can be signed. This corresponds to my reasoning above.
However, if one of the numbers is unsigned, 4 bits are not enough. We
can illustrate that using the following example:
-4 - (7) = -11
If we represent -4 with a 3-bit signed number and 7 with a three bit
signed number, we need to sign extend them both (to 4 bits) to be able
to get correct result, and we need 5 bits to store the correct result
(-11 obviously cannot fit in 4-bits).
This explains why P=Q+2 (instead of Q+1) when one of the numbers is
unsigned, which was one of my original questions, but nobody would
answer it. And I didn't understand it until I performed this analysis.
There, I had to answer one of my questions myself.
However, this still doesn't explain what is the difference between the
following two cases:
(See Table 2 in
http://www.xilinx.com/ipcenter/catalog/logicore/docs/addsub.pdf to
understand what I'm talking about.)
1.
Operand A: Unsigned,
Operand B: Signed or by input pin (2nd row),
when the input pin is set so that the operand B is signed
and
2.
Operand A: Signed or by input pin,
Operand B: Signed or by input pin, (last row)
when the input pins denote that the operand A is unsigned and operand B
is signed
In both cases 1 and 2 above the operands are exactly the same, but the
availability of the overflow flag and the widths of the result are
different. In particular, I cannot get the result to be of the width
P=Q+2 in case 2.
WHY?????????????????????????????????????????
Also, in table 2, why is overflow not available if I select the width
of the output to be P=Q+1????
Article: 92724Frank (Francis.invalid@hotmail.com) wrote: ... : I don't know what you people are talking about. : Back to my question, how do I make a +-5V? 'Buy one' is the most sensible suggestion I've seen elsewhere on the thread. *BEWARE* Another one I've seen mentioned is to get 2 stock 5V supplies, A and B, and connect the +5V of A to the 0V of B, and call pair this 0V, thus making the 0V of A -5V and the 5V of B +5V. *BEWARE* This may or may not work - many lab power supplies and some bricks conenct the 0V from the DC side to the mains earth, so doing this with two such supplies will cause funny noises, bad smells and possibly worse as the magic smoke escapes. If you're not sure, don't try ths aproach! --- cds
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