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Look at other maturing areas: Commercial aviation has hardly gotten faster since the 747 arrived more than 30 years ago. Automobiles are hardly getting faster, except for at the lunatic fringe. 100 m dash has improved a few measly percent since Jesse Owens in 1936, 70 years ago ! Baseball records improve mainly through chemistry... But, as Austin wrote, we are still trying. It is now easier to make circuits smaller, make bigger chips, improve yield, and thus lower cost, than it is to make circuits faster. Peter AlfkeArticle: 102551
I am still raising hell inside Xilinx to make it easier for our customers to buy parts in small volume. I have not given up, never will... Peter AlfkeArticle: 102552
"Paul Leventis" <paul.leventis@gmail.com> wrote in message news:1147833178.442391.186290@i40g2000cwc.googlegroups.com... > To clarify, Altera's posted DDR2 SDRAM controller supports operation up > to 267 Mhz. There is another core that supports 333 Mhz operation > available by contacting your local sales rep. > > Paul Leventis > Altera Corp. > Thanks for the confirmation Paul, am already using it! SlurpArticle: 102553
Austin Lesea <austin@xilinx.com> wrote: >All, >A recent Intel presentation at an IEEE Workshop admitted that clock >frequency has max'd out, and now has to go down (not up) in order to not >create heat. >We have known that for years now. So has AMD. >The only choice is "multi." >Intel proposes a future with more than 200 x86 cores on one die, with a >"communications fabric" and many memories. All on one die. Small >software problem to be solved by the need to have it solved.... >One attendee of the conference (not me!) quipped, "sounds like you are >describing a FPGA..." >Boy did the presenter get mad! To be ccompared to a lowly FPGA! He was >spitting venom back at the attendee. "There is no comparison! FPGAs >are fine grained, and this is not!" >Sounds like if that is the only difference, the FPGA wins. Again. Maybe we'll see "Xilinx inside" within 20 years ;) Maybe machines with fpgas interconnected in a giant "web of interconnects" will be the feature. And parallell computeing as the only way to harness that capability. One could even take processed silicon plates and have them unmap faulty chips and interconnect the rest to have that functionality in one go.Article: 102554
MikeShepherd564@btinternet.com schrieb:
> Maybe the speed freaks can form their own newsgroup ("FPGA
> overclockers"?) Stand by for photos of water-cooled chips, lit with
> blue LEDs.
STRIKE!
You made my day!
(Ok, its evening now, but nevertheless)
Regards
Falk
Article: 102555Peter Alfke schrieb: > Commercial aviation has hardly gotten faster since the 747 arrived more > than 30 years ago. Same marketing problem in car industry. So the change to slogans like " . . you wont arrive faster, but much more relaxed." Not too bad. Maybe its time for the software to catch up. Regards FalkArticle: 102556
Peter, > assuming that you are using System ACE CF to configure your Virtex-4 FX Yep. > can load the boot code directly into the processor caches Thanks sounds very interesting. Any pointers or app notes on how to do this? (Sorry if I'm overlooking the obvious) Cheers, JonArticle: 102557
Michael Schöberl wrote:
> AFAIR there is only one (very old) chip (TI TSB something) that has
> firewire and can connect to an FPGA ... all the others have PCI or PCIe
Yes, the TSB12LV01B.
Goodbye,
Stéphane.
Article: 102558airtom@gmail.com wrote: > Hello, > Can anyone give i explanation for the disappointing 550Mhz performance > of V5 DSP slices? Couldn't we hope 1GHz multipliers with 65nm > technology? > > By the way, why are not the multipliers pipelined to increase the > performance?. Is there any chance to see pipelined multipliers in > virtex-6? Over on toms hardware they have been have a good time overclocking a very affordable $130 Pentium D 805 (dual core) from 2.66 GHz to something like 4.1GHz.bypassing the $1K cpus from Intel & AMD. But the speed gain varied from soso to 2x was achieved at very great cost in extra heat output, the nos are quite large. Typically the power starts at 95W but goes out to 200W or so on the cpu for the extra performance and needed water cooling and they also cranked the voltage way up for the last 10% stretch. The sweet spot I think would be to stay near the 3.6GHz limit of air cooling with the giant Zalman coolers and near the nominal voltage, the extra prize points just not worth the hassle. Now I said all that in 3 paras, they took 45 pages. Still my money is on parallel slower cpus too, but what else would a Transputer person say. All this stuff about 200 x86s on a chip doesn't seem so difficult considering Moores law applied to density over 25yrs. Since almost all software is sequential today and most of the software to exploit 200 cores will have to be rewritten anyway, the holdover of x86 ISA is really looking plain silly, just what will compatitibility mean to run old code on only 1 of 200 cores. If you design a cpu for massive scaling with support for fine grain concurrency you are better off with a design that does it well and you get many more than 200 on the same chip. Now if the array is programmed in a language that is 50/50 HDL and traditional Cxx, the difference between Transputer arrays and FPGA arrays is only a matter of granularity, they both execute concurrent processes. Personaly I think it will be along time though before Intel rediscovers how to make lots of cpus cooperate the way it was done 20 yrs ago already. John Jakson transputer guy FPGAs & Transputers 2 sides of the same coinArticle: 102559
Hi Antti, Do you have a link to this particular implementation? Is it open source? (I have googled, but it seems there are lots of different dosfs') Cheers, JonArticle: 102560
Does any buddy know How DCM work and does it require an input clock sigal or a output signal from external oscillator can work also. Plus how do i connect my code to the output of DCM ThanksArticle: 102561
"Michael Schöberl" <MSchoeberl@mailtonne.de> wrote in message news:446b5445$1@news.fhg.de... > > AFAIR there is only one (very old) chip (TI TSB something) that has > firewire and can connect to an FPGA ... all the others have PCI or PCIe Not true. There a few 1394a LLCs including the Philips chip. There are however no 1394b non-OHCI (read PCI) chips out there to the best of my knowledge. /MikhailArticle: 102562
This particular path doesn't seem to be routed (note there is an "e" on the net delay line). You don't need to be concerned about hold time errors due to estimated delays. HTH, Jim http://home.comcast.net/~jimwu88/tools/Article: 102563
Fizzy schrieb: > Does any buddy know How DCM work and does it require an input clock > sigal or a output signal from external oscillator can work also. Plus RTFM. > how do i connect my code to the output of DCM Instanciate a component from Coregenerator? Regards FalkArticle: 102564
On a sunny day (17 May 2006 11:17:54 -0700) it happened "JJ" <johnjakson@gmail.com> wrote in <1147889874.095362.247580@y43g2000cwc.googlegroups.com>: >Still my money is on parallel slower cpus too, but what else would a >Transputer person say. AMD came out with four core today.Article: 102565
Austin Lesea <austin@xilinx.com> wrote: > Intel proposes a future with more than 200 x86 cores on one die, with a > "communications fabric" and many memories. All on one die. Small > software problem to be solved by the need to have it solved.... > > One attendee of the conference (not me!) quipped, "sounds like you are > describing a FPGA..." > > Boy did the presenter get mad! To be ccompared to a lowly FPGA! He was > spitting venom back at the attendee. "There is no comparison! FPGAs > are fine grained, and this is not!" > > Sounds like if that is the only difference, the FPGA wins. Again. Except that there is no way to compile standard software to an FPGA, or even to compile freshly created software in anything near a normal programming langage. I hope you don't expect that the bulk of C/C++/Java/C# programmers will learn VHDL or Verilog. Of course programming a 200-core x86 processor in C/C++/Java/C# is a software engineering nighmare too, but with enough coding discipline there is at least a slim chance that you can get a team of ordinary programmers to produce working software for it. It is very hard to predict what a viable mainstream architecture will look like in ten years, but unless a lot of work is done to create better compilers for them, it surely isn't going to be an FPGA. I wouldn't bet on the 200-core x86 either, but that's because I'm an optimist. In an emergency, I would prefer a 10000-core Transputer to either of them, even if it would mean resurrecting Occam, but I hope someone can come up with something more imaginative.Article: 102566
"Fizzy" <fpgalearner@gmail.com> wrote in message news:1147890820.359958.300680@38g2000cwa.googlegroups.com... > Does any buddy know How DCM work and does it require an input clock > sigal or a output signal from external oscillator can work also. Plus > how do i connect my code to the output of DCM > > Thanks In fewer words than the manual which you should read: o The Delay Locked Loop is at the center. o A series of delay elements can provide a delay of an input signal such as that from an oscillator up to 20 ns, perhaps more. o This multi-element delay chain is tapped at the right point so the delayed input lines up with where you expect the next input to be at the reference point you select. o The DFS mode (frequency synthesis) taps and muxes this same delay line at multiple points to give you the M/D frequency ratio. The output from the DCM is a signal that often goes through a global clock buffer. Fizzy, Are you expecting comp.arch.fpga to be an instructional forum for you? It seems many of your posts are very green to the point that it doesn't look like you do basic research on the items you have question about. If you're new to programmable logic, welcome to the world ahead of you. Please read the data sheets, read the user guides, read the textbooks on how to code HDL. It's much more effective when this forum is used to help solve problems rather than provide basic instruction which otherwise has multiple sources. Happy coding, - John_HArticle: 102567
Peter Alfke <peter@xilinx.com> wrote: > I am still raising hell inside Xilinx to make it easier for our > customers to buy parts in small volume. > I have not given up, never will... Much luck for this ... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 102568
"Jon Beniston" <jon@beniston.com> schrieb im Newsbeitrag news:1147890013.855465.165380@j33g2000cwa.googlegroups.com... > Hi Antti, > > Do you have a link to this particular implementation? Is it open > source? (I have googled, but it seems there are lots of different > dosfs') > > Cheers, > Jon > learn too google :) its simple google larwe dosfs 3 link http://www.zws.com/products/dosfs/index.html AnttiArticle: 102569
"Jon Beniston" <jon@beniston.com> schrieb im Newsbeitrag news:1147889273.909649.117060@i40g2000cwc.googlegroups.com... > Peter, > >> assuming that you are using System ACE CF to configure your Virtex-4 FX > > Yep. > >> can load the boot code directly into the processor caches > > Thanks sounds very interesting. Any pointers or app notes on how to do > this? (Sorry if I'm overlooking the obvious) > > Cheers, > Jon > xil appnotes and ref designs pretty cool they use the USR ACCESS JTAG command to create virtual JTAG TAP master that then connects to the PPC JTAG tap and uses PPC ICE registers to load the caches. was pretty cool to see that implementation look at the ultracontroller II, the thing is all there anttiArticle: 102570
Peter Alfke wrote: > In general: Whenever you change one input of a LUT, there is no glitch > at the output if the two input addresses generate the same output > level. > I documented this 15 years ago... This information doesn't seem to have made it into the datasheets, which is why I asked that question a few months ago. EricArticle: 102571
I'm implementing a PCI104+ board which will have the opencores PCI bridge core. I've started with the suggested layout from Alteras PCI Megacore. But the choice of pins does not lend to a really clean layout. If I swap some of the pins around it will clean up quite a bit. I'm wondering if I'm asking for timing problems if I do this. I'm only planning to run the PCI at a leasurely 33Mhz, so I'm guessing it won't be a problem, as long as I keep it in the same pair of banks (5 & 6). Any thoughts or suggestions? Many thanks JoeyArticle: 102572
ghelbig@lycos.com writes: > And let's not forget that Xilinx owns the USB Vendor ID for the device, > so one can't re-use it without their permission. Why? Xilinx doesn't have a copyright, trademark, patent, or trade secret on their USB vendor ID. I don't recall that I've ever signed a contract with Xilinx (or anyone else) stating that I would not use the Xilinx USB vendor ID for something else (e.g., a Xilinx-compatible cable). Anyhow, you could always ship a product with some other USB vendor ID, and supply a tool that allowed the user to change the vendor ID to any numeric value of his or her choice.Article: 102573
Ed McGettigan <ed.mcgettigan@xilinx.com> writes: > I reread the thread and didn't see this asked. Why aren't you just > using our iMPACT software. Linux is one of the supported OSes after all. Doesn't work on 64-bit Linux. Jungo supports 64-bit, but Xilinx only supplies 32-bit versions of the proprietary binaries that get linked to the Jungo code. Please, please, please support 64-bit Linux in 8.2i, or at least in 8.2i SP1. Thanks! EricArticle: 102574
Guru wrote: > Here are some more details: > Desired clock increment is about 1 MHz. > Maximum jitter not specified. > 2 DCMs free for now. > > I think that DCM with dynamic FX ratios cannot produce such increments, Guru, A five minute exercise with an excel spreadsheet is all it takes to come up with the answer to the DCM resolution question. If starting with a 66MHz input clock (which from the exercise became clear to me that one would want to use the top frequency of the range to get best resolution), you can get very close to your desired resolution. There will be steps of 1.06MHz going from M/D of 15/31 to 1/2 and from 1/2 to 16/31, so the worst two steps happen to be adjacent, and at the very low end of your frequency range. The next worst step pairs are 0.76MHz, 0.71MHz, and 0.53MHz and 0.57MHz. The interesting thing to note is that the steps immediately prior and immediately after each of the worst case pairs are all on the order of 0.10MHz. So as a practical matter the DCM gets you extremely close. If your range of frequencies were just slightly less than 2:1 (i.e. 34MHz to 66MHz) you would be able to get a worst case 0.76MHz step size. The DCM solution will drastically reduce the jitter. This may or may not be significant in your application. The M/D values will want to be stored in a look up table (i.e. a blockram). Just more food for thought. Regards, Erik. --- Erik Widding President Birger Engineering, Inc. (mail) 100 Boylston St #1070; Boston, MA 02116 (voice) 617.695.9233 (fax) 617.695.9234 (web) http://www.birger.com
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Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z