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Since Spartan 3e is a generation later and 90nm instead of 130nm, I expected it to be faster than Virtex 2p. But it is actually quite a bit slower. Here are some numbers from .twr files: xc3s500e-4 (advanced) Tcko=0.455ns F4-X Tilo=0.778ns G3-Y Tilo=0.824ns Tsrck=0.966ns Tcinxb=0.714ns xc2vp4-5 (production) Tcko=0.419ns F2-X Tilo=0.321ns G1-Y Tilo=0.351ns Tsrck=0.768ns Tcinxb=0.575ns So Spartan 3e ends up being about half the speed of Virtex 2p. Am I understanding this correctly? Why is it slower? Alan Nishioka alan@nishioka.comArticle: 91626
Antti Lukats wrote: > "Marco" <marco@marylon.com> schrieb im Newsbeitrag > news:1131461408.810685.93980@g14g2000cwa.googlegroups.com... >> How could I implement a bus in my Spartan3 to let it communicate >> thorough a 16bit wide, 100MHz bus with a Blackfin DSP? Thanks, Marco >> > > its very easy. > > 1 Open BlackFin DSP datasheet in Acrobat > 2 Start Xilin ISE, New Project > 3 Proceed implementing your bus interface > > simple as that! > > Sorry Marco, there is no answer to your question. It all depends how you > want to connect the BlackFin bus inside the FPGA and that is something you > must know - we dont. Marco, useful buzzwords include 'DCM' and BUFG. JeremyArticle: 91627
Just wanna make sure we are talking about the same thing. Your situation: You have an FPGA and another device being clocked by the same signal. The FPGA outputs some data to the external device. On active clock edge 1 (for example), the FPGA will output some data. The external device will register that data (as input) on active clock edge 2. Now you want to be able to satisfy the setup time of the external device's input flip flop, which means you want to be able to specify the MAXIMUM delay from the 1st active clock edge to the FPGA data being output. That can be done using the OFFSET-OUT-AFTER constraint in the UCF. It will take into account not only the delay of the data but also of the clock that activates the output flip flop. Kunal @ XilinxArticle: 91628
Frank schrieb: > I am outputting a data with a clock 12.5MHz, which will latch the data > into external chip whose input delay is unknown. I am trying to connect > eight FPGA IO pads to the same clock, and delay each of them 1/8 of > my main clock period, i.e. 10 ns, expecting one of them will work correctly. > What constraint can I use in UCF file? > > Thanks in advance > > > Hi Frank, I would recommend you to use or generate somehow a higher Clock frequency. 50MHz would be just fine. Unfortunately you may be unable to generate this Clock from your 12.5 MHz with the builtin DLLs/DCMs for these require some minimum frequency (see the datasheets for details). So, when I assume for a moment that you have a 50 MHZ Clock available you can build two cyclic shiftregister that shifts a single '1' over 4 FFs. One must be clocked by the rising edge one by the falling edge of the 50 MHz. Then you can use these 8 outputs as clock enable signals for your output FFs which also have to use rising and falling edge clocks alternating from one FF to the next. A 12.5MHz Clock for the rest of your design can be derived from that 50 MHz easily by the DLLs/DCMs and your output value can be stored in an internal register that feeds the IOB-FFs which take the values with their respective delays due to the generated CE-Signals. Thus the design wil be totally synchronous, and the Output to PAD delays of the IOBs should be quite equal anyway. have a nice synthesis EilertArticle: 91629
Hi Fahad, Yes but only if you have a floating license and Modelsim SE/LE in your bundle. Spectrum is not supported under Linux but Precision is. HDL Designer works OKish under Linux but you might have to tweak the fonts to make it looks nicer. Also installing P&R tools is still a bit of a hit and miss, if you have Redhat WS 3.0 (or WhiteBox/CentOS 3.5) you should be OK. Hans www.ht-lab.com "fad" <fahad.arif@gmail.com> wrote in message news:1131519282.510124.10500@g44g2000cwa.googlegroups.com... > Does anyone know the process of installing FPGA Adv on Linux based > system? Does FPGA Adv be have Linux support or not? > I have to install modelsim and leonardo spectrum on linux machine > separately as well. please suggest if anybody has already done the > process. > Regards, > Fahad >Article: 91630
"Alan Nishioka" <alan@nishioka.com> writes: <snip> > So Spartan 3e ends up being about half the speed of Virtex 2p. > Am I understanding this correctly? Why is it slower? > Because it was designed that way :-) Spartan is designed for cheapness (and sort-of low-power). Virtex is designed for speed and everything else is secondary. From S-3 onwards (I believe) the designs have diverged, so S3 is not simply a cheapened V-II, unlike Spartan-II was from Virtex(I). Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.trw.com/conektArticle: 91631
Maybe someone can make a suggestion: I'm building a board with a Coolrunner XPLA3384 on it, however, my intitial (very very basic) test code is running into problems... The device is programmed and verified successfully, but all (configured) output pins remain at ground. Pins not configured as outputs a pulled up by the internal pullup resistors, just as when the device is in an erased state. I'm using dedicated JTAG pins to configure the device I've checked the power and ground pins, all are looking good, same goes for short circuits between the pins and ground... I feel I'm missing something small - can anyone perhaps make a suggestion on where to look? Thanks johannes http://students.sun.ac.za/~jvdhArticle: 91632
bh top posted: [snip] > Have you verified that you can receive the 'same' frame if it > is sent via a different source (not your FPGA)? > > > "ashwin" <achiluka@gmail.com> wrote in message [snip] Ethereal uses WinPcap, which allows you to send test packets e.g. http://www.winpcap.org/docs/man/html/group__wpcap__tut8.html Have you tried setting the destination MAC address field to the broadcast address?Article: 91633
Frank schrieb: > I am outputting a data with a clock 12.5MHz, which will latch the data > into external chip whose input delay is unknown. Other posters helped you with your suggested approach. But I doubt that what you are trying to do is neccessary. Whtat do you men by input delay? If data is clocked into a device usually there are two important parameters: Setup and hold time. It should be possible to find out what these are for your device. If you give us a part number maybe someone even knows the values. Also, for virtually all devices that I know of both parameters are an order of magnitude smaller than 40ns. Therefore if you register the data at the opposite edge of your clock you are very likely meeting both requirements. Also, hold times tend to be very small. Probably smaller than the Tco parameter of the FPGA. If this is true you can achieve a simpler design by registering the data with the same clock edge for both devices. Kolja SulimmaArticle: 91634
just one question (not directly related to the topic)... if i write A= C+ D in the verilog and choose optimize for speed will the tool generate the CLA adder ???Article: 91635
"backhoes" <nix@nirgends.xyz> wrote in message news:dkur6u$jgj$1@hermes1.rz.hs-bremen.de... > Hi Frank, > I would recommend you to use or generate somehow a higher Clock frequency. > 50MHz would be just fine. Unfortunately you may be unable to generate this > Clock from your 12.5 MHz with the builtin DLLs/DCMs for these require some > minimum frequency (see the datasheets for details). > Eilert, You can use the DCMs with clock inputs down to 1MHz as long as you use "frequency synthesis" mode, i.e. use the CLKFX output(s). The output clock must be greater than 24 MHz. I'm using the "datasheets for details"! ;-) Cheers then, Syms.Article: 91636
There are two major reasons, one is personal the other is technical. As for the personal reason, I began using programmable logic about six or seven years ago, back when HDL synthesis was a "big thing" and everybody was charging major money for their synthesis engine. At that time, the company I was working for used Xilinx Spartan devices with Foundation 3.1. It appeared that everytime we turned around that Xilinx wanted more money for maintance and licensing on their tool set. I personally find this practice of constantly having to grease palms that have already been overpaid distastefull. One day, I met with the rep from Altera, who was a direct employee not from a marketing firm, and he suggested that I try their Maxplus2 out. In the next few months, I started on a project and tried the Altera toolst. Not only did I find the tools far easier to use, I found getting tech support to be much easier. I was almost always able to get someone on the phone immediatly or if that didn't solve it, in person.. As far as tehcnical reasons go, when I started with the company I am at now, my first project was to develop an application around a set of hardware designed by a sister division for a different product. At the heart of each of the PCBs in the product was an XC95xx. Unfortunately, the product line was almost done in by electrical noise issues that effected the Xlinx device on one of the critical boards. I redesigned the board around an Altera device and the problems disappeared. While it is likely that there are factors to the redesign other than just changing the device that influenced the noise immunity, according to the Xilinx Rep, the Altera Max 7000 device that was used is a newer technology process than the 9500 series and is inherently more noise immune. Since that time, I have developed a number of boards with Altera CPLDS and FPGAs (Cyclone 1). I have found them extremely easy to use and they haven't given me a bit of trouble. As far as development tools go, I spent about $200 or so to by a USB byteblaster to program the Cyclone devices. I received my first programmer a Byteblaster MV from the Altera Rep for free . This is a far cry from the thousands that were spent on Foundation. I applaud Altera for their policy of providing decent quality tools, that unless you are developing for their newest embedded cores, are free. Personally, I think that Maxplus2 was better than their Quartus tools from a schematic editing standpoint. While I know that schematic editing is passe, I still usually design by having a top level schematic of VHDL blocks.Article: 91637
"Udo" <WeikEngOff@aol.com> wrote in message news:1131570283.253561.155650@o13g2000cwo.googlegroups.com... > Hello, > > how can I initialize a 8k*8 Block RAM with an Intel Hex-File? > > > Thanks for any hint. > Udo > Udo, Check out the Xilinx app. DATA2MEM . It uses a file of the form .mem which contains the data to be loaded. The format is pretty similar to Intel Hex, a simple perl script would take a few minutes to write to change from one format to the other. Some guy on here was asking about DATA2MEM a month or so ago, check out his thread on Google groups for some newbie hints, and save yourself the pain I went through trying to get it to work!! HTH, Syms.Article: 91638
But Gabor i did observed problems while connecting the bufgp to an ordinary I/Opad. It is listed in the lib.pdf that the bufg can take input from global clock pins. One more thing i want to as is that isnt it better to use the clock directly clocking the F/F and to use the strobe to control the input of the F/F rather than mixing the strobe and clock and then use the new output to clcok the F/F. thanksArticle: 91639
Hi, We are using EDK 6.3 on PPC and Microblaze designs. I will have to write bootloaders for loading firmwares and OS from flash to BRAM/SDRAM. Does anyone know where I could find step by step tutorials and examples ? I'm looking for information for starting from scratch and explaining the way it works ! Small examples are welcome. Thank you. Stéphane.Article: 91640
Alan The figures you show are exactly what I would expect. Xilinc and Altera both have low cost, lower performance, families as well as high performance families. Spartan-3 is made to have a sell cost that is very cheap compared to V2-Pro. There is an architectural inheritance but new silicon mask sets for any family are customised to the purpose be it low cost or high speed. There are also commercial reasons why you won't get very high speed at very low cost. Typically the higher cost families have been used to introduce new technology for high speed, higher margin parts, and to get the development costs back reasonably quickly. The Spartan-3 release didn't follow that scheme and the new technology (90nm) was used instead for low cost. It may be an indicator of the growth in the size of the FPGA market that Xilinx choose to start with the low cost family on the new technology and to presumably to recover their costs on larger volumes of chips than just larger margin silicon. Compared to low cost silicon of a few years ago, and of even leading edge silcon early or pre-Virtex, Spartan-3 speed is very good and we are running designs here regularly at clock rates of between 50-150MHz. More with some effort. That kind of clock rate covers a large percentage of designs out there and offers very good value. John Adair Enterpoint Ltd. - Home of Raggedstone1. The Cheap Spartan3 Development Board. http://www.enterpoint.co.uk "Alan Nishioka" <alan@nishioka.com> wrote in message news:1131597894.391304.28580@g14g2000cwa.googlegroups.com... > Since Spartan 3e is a generation later and 90nm instead of 130nm, I > expected it to be faster than Virtex 2p. But it is actually quite a > bit slower. Here are some numbers from .twr files: > > xc3s500e-4 (advanced) > Tcko=0.455ns > F4-X Tilo=0.778ns > G3-Y Tilo=0.824ns > Tsrck=0.966ns > Tcinxb=0.714ns > > xc2vp4-5 (production) > Tcko=0.419ns > F2-X Tilo=0.321ns > G1-Y Tilo=0.351ns > Tsrck=0.768ns > Tcinxb=0.575ns > > So Spartan 3e ends up being about half the speed of Virtex 2p. > Am I understanding this correctly? Why is it slower? > > Alan Nishioka > alan@nishioka.com >Article: 91641
"sjulhes" <t@aol.fr> wrote in message news:43734c2c$0$18830$636a55ce@news.free.fr... > Hi, > > We are using EDK 6.3 on PPC and Microblaze designs. > > I will have to write bootloaders for loading firmwares and OS from flash > to > BRAM/SDRAM. > > Does anyone know where I could find step by step tutorials and examples ? > > I'm looking for information for starting from scratch and explaining the > way > it works ! > > Small examples are welcome. > > Thank you. > > Stéphane. > > go into Xilinx site and search for xapp482.pdf MarcoArticle: 91642
I was looking for some documentation on recent speed and logic density enhancements on modern fpgas (i have searched xilinx and IEEE with only mildly successful results). I am submitting a paper to a computer vision conference (CVPR) and am trying to promote the use of fpgas for embedded computer vision and pattern recognition applications. I am basically looking for a document that shows a comparison of FPGAs with GPPs or DSPs and a forcast of trends into the future with regard to speed and logic density of FPGAs when compared to speed/density of GPuPs. points of comparison and interest: power, fixed point calcs, floating point calcs, onboard memory/BRAM, clock rate, DSP and scientific comp. related ops comparison (MACS, matmul, etc) thanks for your help, geoffreyArticle: 91643
has anyone in the dig. design and reconfig. computing community looked seriously at open source hardware design libraries, working toward a hardware paradigm similar to that in the open source software community? I am aware of the existence of opencores.org, but this seems like a small first step, of which many more could be taken toward improving the availability and ease of access and use of open source logic designs. does anyone have any thoughts or knowledge or any thing to say about an open source hardware paradigm? thanks, Geoffrey Wall Masters Student in Electrical/Computer Engineering Florida State University, FAMU/FSU College of Engineering wallge@eng.fsu.edu Cell Phone: 850.339.4157 ECE Machine Intelligence Lab http://www.eng.fsu.edu/mil MIL Office Phone: 850.410.6145 Center for Applied Vision and Imaging Science http://cavis.fsu.edu/ CAVIS Office Phone: 850.645.2257Article: 91644
yes, but not really clear to understand ! "Marco" <marcotoschi@nospam.it> a écrit dans le message de news: dkvjvn$gej$1@nnrp.ngi.it... > > "sjulhes" <t@aol.fr> wrote in message > news:43734c2c$0$18830$636a55ce@news.free.fr... > > Hi, > > > > We are using EDK 6.3 on PPC and Microblaze designs. > > > > I will have to write bootloaders for loading firmwares and OS from flash > > to > > BRAM/SDRAM. > > > > Does anyone know where I could find step by step tutorials and examples ? > > > > I'm looking for information for starting from scratch and explaining the > > way > > it works ! > > > > Small examples are welcome. > > > > Thank you. > > > > Stéphane. > > > > > > go into Xilinx site and search for xapp482.pdf > > Marco > >Article: 91645
I also started out with Foundation 3.1 and I agree with everything you have saidk NoWay2. Also, Xilinx tech support is getting worse. Anyone used to be able to call and get someone on the phone immediately. Now they have shipped a lot of it overseas, which isn't a big deal as long as it's quality support. I'm still undecided as to whether it is. The real kicker now is that in order to talk to someone over the phone you need to purchase at least 1000 parts a year. Otherwise, you're stuck with a worthless exchange of emails with a day or two delay with someone in China who is not able to call you even if the need should arise. To give Xilinx a little credit, their tools have come a long way from Foundation 3.1. That tool was a train wreck. With the newer tools, ISE7.1, there is no longer a need for licenses. Their tools are free unless you're developing on their newest FPGAs. Xilinx also has an incredible website with a huge amount of documentation.Article: 91646
I seriously doubt you see anything much bigger that the snippets on Open Cores. This is may be different in the educational community where open source is much more widely used, but in industry very few would be willing to give away what they spent zillions of man hours developing. Try going to to nVidia and asking for the source to their logic models of their video chips! Why would they want to give the competitors their design? I understand that a lot of open source is aimed to be portable across many systems. People tend to confuse HDL as 'software'. It is not a program like a 'C' program for a CPU. It is actually describing hardware and often has to use primitives that are only available on certain ASICs, FPGAs, etc. You rarely optimize for portability. When I need to get something running fast, you MUST optimize for the architecture of your medium to push clock speed, etc. The HDL you end up may not be very useful to someone using a different ASIC. Furthermore, many man-hours are spent in this process and most companies are not willing to do this for somebody else's benefit. One could make the argument that there should be a library for simple constructs that would be common to all FPGA, ASIC platforms. What you would end with is the equivalent of a C library that only adds to numbers. Not very useful for serious work. In the FPGA world, there are lots of places were you can buy working IP cores that are fully documented and supported. My boss isn't willing to spend 4 times the cost of working 3rd party IP to debug an open source version that isn't documented that well and has no support. The problem in this model is the same problem with the open source software community. While some of the products are nice, they are plagued with *lots* of useless projects/libraries that take a week to install, have poor documentation and no support. Why would I want to spend my time on that. Most forget that while open source stuff is free , it may take 4 times the time to use. This is only cheaper if your time doesn't cost a whole lot. All this being said, I really like the open cores site. I would use it for hobby/side projects. As for serious commercial projects, I place more trust in either my own or paid for IP that is tested and supported. -Eli g.wall wrote: > has anyone in the dig. design and reconfig. computing community looked > seriously at open source hardware design libraries, working toward a > hardware paradigm similar to that in the open source software community? > I am aware of the existence of opencores.org, but this seems like a > small first step, of which many more could be taken toward improving the > availability and ease of access and use of open source logic designs. > does anyone have any thoughts or knowledge or any thing to say about > an open source hardware paradigm? > > > thanks, > > Geoffrey Wall > Masters Student in Electrical/Computer Engineering > Florida State University, FAMU/FSU College of Engineering > wallge@eng.fsu.edu > Cell Phone: > 850.339.4157 > > ECE Machine Intelligence Lab > http://www.eng.fsu.edu/mil > MIL Office Phone: > 850.410.6145 > > Center for Applied Vision and Imaging Science > http://cavis.fsu.edu/ > CAVIS Office Phone: > 850.645.2257Article: 91647
Geoffrey, the most important aspect is the freedom in systems architecture offered by FPGAs. This allows you to use massive parallelism for higher performance, or serial processing for lower cost etc. If you look just at clock rate, FPGAs suffer a penalty imposed by the interconnect flexibility. You have to compensate for that by taking advantage of the architectural flexibility offered in FPGAs. And do not forget (dynamic) reconfigurability... Peter Alfke, Xilinx ApplicationsArticle: 91648
Hi, It's a few days since I can't put a FF into IOB register: XST (7.1.4) option: -equivalent register removal: NO -pack IO registers into IOB : YES MAP (7.1.4) option: -pack IO registers into IOB : For inputs and outputs moreover I applied the attribute on the name of the clocked process that represents the FF: attribute IOB of iob_t : label is "TRUE"; It is for a bidirectionnal signal: input is registered into IOB, output is also registered there, but the duplicated tristate_enable registers don't want to go inside the OLOGIC (Virtex 4). Each of them is not that far, but not into the IOB! Any suggestion?Article: 91649
John,
can you please post the MAP error message?
Thanks,
Aurash
john wrote:
>Hi,
>
>It's a few days since I can't put a FF into IOB register:
>
>XST (7.1.4) option: -equivalent register removal: NO -pack IO registers into IOB : YES
>
>MAP (7.1.4) option: -pack IO registers into IOB : For inputs and outputs
>
>moreover I applied the attribute on the name of the clocked process that represents the FF: attribute IOB of iob_t : label is "TRUE";
>
>It is for a bidirectionnal signal: input is registered into IOB, output is also registered there, but the duplicated tristate_enable registers don't want to go inside the OLOGIC (Virtex 4). Each of them is not that far, but not into the IOB!
>
>Any suggestion?
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
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