Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
I understand that Xilinx will be doing a Floating Point Unit that uses the APU interface. I haven't been able to find out how big a foot print it will have within a given FPGA. I also don't know what the cost will be. Has anyone heard anything about this? ThanksArticle: 83376
Mac wrote:
>On Wed, 27 Apr 2005 17:18:03 -0700, kevin wrote:
>
>
>
>>"Hope this helps."
>>
>>It absolutely does! Thanks guys.
>>
>>Kevin
>>
>>
>>
>
>Keep in mind that the output of this type of DDS will NOT produce a 50%
>duty cycle (which is something you asked for), except at frequencies whose
>period is an even number of counts of the master clock (i.e., Fmaster/2N).
>For other frequencies, the maximum deviation from 50% duty cycle is one
>master clock. For example, if you tried to go output 75 MHz, with a master
>clock of 160 MHz, you would have a series of 125 ns periods with an
>occasional high or low stretched out by an extra 62.5 ns to keep the
>average frequency on track.
>
>Still, in your case, if you multiply the 40 MHz up to 160 MHz (go higher
>if you can) then implement a 32-bit phase accumulator, you should be close
>enough to 50% duty cycle and have small enough frequency steps to make
>most people happy.
>
>One way to reduce the jitter a little is to use a DAC type of approach,
>and a little bit of analog circuitry. You would take, say the 4 most
>significant bits of the phase output, and feed them to a phase to
>amplitude lookup table, then feed the output of the lookup table to a
>series of outputs with well-chosen resistor values.
>
>The resistor values would be, for example, 200, 400, 800 and 1600, Ohms.
>Of course, those resistor values don't exist. So you would pick the
>closest ones you can. These resistors would then all be connected
>together. This common node, then, would be your analog output. You could
>buffer it with an op-amp, and feed the op-amp to a 11.2MHz low pass
>filter, and you would have a pretty good 9MHz - 11.2 MHz sine wave, all
>things considered. The sine wave could then go to a comparator, and the
>comparator output would have much lower jitter than you would if you
>didn't use any analog techniques. This 9-11 MHz digital signal would be
>the x16 signal, and you would create the base signal by dividing it down.
>
>Total external parts: 4 resistors, 1 package with two or four op-amps, one
>comparator, and a few capacitors. If you used a quad op-amp, you could
>make a really good low-pass filter, and really cut the jitter down.
>
>If this all sounds like too much complication and bother, well, it
>probably is, but then again, maybe it will appeal to you (or the customer.)
>
>Of course, you could also use a DAC instead of the four resistors. You
>could even use an 8-bit DAC which would really help cut down the jitter,
>but would force you to implement an 8-bit output phase to amplitude
>converter.
>
>And the ultimate would be to put an Analog Devices DDS on the board. Then
>you would use the FPGA to generate the 160 MHz clock, program the DDS, and
>divide down the frequency output of the DDS by 16. That is what I would do.
>
>--Mac
>
>
>
for many applications, using an external circuit such as a DAC or AD
DDS would be extreme overkill. One such overkill application would be
generation of a clock for a UART.
One way to look at the output of the pahse accumulator I described
earlier is that it is a perfect squarewave resampled by your master
clock. If the master clock is not a neat multiple of your generated
frequency, then you'll have jitter of up to a clock cycle. You can
reduce the jitter by using a faster master clock (with modern FPGAs
there is no reason you couldn't quadruple your 40 MHz master clock and
run the DDS at 160 MHz).
It all comes down to what are your requirements for the generated clock.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 83377Hi Jesse, I'm sorry, I meant to post that the last time I installed the Nios kit was with Nios I. My apologies. Very happy to hear they can co-exist now. -- Pete kem...@yahoo.com wrote: > Hi Pete, > > There were issues with multiple Cygwin installations long ago, but I > think they were corrected in the Nios I 3.1/3.2 time-frame... as such > I'm surprised to hear that you ran into trouble with Nios II - perhaps > something else is going on? > > Just as a reference point, I personally use a generic Cygwin > installation installed in a separate location from Altera's (which now > goes into quartus/bin/cygwin)... in fact we (as Nios/SOPC developers at > Altera) use a separate Cygwin installation extensively (on our desktop > PCs as it provides a nice cross-platform development/build-system > setup; so many people have this working. > > The one tip that comes to mind to ensure that wires don't get crossed. > I can think of two things: environment variables, and cygwin1.dll > (there are a number of versions of it and you want whatever shell you > open up to be using the most recent one). > > I would carefully check that, when you open your Altera SDK shell, your > environment variables & path do not point to your separate standalone > Cygwin installation -- this is how things are on my setup. I also > checked what my environment looks like with my standalone Cygwin > installation, and to my surprise there were path entries pointing to > the Altera installation of Cygwin. Everything functions normally, > though. > > You might also try a quick registry scan to see if there are any relics > from the past floating about. In my working setup, I started from a > clean PC with nothing on it, and installed Quartus and then Cygwin > separately. > > If this doesn't help feel free to send me an email offline and I'll > send you a cut & paste of what my environment looks like. > > Jesse Kempa > Altera Corp. > jkempa at altera dot comArticle: 83378
In article <d4r6o402p2@enews3.newsguy.com>, Phil Tomson <ptkwt@aracnet.com> wrote: >FYI: >I found that it was necessary to unzip the self-extracting exe file for >webpack 7.1 and then run 'wine setup.exe'. If I tried to run >'wine WebPACK_71_fcfull_i.exe' wine would report an error about the exe >not being a Win32 executable. So first run: >'unzip WebPACK_71_fcfull_i.exe' and then run 'wine setup.exe'. (thanks >to Uwe Bonnes for pointing this out) > It seemed to install OK, but when I try to create a new project I get a dialog box that comes up and says: "no device data files have been found in this installation, please verify that the software is installed properly" If I click OK a couple of times it lets me continue to the project setup wizard where you enter the project name and location. There is a box which asks you to select the type of top-level module for the project there as well, but the pulldown menu is empty. When I click 'next' nothing happens... probably because type of top-level module isn't being set. Has anyone seen this? I tried both 6.3 and 7.1 and got similar results. I'm running wine --version 20050310 PhilArticle: 83379
Phil Tomson <ptkwt@aracnet.com> wrote: > FYI: > I found that it was necessary to unzip the self-extracting exe file for > webpack 7.1 and then run 'wine setup.exe'. If I tried to run > 'wine WebPACK_71_fcfull_i.exe' wine would report an error about the exe > not being a Win32 executable. So first run: > 'unzip WebPACK_71_fcfull_i.exe' and then run 'wine setup.exe'. (thanks > to Uwe Bonnes for pointing this out) Phil, wine WebPACK_71_fcfull_i.exe runs fine for me, at least I tested until the licence acceptance was asked. Are you sure you didn't run out of filespace or such problems? How long is a relay log up to the error? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 83380
In article <d4rbm4$9dh$1@lnx107.hrz.tu-darmstadt.de>, Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote: >Phil Tomson <ptkwt@aracnet.com> wrote: >> FYI: >> I found that it was necessary to unzip the self-extracting exe file for >> webpack 7.1 and then run 'wine setup.exe'. If I tried to run >> 'wine WebPACK_71_fcfull_i.exe' wine would report an error about the exe >> not being a Win32 executable. So first run: >> 'unzip WebPACK_71_fcfull_i.exe' and then run 'wine setup.exe'. (thanks >> to Uwe Bonnes for pointing this out) > >Phil, >wine WebPACK_71_fcfull_i.exe runs fine for me, at least I tested until the >licence acceptance was asked. Are you sure you didn't run out of filespace >or such problems? How long is a relay log up to the error? I suppose it's possible that I ran out of space, however, the error message from wine about WebPACK_71_fcfull_i.exe not being a valid Win32 executable came back right away. The installation _seemed_ to proceed OK by running 'wine setup.exe', however, I can't create projects seemingly because it complains about 'no device files found' (see my other post). PhilArticle: 83381
Hello, I use Quartus 4.2 SP1 WebEdition for my work. The Hardware I built gets data from an external source with 40Mbit/s which has an 16Bit multiplexed bus with an High/Low word and Strobe Pin to tell me when data is valid and which is the high and wich is the low word. After that I analyse the data an give it to an PC. In the functional simulation everything works fine, but when I test this in reality, the demux unit does not seem to work right, with Signal Tap II I can see that the values comming out of this are something but not the values which are feed into the FPGA. But then the analysis of the worng values works fine, only the demux unit seems to be broken. Are there any tools to simulate such a behaviour or can you recommend me something to do ? Or can I change something in the timing options of Quartus ? Thanks in advance. With best regards. AlexArticle: 83382
We are looking for a Sr. Digital FPGA Engineer to work as a senior
member of our RFID reader design team. Primary responsibility will be
FPGA design of digital modems working closely with our system engineers
on implementing DSP blocks using Xilinx FPGA components. Additional
responsibilities include digital board level design using FPGA and
embedded processors such as the Intel X-Scale. Will participate in the
integration of hardware and firmware and frequently interact with our
embedded software team. Looking for BSEE and 10+ years exp; expert
knowledge of Xilinx FPGA technology, Verilog, design tools, and
processes; digital board-level design exp. w/ successful production
release; and ability to follow and implement proven design methodology
including architectural reviews, design documentation, and design
validation. Experience with wireless products, modems, or other
communication products; DSP hardware design; and Intel X-Scale processor
system design are desired.
This opportunity is located in Newport Beach, CA, or Seattle, WA.
Excellent compensation and benefits. Details will be provided upon
request.
Please reply to: gcarlson@tqr.com
Posted Via Usenet.com Premium Usenet Newsgroup Services
----------------------------------------------------------
** SPEED ** RETENTION ** COMPLETION ** ANONYMITY **
----------------------------------------------------------
http://www.usenet.com
Article: 83383Ray Andraka wrote: > > > for many applications, using an external circuit such as a DAC or AD > DDS would be extreme overkill. One such overkill application would be > generation of a clock for a UART. > > One way to look at the output of the pahse accumulator I described > earlier is that it is a perfect squarewave resampled by your master > clock. If the master clock is not a neat multiple of your generated > frequency, then you'll have jitter of up to a clock cycle. You can > reduce the jitter by using a faster master clock (with modern FPGAs > there is no reason you couldn't quadruple your 40 MHz master clock and > run the DDS at 160 MHz). > > It all comes down to what are your requirements for the generated clock. > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 Another issue with the analog approach is that you can introduce more jitter into the system if your power supplies are not clean. This occurs when the threshold varies for creating a squarewave from the synthesized waveform. Voltage jitter in the threshold is converted to time jitter. The time jitter increases as the slew rate of the synthesized wave decreases. If your synthesized waveform is not produced by a D/A with a solid reference voltage, but rather the LVCMOS outputs of the FPGA through resistors, you'll get voltage jitter in the synthesized waveform as well due to noise on Vcco. Duty cycle is also not as easy to control in the analog approach, although you can deal with this by synthesizing a 2x frequency and dividing by two afterwards. When using the output of a DDS directly remember that the MSB of the phase counter is only 50% when the counter wraps at a power of 2. While this is the easiest way to make a DDS, there are applications where the count is not a power of 2 to allow a precise frequency step.Article: 83384
Hi, my question is only how to connect 2 dcms to the same clock input? regards, BenjaminArticle: 83385
I think you highly under estimate the average engineer. I believe this is because you only deal with people that can't get their designs to work. There are a lot more out there that never need help and you never hear from them. I would hate to think what engineers are designing logic that can't design an async FIFO(actually I know one, see bleow). My experience has shown that cut and paste does not provide the best performance, it may provide the best time to market as pointed out. When performance is more important than time to market you design everything yourself and highly optimize it. Apparently you only work with some below average junior engineers. We did have a senior senior engineer that couldn't design his own async FIFO, just goes to show there are below average people at all levels. That is the same type of mentality that would not hire a person with less than 5 years experience. I hope the people with that mentality end up with senior senior on their team. Peter Alfke wrote: > It's just not what you should entrust a junior engineer to do.Article: 83386
Hi, the problem was that coregen already created a ibufg for the clkin of the dcm... regards, BenjaminArticle: 83387
Alexander Korff wrote: > Hello, > > I use Quartus 4.2 SP1 WebEdition for my work. > The Hardware I built gets data from an external source with 40Mbit/s which > has an 16Bit multiplexed bus with an High/Low word and Strobe Pin to tell me > when data is valid and which is the high and wich is the low word. After > that I analyse the data an give it to an PC. > In the functional simulation everything works fine, but when I test this in > reality, the demux unit does not seem to work right, with Signal Tap II I > can see that the values comming out of this are something but not the values > which are feed into the FPGA. But then the analysis of the worng values > works fine, only the demux unit seems to be broken. > Are there any tools to simulate such a behaviour or can you recommend me > something to do ? Or can I change something in the timing options of Quartus > ? > > Thanks in advance. > > With best regards. > > Alex > If you are treating your IO pins as synchronous inputs, you need to assign timing constraints on the IOs and on your clock. Quartus does then a very good job at building correct delays to achieve timing coherence, but it cannot guess your constraints. You need to feed QII with accurate figures ! (garbage in garbage out) Then, static timing analysis (post P&R indeed) will confirm that everything is fine (Tsu, Th figures in the timing reports). STP II, being a synchronous logic analyzer, isn't the best tool for debugging timing issues. Timing sim can help, but you need to feed to with accurate timings indeed... back to square 1. Last : a mux is combinational. If you pile up logic (combinational layers before the first FlipFlops, it becomes a difficult case (with a potentially high difference between shortest & longest path). If your IOs are resynchronized asap (before the combinational logic), then timing issues become Fmax issues, which are trivial. Bert CuzeauArticle: 83388
I have a company modelsim dongle, which I have always assumed I can move around and use on any machine the dongle is currently plugged into. By definition I can only be using it in one place at a time ... Surely this is allowed ?? /MikeJ p.s. sorry I mailed you Hans, hit the wrong button :)Article: 83389
dan.nilsen@gmail.com (Dan Nilsen) wrote in message news:<50a67599.0504260257.6c83de8e@posting.google.com>... > Hi all! > > I have a problem that someone here might have the answer to. I have a > divider that takes inputs of 13 and 12 bits, and produces an output of > 12 bits. I have a component to strip away the redundant bits from the > divider, if the result of the division is, say an int value of 6, I > don't want to use all 12 bits. This circuit is a part of an MPEG-4 > device, a quantizer, so I want to compress as much as possible. I think you will find the step following quantization actually performs the compression. Quantization just prepares the values so they compress well (loads of zeroes). Something like the huffman and run length encoding algorithms will take the quantized values and express them concisely (compress them).Article: 83390
Well, Bryan, here is a test for a smart engineer: Assume a 1K-address deep FIFO ( data width does not matter) implemented in a dual-ported RAM. Design only the EMPTY-flag detect circuit that operates reliably at totally asynchronous write and read clock frequencies of >300 MHz, and show a test circuit that proves that this operation is reliable. (Hint: The Virtex-4 BlockRAM does this job at up to 500 MHz worst case). Peter AlfkeArticle: 83391
The relationship between the processor core and the OCM port needs to be an integer multiple. You cannot run the processor at 300 MHz and the OCM at 200MHz. Valid combinations are 300/100 (what you have up and running), 300/150, or 200/200. Don't forget to change PARAMETER C_DSCNTLVALUE to the correct value dependent on your clock settings. - Peter Joey wrote: > Hi everyone !! > > Could anybody tell me how to change the On-Chip Memory clock frequency. I > have the Power PC running at 300MHz and the OCM at 100MHz. What all I did to > double the OCM frequency was that I added the CLK2X port of the Digital > Clock Module (DCM) and connect it to the powerpc port BRAMDSOCMCLK and the > dsocm port DSOCM_Clk. Did I do any mistake, or is it something more that I > need to do here!! > > Well, I am using a Virtex II Pro device. I will add the relevant (changed) > part of the MHS file here: > > BEGIN dcm_module > PARAMETER INSTANCE = dcm_0 > PARAMETER HW_VER = 1.00.a > PARAMETER C_CLK0_BUF = TRUE > PARAMETER C_CLKFX_BUF = TRUE > PARAMETER C_CLKFX_DIVIDE = 1 > PARAMETER C_CLKFX_MULTIPLY = 3 > PARAMETER C_CLKIN_PERIOD = 10.000000 > PARAMETER C_CLK_FEEDBACK = 1X > PARAMETER C_EXT_RESET_HIGH = 1 > PORT CLKIN = dcm_clk_s > PORT CLK0 = sys_clk_s > PORT CLKFX = proc_clk_s > PORT CLKFB = sys_clk_s > PORT RST = net_gnd > PORT LOCKED = dcm_0_lock > PORT CLK2X = dcm_0_CLK2X ########## WHAT I ADDED!! END > > BEGIN dsocm_v10 > PARAMETER INSTANCE = docm > PARAMETER HW_VER = 2.00.a > PARAMETER C_DSCNTLVALUE = 0x85 > PORT DSOCM_Clk = dcm_0_CLK2X ### WHAT I CHANGED !! Before it was sys_clk_s > PORT sys_rst = sys_bus_reset > END > > BEGIN ppc405 > PARAMETER INSTANCE = ppc405_0 > PARAMETER HW_VER = 2.00.c > BUS_INTERFACE JTAGPPC = jtagppc_0_0 > BUS_INTERFACE DSOCM = docm > BUS_INTERFACE IPLB = plb > BUS_INTERFACE DPLB = plb > PORT PLBCLK = sys_clk_s > PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ > PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ > PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ > PORT RSTC405RESETCHIP = RSTC405RESETCHIP > PORT RSTC405RESETCORE = RSTC405RESETCORE > PORT RSTC405RESETSYS = RSTC405RESETSYS > PORT BRAMDSOCMCLK = dcm_0_CLK2X ##### WHAT I CHANGED !!Before it was > sys_clk_s > PORT CPMC405CLOCK = proc_clk_s > END > > Somebody please help !!! > > Regards, > Joe > > >Article: 83392
austin wrote: > The reason why we don't specify the cycle to cycle jitter any longer is > that it is hardly used by anyone anymore. > > Obviously, you have a a requirement. > > I may question how useful it is, but I won't (how does it know, or care > what the previous cycle timing was?). I'd be interested to know what you would consider to be useful in this case - the question that I really needed to answer, of course, is "will these two devices work together". The target DLL in question had a cycle-to-cycle jitter requirement (+-100 ps) that was smaller than the period jitter out of the DCM (particularly when input clock jitter was included). > The worst case cycle to cycle jitter (immediate cycle to the next one) > is the tap value. > > That is ~50ps for V2, and 35 for V2 Pro, and ~25ps for V4. > > Add linearly to that value the cycle to cycle jitter on the input clock > itself. > > So it the input is 20 ps, and the tap is 50 ps, then the total is 70 ps. Thank you Austin :) I appreciate the help - I've been trying to track down parameters for this interface for about two weeks now. JeremyArticle: 83393
Peter Soerensen wrote: > Hi all, > > I have just upgraded from the 6.3 version of the EDK to the 7.1 version. > For testing purposes i wanted to download the ML40x reference design onto > my ML 401 board. Unfortunately, the new EDK (the par tool) seems unable to > meet the timing constraints of the design. I dont know if this is a > problem with the EDK or ISE 7.1. If anyone out there has found a work > around or perhaps a solution I would love to hear about it. I have made no > changes to the design. > > Thanks peter I had similar problems initially. With ISE/EDK 6.3, I would increase the effort level for PAR to meet timing. With ISE/EDK 7.1, I found that adding the "-timing" option to MAP, andusing the default effort for PAR gives me about the same results as with 6.3sp2. I am just tracing a gcc incompatibility between 7.1 and 6.3 EDK (again). Anybody run in to that yet ? Best Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 83394
I'm not implementing RLE or Huffman in this project, but I'm aware that this is where much of the compression do take place. I will as I said, get lots of 0's and this can be compressed further. It might be the next step, but it is out of scope for my undergrad. engineering project. Thanks to all for their contributions anyway! DanArticle: 83395
Bryan - Maybe I'm jaded since I'm a consultant, but a lot of engineers just don't understand subtle issues like clock domain crossing. I've had to clean up so many bugs in this area that I can't count them all. Just when you think you've seen every way to send signals between clock domains incorrectly, a new way is invented. Same comments on signal integrity issues. Too many designers still think the world is only 1's and 0's. Reflections? Crosstalk? What are those? Sorry for the minor rant, but if Xilinx can make async fifos easier, maybe the average designer can make reliable designs. Yes, for custom case, you can may be able to create a smaller, more optimized design for a specific application, but for some engineers there effort may be better spent on the core of their design rather than re-creating a low level design block. Peter - thanks for all the great input you have in this newsgroup! John PArticle: 83396
On Thu, 28 Apr 2005 14:50:27 -0400, Ray Andraka wrote: > Mac wrote: > >>On Wed, 27 Apr 2005 17:18:03 -0700, kevin wrote: >> >> >> >>>"Hope this helps." >>> >>>It absolutely does! Thanks guys. >>> >>>Kevin >>> >>> >>> >> >>Keep in mind that the output of this type of DDS will NOT produce a 50% >>duty cycle (which is something you asked for), except at frequencies whose >>period is an even number of counts of the master clock (i.e., Fmaster/2N). >>For other frequencies, the maximum deviation from 50% duty cycle is one >>master clock. For example, if you tried to go output 75 MHz, with a master >>clock of 160 MHz, you would have a series of 125 ns periods with an >>occasional high or low stretched out by an extra 62.5 ns to keep the >>average frequency on track. >> >>Still, in your case, if you multiply the 40 MHz up to 160 MHz (go higher >>if you can) then implement a 32-bit phase accumulator, you should be close >>enough to 50% duty cycle and have small enough frequency steps to make >>most people happy. >> >>One way to reduce the jitter a little is to use a DAC type of approach, >>and a little bit of analog circuitry. You would take, say the 4 most >>significant bits of the phase output, and feed them to a phase to >>amplitude lookup table, then feed the output of the lookup table to a >>series of outputs with well-chosen resistor values. >> >>The resistor values would be, for example, 200, 400, 800 and 1600, Ohms. >>Of course, those resistor values don't exist. So you would pick the >>closest ones you can. These resistors would then all be connected >>together. This common node, then, would be your analog output. You could >>buffer it with an op-amp, and feed the op-amp to a 11.2MHz low pass >>filter, and you would have a pretty good 9MHz - 11.2 MHz sine wave, all >>things considered. The sine wave could then go to a comparator, and the >>comparator output would have much lower jitter than you would if you >>didn't use any analog techniques. This 9-11 MHz digital signal would be >>the x16 signal, and you would create the base signal by dividing it down. >> >>Total external parts: 4 resistors, 1 package with two or four op-amps, one >>comparator, and a few capacitors. If you used a quad op-amp, you could >>make a really good low-pass filter, and really cut the jitter down. >> >>If this all sounds like too much complication and bother, well, it >>probably is, but then again, maybe it will appeal to you (or the customer.) >> >>Of course, you could also use a DAC instead of the four resistors. You >>could even use an 8-bit DAC which would really help cut down the jitter, >>but would force you to implement an 8-bit output phase to amplitude >>converter. >> >>And the ultimate would be to put an Analog Devices DDS on the board. Then >>you would use the FPGA to generate the 160 MHz clock, program the DDS, and >>divide down the frequency output of the DDS by 16. That is what I would do. >> >>--Mac >> >> >> > for many applications, using an external circuit such as a DAC or AD > DDS would be extreme overkill. One such overkill application would be > generation of a clock for a UART. > The OP didn't say all that much about what he is trying to do. It is a pretty good surmise, since he is talking about generating two clocks, one of which is 16x the other, that he is generating clocks for a UART. On the other hand, these clocks are much faster than typical UART clocks for RS-232, so who knows? > One way to look at the output of the pahse accumulator I described > earlier is that it is a perfect squarewave resampled by your master > clock. If the master clock is not a neat multiple of your generated > frequency, then you'll have jitter of up to a clock cycle. I think that is exactly what I said, isn't it? Anyway, I am fairly familiar with how dds's and phase accumulators work, and have even incorporated a phase accumulator into an FPGA design, exactly as you outline. > You can > reduce the jitter by using a faster master clock (with modern FPGAs > there is no reason you couldn't quadruple your 40 MHz master clock and > run the DDS at 160 MHz). > Yeah, that is what I said. So your max deviation from 50% duty cycle is 6.25 ns. The OP needs to generate 700 KHz * 16 = 11.2 MHz, which is a period of around 90 ns. So a deviation of 6.25 ns is significant. That's what got me thinking about ways to reduce the jitter. > It all comes down to what are your requirements for the generated clock. Well, he said 50% duty cycle. If you have a low of 7 clock periods followed by a high of 8 clock periods (or vice-versa), I wouldn't exactly call that a 50% duty cycle. --MacArticle: 83397
On Thu, 28 Apr 2005 13:24:29 -0700, Gabor wrote: > > Ray Andraka wrote: > >> > >> for many applications, using an external circuit such as a DAC or AD > >> DDS would be extreme overkill. One such overkill application would > be >> generation of a clock for a UART. >> >> One way to look at the output of the pahse accumulator I described >> earlier is that it is a perfect squarewave resampled by your master >> clock. If the master clock is not a neat multiple of your generated >> frequency, then you'll have jitter of up to a clock cycle. You can >> reduce the jitter by using a faster master clock (with modern FPGAs >> there is no reason you couldn't quadruple your 40 MHz master clock > and >> run the DDS at 160 MHz). >> >> It all comes down to what are your requirements for the generated > clock. >> >> -- >> --Ray Andraka, P.E. >> President, the Andraka Consulting Group, Inc. >> 401/884-7930 Fax 401/884-7950 >> email ray@andraka.com >> http://www.andraka.com >> >> "They that give up essential liberty to obtain a little >> temporary safety deserve neither liberty nor safety." >> -Benjamin Franklin, 1759 > > Another issue with the analog approach is that you can introduce more > jitter into the system if your power supplies are not clean. This > occurs when the threshold varies for creating a squarewave from the > synthesized waveform. Voltage jitter in the threshold is converted > to time jitter. You did read the part where I said I would low-pass filter the output, right? > The time jitter increases as the slew rate of the > synthesized wave decreases. If your synthesized waveform is not > produced by a D/A with a solid reference voltage, but rather the > LVCMOS outputs of the FPGA through resistors, you'll get voltage > jitter in the synthesized waveform as well due to noise on Vcco. > I concede that this is all true. > Duty cycle is also not as easy to control in the analog approach, > although you can deal with this by synthesizing a 2x frequency and > dividing by two afterwards. When using the output of a DDS directly > remember that the MSB of the phase counter is only 50% when the > counter wraps at a power of 2. While this is the easiest way to > make a DDS, there are applications where the count is not a power > of 2 to allow a precise frequency step. I'm not sure I'm really following you here. The way a complete DDS works is that there is a phase accumulator, followed by a phase to amplitude converter (not sure if that is the proper name for it), followed by a DAC. Which would have to be followed by a low-pass filter. The phase accumulator, which has N bits, is incremented by a frequency tuning word (FTW) every clock cycle. I think what you are saying is that if and only if the FTW is a power of 2, the nominal duty cycle is exactly 50%. If so, I think I agree with you. I think you are also pointing out that a DDS can be tuned to any frequency from DC to Fmaster/2, and the frequency step size is Fmaster/2^N. If so I also agree with that. Anyway, I'm getting tired of this. I'm sure the OP has enough ideas to get going. I think if I have accomplished anything it is just muddying the waters. ;-) --MacArticle: 83398
Dear Gurus,
I've few concerns from the given function.
1. Do I necessary have to re-implement the data-type from float/double
to integers? I found it's difficult to re-scale the coefficients into
integers for this particular polynomial, since the range is fall
between 35333307.73 and 0.014726741 (to keep the precision at least 7
decimal places), and the integer for my machine can only support
4bytes. How will the typical designer do to overcome this problem?
2. I've found several 3rd party tools that particularly focus on this
field of application, e.g. Starbridge Inc. Viva, Mitrion-C, Celoxica-C,
ImpulseC...etc. Do they really can optimize the software design into
hardware design automatically without the tedious conversion? Or
alternatively, Matlab combines with Xilinx's system generator,
Accelchip, Xilinx core_gen (free)...etc. Which of them is the most
cost-effective for my case? Kindest thanks for your feedback!
Any help will be very appreciate!
// x is fall within a range of 0.0 to 10.0
float j1(float x)
{
float ax,z;
double xx,y,ans,ans1,ans2;
if ((ax=(float)fabs(x)) < 8.0) {
y=x*x;
ans1=x*(35333307.73+y*(-3855009.392+y*(118357.8384
+y*(-1451.470429+y*(7.668204395+y*(-0.014726741))))));
ans2=70666615.43+y*(1123308.192+y*(9073.879268
+y*(48.55831735+y*(0.184081611+y*4.8828125e-4))));
ans=ans1/ans2;
} else {
z=(float)8.0/ax;
y=z*z;
xx=ax-2.356194491;
ans1=1.0+y*(0.183105e-2+y*(-0.3516396496e-4
+y*(0.2457520174e-5+y*(-0.240337019e-6))));
ans2=0.04687499995+y*(-0.2002690873e-3
+y*(0.8449199096e-5+y*(-0.88228987e-6
+y*0.105787412e-6)));
ans=sqrt(0.636619772/ax)*(cos(xx)*ans1-z*sin(xx)*ans2);
if (x < 0.0) {
ans = -ans;
}
}
return (float)ans;
}
best regards,
Stanley
Article: 83399In article <d4rbk4087a@enews3.newsguy.com>, Phil Tomson <ptkwt@aracnet.com> wrote: >In article <d4r6o402p2@enews3.newsguy.com>, >Phil Tomson <ptkwt@aracnet.com> wrote: >>FYI: >>I found that it was necessary to unzip the self-extracting exe file for >>webpack 7.1 and then run 'wine setup.exe'. If I tried to run >>'wine WebPACK_71_fcfull_i.exe' wine would report an error about the exe >>not being a Win32 executable. So first run: >>'unzip WebPACK_71_fcfull_i.exe' and then run 'wine setup.exe'. (thanks >>to Uwe Bonnes for pointing this out) >> > >It seemed to install OK, but when I try to create a new project I get a >dialog box that comes up and says: >"no device data files have been found in this >installation, please verify that the software is installed properly" > >If I click OK a couple of times it lets me continue to the project setup >wizard where you enter the project name and >location. There is a box which asks you to select the type of >top-level module for the project there as well, but the pulldown menu >is empty. When I click 'next' nothing happens... probably because type >of top-level module isn't being set. Has anyone seen this? > >I tried both 6.3 and 7.1 and got similar results. I'm running >wine --version 20050310 I tried wine 20041019 and it seems to be working better. PHil
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z