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Messages from 69350

Article: 69350
Subject: Re: Mutiple Quartus Instances?
From: "Kenneth Land" <kland1@neuralog1.com1>
Date: Fri, 7 May 2004 12:39:16 -0500
Links: << >>  << T >>  << A >>

"Subroto Datta" <sdatta@altera.com> wrote in message
news:AbMmc.496$jd.228@newssvr33.news.prodigy.com...
>
> "Kenneth Land" <kland1@neuralog1.com1> wrote in message
> news:109kls5eqph5vcc@news.supernews.com...
> > Anyone know if there are any gotcha's with working with multiple Quartus
> (II
> > v. 4) projects on the same computer?
> >
>
> Hi Ken,
>
>     Based on the Quartus architecture you should not:
>
> 1. Open the SAME project in multiple Quartus instances, i.e. each Quartus
> instance should work on a different project.
>
> 2. Do not open a project from the UI and then run the command line
compiler
> executables from a DOS prompt/command shell (quartus_map, quartus_fit,
> quartus_tan, quartus_asm ...) on the same project. Use the UI or the
command
> line exclusively at any point in your design flow. You can switch between
> the two as needed.
>
> 3. Don't open and/or close more than one instance of Quartus at exactly
the
> SAME time. Basically, if one instance of Quartus is trying to close down,
it
> is in the process of writing stuff to the registry. Then during that time,
> another instance of Quartus just starting up may be trying to read that
data
> whcih may not be correct. Therefore if you initiate a closing of a Quartus
> instance let it close fully before you open another one.
>
> Apart from these you are ready to go. Hope this helps.
>
> - Subroto Datta
> Altera Corp.
>
>

Thanks Subroto,

With 10 min. compile times I can ping pong between two projects and stay
productive.  I've been doing it for some time, but

Quartus is an awesome tool and I really want to learn more about it.  The
the Signal Tap II and Simulation modules are fascinating.   Takes so much
time and effort to learn the quirks though.

Ken



Article: 69351
Subject: Re: Virtex2 (500) DCM Frequency Synthesize
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 07 May 2004 11:20:01 -0700
Links: << >>  << T >>  << A >>
I would use two independent DCMs:
first one multiplies by 27 and divides by 10, generates 54 MHz
second one multiplies by 27 and divides by 20, generates 27 MHz

You can of course also generate 27 MHz by flip-flop-dividing the 54 MHz.

That gets you out of the cascading dilemma, when the output jitter is more
than the input to a DCM tolerated.
Always try to avoid cascading DCMs!
Peter Alfke, Xilinx Applications

> From: furia1024@wp.pl (Jerzy)
> Organization: http://groups.google.com
> Newsgroups: comp.arch.fpga
> Date: 7 May 2004 07:49:57 -0700
> Subject: Virtex2 (500) DCM Frequency Synthesize
> 
> Hello
> I've got following problem:
> I need 27MHz and 54MHz clocks, input freq. is 20MHz.
> Till today I used DCM FS 27/20 next to DLL and DLL*2.
> Theoreticly it should works OK, but doesn't. From time to time after
> reboot or after clok stop, it works strange and completly bad. Today
> I've read about jitter on output of DCM's CLKFX, I check on "Virtex-II
> CLKFX Jitter Calculator" that in this conditions I have over 2 ns
> jitter on CLKFX output, which is to big for DLL input CLKIN.
> So I try to do this way:
> DCM FS 27/5 - I have 108MHz next to DLL/4 and DLL*2
> The jitter on CLKFX should be below 1ns and now it must work but
> doesn't.
> What should I check else?
> Please help me, I lose my hair :>
> 
> Best regards
> Jerzy Gbur


Article: 69352
Subject: Re: How to drive record fields from procedure AND testbench?
From: tom1@launchbird.com (Tom Hawkins)
Date: 7 May 2004 12:31:08 -0700
Links: << >>  << T >>  << A >>
petersommerfeld@hotmail.com (Peter Sommerfeld) wrote in message news:<5c4d983.0405070615.9481693@posting.google.com>...
> Hi Jim,
> 
> Yes I would love to participate in the VHDL-200X effort. It's nice to
> see it's open to the non-members. Is there a target release date for
> VHDL-200X?
> 
> This problem of the fields of a record appearing to be resolved as a
> group, and not individually, is particularly vexing to me. Hopefully I
> won't have to deal with it in the next VHDL version.
> 
> -- Pete

Pete, I'm sure you're aware that Confluence does not have this
limitation:

  component some_comp *gaggle with local_source external_reference is
    gaggle.from_here <- local_source
    gaggle.from_somewhere_else -> external_reference
  end

And in the second thread that Mike referenced, the author mentioned
partial function applications.  As a functional programming language,
Confluence has a few forms of partial functions:

  system = {my_component _ _ _}

This allows you to instantiate a component with the ports unconnected,
then pass around the resulting system to be wired up later.

-Tom


> > >>   gaggle.DSPaddr    <= DSPaddr;
> > >>   gaggle.DSPdata_in <= DSPdata;
> > >>-- . . . (rest of INs go here)
> > >>-- then OUTs:
> > >>            nDHOLD  <= gaggle.nDRDY;
> > >>            nDRDY   <= gaggle.nDRDY;
> > >>            DSPdata <= gaggle.DSPdata_out when output_enabled
> > >>                                          else (DSPdata'range => 'Z');

> 
> 
> > Peter,
> > As a PS to my other post, to date I have found
> > that if I want to work with a single record,
> > I have been limited to std_logic family.
> > 
> > I have tried tinkering with integers and resolution
> > functions, but have had problems with resolving a value
> > to drive when the record field is not to be driven.
> > It seems that the resolution function is called at the
> > block level and there currently no way I could find to
> > work around this.
> > 
> > This is a topic we are kicking around in the VHDL-200X
> > effort.  I had wished for it to be part of the fast track
> > effort and I made a proposal, but it is not clear even to
> > me that the proposal is the best long term solution, so I
> > don't want to push it.  My preference is to see what comes
> > up when we give more time and consideration to the problem.
> > 
> > For more on the vhdl-200x effort, see:
> >      http://www.eda.org/vhdl-200x
> > 
> > IEEE standards are open to public participation.
> > 
> > Best Regards,
> > Jim
> > 
> > 
> > > Hi Mike,
> > > 
> > > Yes I found my problem, and it was unfortunately in a part of my
> > > record that I didn't post. In my record, I had a field that was of the
> > > physical type time which I was using inside my procedures for certain
> > > delays. ie:
> > > 
> > >   type rec is record
> > >     ...
> > >     clock_period : time;
> > >     ...
> > >   end record;
> > > 
> > > So while I was assuming a signal-driving issue to be the problem, it
> > > was this field (which is still bizarre, because I set this field only
> > > once and never write it again, therefore, I would have thought, it
> > > could not be a problem). Anyways, I replaced this field with a clock
> > > signal which makes more sense now anyways and everything works great,
> > > and thanks to yours and Jim's replies, I understand what's going on
> > > much better too. I had better post the whole thing the next time I
> > > have a problem like this.
> > > 
> > > -- Pete
> > > 
> > > 
> > >>Peter Sommerfeld wrote:
> > >>
> > >>
> > >>>Thanks for the reply. I must be on the right track, because it looks
> > >>>like I have been doing what you suggested in
> > >>>http://groups.google.com/groups?q=gaggle.DSPaddr. However, the InitBus
> > >>>call causes compile errors in my design. 
> > >>
> > >>You have stumbled onto the procedure scope problem.
> > >>Re-read that thread and see the lines I added
> > >>to my example architecture below.
> > >>
> > >>     -- Mike Treseler
> > >>     
> > >>     
> > >>------------------------------------------------------------
> > >>architecture synth of signal_structure is
> > >>   -- note, I changed your type to data in and out signals
> > >>   
> > >>   type DSPIF_type is
> > >>      record
> > >>         DSPaddr     : std_logic_vector(23 downto 0);
> > >>         DSPdata_in  : std_logic_vector(31 downto 0);
> > >>         DSPdata_out : std_logic_vector(31 downto 0);
> > >>         nDHOLD      : std_logic;
> > >>         nDHOLDA     : std_logic;
> > >>         nDPAGE      : std_logic_vector(3 downto 0);
> > >>         nDSTRB      : std_logic;
> > >>         nDBE        : std_logic_vector(3 downto 0);
> > >>         nDOE        : std_logic;
> > >>         nDWE        : std_logic;
> > >>         nDRDY       : std_logic;
> > >>      end record;
> > >>
> > >>   signal gaggle         : DSPIF_type;
> > >>   signal output_enabled : boolean;
> > >>-------------------------------------------------------------------------------
> > >>   -- Added proc example in scope
> > >>   procedure InitBus( signal gaggle: inout DSPIF_type )
> > >>   is begin end InitBus;
> > >>-------------------------------------------------------------------------------   
> > >>begin
> > >>   -- wire up signal structure to pins
> > >>   gaggle.DSPaddr    <= DSPaddr;
> > >>   gaggle.DSPdata_in <= DSPdata;
> > >>-- . . . (rest of INs go here)
> > >>-- then OUTs:
> > >>            nDHOLD  <= gaggle.nDRDY;
> > >>            nDRDY   <= gaggle.nDRDY;
> > >>            DSPdata <= gaggle.DSPdata_out when output_enabled
> > >>                                          else (DSPdata'range => 'Z');
> > >>
> > >>-- processes using the gaggle signals go here
> > >>
> > >>end architecture synth;
> > >>   
> > >>
> > >>   -- Mike Treseler
> > 
> > 
> > -- 
> > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > Jim Lewis
> > Director of Training             mailto:Jim@SynthWorks.com
> > SynthWorks Design Inc.           http://www.SynthWorks.com
> > 1-503-590-4787
> > 
> > Expert VHDL Training for Hardware Design and Verification
> > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Article: 69353
Subject: Muxes : 64X1
From: "Gary Olson" <gary_olson@littleoptics.com>
Date: Fri, 7 May 2004 12:32:45 -0700
Links: << >>  << T >>  << A >>
Question I have is I need a 42X1 Mux 
Actually I am muxing 42 16 bit databusses. The Timing is critical 
because the 42 16 bit words are read by a microcontroller. I am 
wondering the best way to MUX theses signals. I could use a 64X1 
mux and syntesize out unused logic. 
Or I could use a 32X1, 16X1 with a 2X1 to merge the two muxed data paths. 

Does it make any difference at all what I do? Any other alternative approaches? 

Thank You, 
Gary Olson


Article: 69354
Subject: Re: Muxes : 64X1
From: "Gary Olson" <gary_olson@littleoptics.com>
Date: Fri, 7 May 2004 12:50:54 -0700
Links: << >>  << T >>  << A >>
I meant the timing is not critical because I am reading the Mux output 
with a Microcontroller.



Article: 69355
Subject: Re: Muxes : 64X1
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 7 May 2004 13:13:43 -0700
Links: << >>  << T >>  << A >>
Gary,
Ken Chapman of Xilinx wrote a TechXclusive about Multiplexers. It's worth a
read.
cheers, Syms.



Article: 69356
Subject: Re: Muxes : 64X1
From: "Gary Olson" <gary_olson@littleoptics.com>
Date: Fri, 7 May 2004 13:17:57 -0700
Links: << >>  << T >>  << A >>
Here is my VHDL 
library IEEE; 
use IEEE.STD_LOGIC_1164.all; 

entity MUX42 is 
port ( 
dIn_0 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_1 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_2 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_3 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_4 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_5 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_6 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_7 : in STD_LOGIC_VECTOR (15 downto 0); 
dIn_8 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_9 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_10 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_11 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_12 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_13 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_14 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_15 : in STD_LOGIC_VECTOR (15 downto 0); 
dIn_16 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_17 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_18 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_19 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_20 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_21 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_22 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_23 : in STD_LOGIC_VECTOR (15 downto 0); 
dIn_24 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_25 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_26 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_27 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_28 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_29 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_30 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_31 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_32 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_33 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_34 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_35 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_36 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_37 : in STD_LOGIC_VECTOR (15 downto 0); 
dIn_38 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_39 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_40 : in STD_LOGIC_VECTOR (15 downto 0); 
      dIn_41 : in STD_LOGIC_VECTOR (15 downto 0); 
sel_0 : in STD_LOGIC; -- select mux input 
      sel_1 : in STD_LOGIC; -- select mux input 
sel_2 : in STD_LOGIC; -- select mux input 
      sel_3 : in STD_LOGIC; -- select mux input 
sel_4 : in STD_LOGIC; -- select mux input 
      sel_5 : in STD_LOGIC; -- select mux input 
      dOut : out STD_LOGIC_VECTOR (15 downto 0) 
    ); 
end MUX42; 

--}} End of automatically maintained section 

architecture MUX42 of MUX42 is 
      signal adr: std_logic_vector(5 downto 0); 
begin 
    adr <= sel_5 & sel_4 & sel_3 & sel_2 & sel_1 & sel_0; 

with adr select dOut<= 
      dIn_0 when "000000", 
      dIn_1 when "000001", 
      dIn_2 when "000010", 
dIn_3 when "000011", 
dIn_4 when "000100", 
      dIn_5 when "000101", 
      dIn_6 when "000110", 
dIn_7 when "000111", 
dIn_8 when "001000", 
      dIn_9 when "001001", 
      dIn_10 when "001010", 
dIn_11 when "001011", 
dIn_12 when "001100", 
      dIn_13 when "001101", 
      dIn_14 when "001110", 
dIn_15 when "001111", 
dIn_16 when "010000", 
      dIn_17 when "010001", 
      dIn_18 when "010010", 
dIn_19 when "010011", 
dIn_20 when "010100", 
      dIn_21 when "010101", 
      dIn_22 when "010110", 
dIn_23 when "010111", 
dIn_24 when "011000", 
      dIn_25 when "011001", 
      dIn_26 when "011010", 
dIn_27 when "011011", 
dIn_28 when "011100", 
      dIn_29 when "011101", 
      dIn_30 when "011110", 
dIn_31 when "011111", 
dIn_32 when "100000", 
      dIn_33 when "100001", 
      dIn_34 when "100010", 
dIn_35 when "100011", 
dIn_36 when "100100", 
      dIn_37 when "100101", 
      dIn_38 when "100110", 
dIn_39 when "100111", 
dIn_40 when "101000", 
      dIn_41 when 




Article: 69357
Subject: Re: Error while simulation with XILINX DCM
From: "Jim Wu" <NOSPAM@NOSPAM.com>
Date: Fri, 07 May 2004 22:33:21 GMT
Links: << >>  << T >>  << A >>
> in order to verify the functionality of XILINX DCM, I have generated a
> dcm.vhd file with the ISE 6.2 architecture wizard. The dcm module is
> embedded into a simple top-level file that only connects the testbench
> signals (in-clock and reset (=0) to the DCM-module. The DCM reset
> signal is always set to '0'.
>

It would help if you can post the testbench code as well. Sometimes the
generation of the inputs to the DCM may affect the behavior simulation
model. I've seen that DCM model does not work if the input clock starts at 1
at time 0. e.g

process
clock_in <= '1';
wait for 10ns;
clock_in <= '0';
wait for 10ns;
end process;

HTH,
Jim
jimwu88NOOOSPAM@yahoo.com
http://www.geocities.com/jimwu88/chips




Article: 69358
Subject: Re: ChipScope Core Generator Flow
From: "Jim Wu" <NOSPAM@NOSPAM.com>
Date: Fri, 07 May 2004 22:41:02 GMT
Links: << >>  << T >>  << A >>
> Hello,
>
> I want to use the Xilinx Chipscope. As described I generated the
> controller and logic analyzer using the ChipScope Core Generator and
> than instantiated the icon and ila instances in my VHDL and synthesised
> it using Precision RTL. But the generated edif file does not contain any
> cell icon and ila. Therefore Chipscpoe logic isn't implemented and I
> can't use it.
>
> What is my fault?
>

Could be that Precision RTL optimizes out the icon and ila instantiations.
I've never used Precision RTL, but it should have a way (most synthesis
tools do)  to not optimize out certain blocks.

HTH,
Jim
jimwu88NOOOSPAM@yahoo.com
http://www.geocities.com/jimwu88/chips




Article: 69359
Subject: SignalProbe in Quartus...
From: "Kenneth Land" <kland1@neuralog1.com1>
Date: Fri, 7 May 2004 17:47:36 -0500
Links: << >>  << T >>  << A >>
I'm trying to use SignalProbe to speed up the debugging process.

I've got a number of testpoint pins that I've been assigning and reassigning
signals to in order to see the signals on an external logic analyzer.

This works very well except the 10 min. compile just to change test signals
is getting old.  SignalProbe seems to be the solution to my problem but I'm
not able to get it going correctly.

It seems that most of the signals I want to probe are intermediate named
values that connect one block of logic to another.  Anyway, these signals
don't appear in the signalprobe node finder.

I can type them into the assignment editor as the SignalProbe source, but
the SignalProbe Compile warns that the Source "Could not be found, or is an
unsupported type"

Does SignalProbe not support internal signals?  Do I need to do something to
make a signal a supported type?

Thanks,
Ken




Article: 69360
Subject: Re: ChipScope Core Generator Flow
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 7 May 2004 18:07:18 -0700
Links: << >>  << T >>  << A >>
Very true, for example you need this with Synplify

  attribute syn_black_box : boolean;
  attribute syn_black_box of icon : component is TRUE;
  attribute syn_noprune : boolean;
  attribute syn_noprune of icon : component is TRUE;

HTH, Syms.

"Jim Wu" <NOSPAM@NOSPAM.com> wrote in message
news:2gUmc.17549$vz5.3774@nwrdny01.gnilink.net...

> Could be that Precision RTL optimizes out the icon and ila instantiations.
> I've never used Precision RTL, but it should have a way (most synthesis
> tools do)  to not optimize out certain blocks.
>
>



Article: 69361
Subject: OPB IPIF user logic
From: ramntn@yahoo.com (ram)
Date: 7 May 2004 18:51:31 -0700
Links: << >>  << T >>  << A >>
Hi Group,
 I am designing a simple core to add to the opb bus using opb_ssp0
package.
The core has 2 register, and I am tryin to write a value and read from
them.
But when I do that its giving me an output thats wierd, whenever I
write a even number to the register I read back an odd number ( one
greater then the even number )but for odd numbers its ok.

have a look at the following code example and the results.
/* write to register */
XIo_Out32( (XIo_Address)(XPAR_MY_COUNTER_BASEADDR + REG_A_OFFSET) ,
0x32 )
/*Read from register */
reg_a = XIo_In32( (XIo_Address)XPAR_MY_COUNTER_BASEADDR + REG_A_OFFSET
);

/* Display result */
XUartLite_SendByte( XPAR_RS232_BASEADDR, reg_a );

In the above example the result is 0x33.

Does anybody have the same problem ,i will appreciate if somebody
could help me to point out the mistake i am doing.

Thanx for your time and support
Ram

Article: 69362
Subject: Re: SignalProbe in Quartus...
From: "Gary Pace" <xxx@yyy.com>
Date: Sat, 08 May 2004 02:16:57 GMT
Links: << >>  << T >>  << A >>
The synthesis process often removes internal nodes as the functionality is
analysed and reduced to the FPGA target architecture.

If you arrange your design so that you are only trying to probe register
contents (i.e. the Q's of latches etc), you can prevent the synthesis from
removing these by right clicking the latch and setting the appropriate
option to OFF (can't remember which one, but it's there).

If you can't find it the assignment editor, there is a parameter you can
define for a synbol (megafunction or your own) to prevent register merging.

I've used signal probe quite a lot, it's pretty useful but it does use a lot
of embedded memory if you try to assign plenty of nodes to it. Otherwise,
you'll still need to re-compile to change which signals you're probing


"Kenneth Land" <kland1@neuralog1.com1> wrote in message
news:109o4gg8872s529@news.supernews.com...
> I'm trying to use SignalProbe to speed up the debugging process.
>
> I've got a number of testpoint pins that I've been assigning and
reassigning
> signals to in order to see the signals on an external logic analyzer.
>
> This works very well except the 10 min. compile just to change test
signals
> is getting old.  SignalProbe seems to be the solution to my problem but
I'm
> not able to get it going correctly.
>
> It seems that most of the signals I want to probe are intermediate named
> values that connect one block of logic to another.  Anyway, these signals
> don't appear in the signalprobe node finder.
>
> I can type them into the assignment editor as the SignalProbe source, but
> the SignalProbe Compile warns that the Source "Could not be found, or is
an
> unsupported type"
>
> Does SignalProbe not support internal signals?  Do I need to do something
to
> make a signal a supported type?
>
> Thanks,
> Ken
>
>
>



Article: 69363
Subject: Re: How to remove an unintended Right-click menu?
From: "Jim Carlock" <anonymous@127.0.0.1>
Date: Fri, 7 May 2004 23:51:42 -0400
Links: << >>  << T >>  << A >>
Hit the escape key?

-- 
Jim Carlock
http://www.microcosmotalk.com/
Post replies to the newsgroup.


"Adlene" <Adlene3352@hotmail.com> wrote in message
news:c7hbeh$bqt$1@reader01.singnet.com.sg...
Hi, there:

When I right click on a text file, the Convert to Palm e-Book and
Convert to Palm PDB comes out...I have removed the application
for Palm e-Book Builder and restarted PC but these two menus won't
go away...

How may I remove these two menus manually?

Best Regards,
Kelvin




Article: 69364
Subject: Re: How to remove an unintended Right-click menu?
From: "Kelly" <kelly@mvps.org>
Date: Sat, 8 May 2004 02:05:30 -0500
Links: << >>  << T >>  << A >>
Hi Kelvin,

It depends on where in the right click menu.  They can be removed from here, 
for starters:

Go to Start/Run/Regedit and navigate to:

HKEY_CLASSES_ROOT\*\OpenWithList
HKEY_CLASSES_ROOT\*\shellex\ContextMenuHandlers
HKEY_CLASSES_ROOT\Directory\Background
HKEY_CLASSES_ROOT\Directory\shell
HKEY_CLASSES_ROOT\Directory\shellex\ContextMenuHandlers
HKEY_CLASSES_ROOT\Drive\shell
HKEY_CLASSES_ROOT\Drive\shellex\ContextMenuHandlers
HKEY_CLASSES_ROOT\Folder\shell
HKEY_CLASSES_ROOT\Folder\shellex\ContextMenuHandlers

-- 
All the Best,
Kelly

Microsoft-MVP Windows® XP
2004 Windows MVP "Winny" Award

Troubleshooting Windows XP
http://www.kellys-korner-xp.com

Taskbar Repair Tool Plus!
http://www.kellys-korner-xp.com/taskbarplus!.htm


"Adlene" <Adlene3352@hotmail.com> wrote in message 
news:c7hbeh$bqt$1@reader01.singnet.com.sg...
Hi, there:

When I right click on a text file, the Convert to Palm e-Book and
Convert to Palm PDB comes out...I have removed the application
for Palm e-Book Builder and restarted PC but these two menus won't
go away...

How may I remove these two menus manually?

Best Regards,
Kelvin




Article: 69365
Subject: Re: Which board to buy? Status of open source tools?
From: "Alex Gibson" <me@privacy.net>
Date: Sat, 8 May 2004 19:49:38 +1000
Links: << >>  << T >>  << A >>

"Joel Hardy" <deeng_temp@yahoo.com> wrote in message
news:91268129.0405062217.35c0b0cd@posting.google.com...
> Howdy all,
>
> I'm looking to get an FPGA development board sometime soon.  When I
> was in college, I played with what was probably the Xess XSB-300E (fun
> stuff: we made a  PCMCIA interface and plugged it into an iPaq... but
> that's another story).  That's WAY outside of my price range (<
> $200US), but the XSA-50 doesn't look too bad.  Any comments on that
> one?  Also, I found this
> (www.nuhorizons.com/products/xilinx/spartan3/development-board.html),
> which looks considerably better to me, especially since my main
> prospective project would benefit from a large amount of fast RAM.
> Any advice?  Is there anything else in the sub-$200 I should look at?
>
> Also, what's the status of open source tools?  (I like to tinker on
> the software end of things, too, and I have a bad case of PowerBook
> envy, and I haven't seen any software available other than x86 and
> big-iron UNIX).  Can they go from VHDL/Verilog all the way to
> downloading the file to the chip?  I see that compilation (Icarus
> verilog) and downloading (found it in this group's FAQ) work, but what
> about place and route?  Icarus' docs say it's a no-go for this; is
> there anything else, or must I use the Xilinx tools?  (I guess I have
> a Xilinx bias -- it's all I've used, and I don't see much else for
> cheap development boards.)
>
> Thanks for the help!
> - Joel Hardy

have a browse of http://www.digilentinc.com/index.html

xilinx webpack is free  www.xilinx.com/webpack

same with Quartus from altera
parallax were selling a few boards
also altera was selling some "student" boards
a while back

Alex



Article: 69366
Subject: Re: Which board to buy? Status of open source tools?
From: "Alex Gibson" <me@privacy.net>
Date: Sat, 8 May 2004 20:06:11 +1000
Links: << >>  << T >>  << A >>

"Alex Gibson" <me@privacy.net> wrote in message
news:2g3pdhF3vva3U1@uni-berlin.de...
>
> have a browse of http://www.digilentinc.com/index.html
>
> xilinx webpack is free  www.xilinx.com/webpack
>
> same with Quartus from altera
> parallax were selling a few boards
> also altera was selling some "student" boards
> a while back
>
> Alex


here is the link for the altera uni program board
http://www.altera.com/education/univ/kits/unv-kits.html



Article: 69367
Subject: downloading a non-volitle design (xilinx)
From: "GL" <gl@hotmail.com>
Date: Sat, 08 May 2004 10:23:55 GMT
Links: << >>  << T >>  << A >>
How do you download your design (in VHDL) to a Xilinx board and make it
non-volitle, using the Xilinx ISE webpack software?

Here are the things I've been trying...not yet successful...

-generate PROM file
-start iMPACT
-choose Slave Serial Mode? (I'm confused here...which mode should I choose?)

If anyone could tell me the steps, I would really appreciate it.  My xilinx
board has a SPARTAN FPGA chip and flash memory.

Thanks!



Article: 69368
Subject: Re: Virtex2 (500) DCM Frequency Synthesize
From: Jerzy <furia1024@wp.pl>
Date: Sat, 08 May 2004 11:39:54 GMT
Links: << >>  << T >>  << A >>
First Thank All Of You, very much for answers

Peter Alfke wrote:

>I would use two independent DCMs:
>first one multiplies by 27 and divides by 10, generates 54 MHz
>second one multiplies by 27 and divides by 20, generates 27 MHz
>
>You can of course also generate 27 MHz by flip-flop-dividing the 54 MHz.
>
>That gets you out of the cascading dilemma, when the output jitter is more

Yes, I'll try that after weekend. It will be great that phase between
54MHz and 27MHz will be constans. Maybe dividing by flip-flop helps.
Another thing, that 54MHz must drive external ZBT SRAM, so I'd like to
use external feedback.
And how to do it without DCM?



Best regards
Jerzy Gbur



Article: 69369
Subject: Re: SignalProbe in Quartus...
From: "Subroto Datta" <sdatta@altera.com>
Date: Sat, 08 May 2004 13:00:23 GMT
Links: << >>  << T >>  << A >>
Hi Ken,

  To preserve a combinational node through synthesis, place and route, you
should do
one of the following:

a) If it is a BDF (schematic file) or TDF (AHDL file), feed the signal
that you are interested in observing into a LCELL primitive, and give
the LCELL primitive an interesting name, so that you can find it when
you choose the Post Compilation filter in the node finder. You should
feed the output of the LCELL to where the signal wof interes was
previously connected.

b) If you are using VHDL or Verilog, consider using the keep
pragma/keyword. Its usage is described in the online help. Search for
"keep". The Verilog help panel is shown below:

------------------- keep usage in
Verilog -----------------------------------
A Verilog HDL language directive that directs Analysis & Synthesis to
keep a particular wire intact. You can use this language directive to
keep a combinational logic node so you can observe the node during
simulation or with the SignalTap® II Logic Analyzer.

You cannot use this language directive for nodes that have no fan-out.

To use the keep language directive, you can specify the keep language
directive in a comment that is on the same line as the register you
want Analysis & Synthesis to preserve. In the comment, precede the
language directive with the synthesis keyword.

For example, in the following code, the comment
/* synthesis preserve */ directs Analysis & Synthesis to not minimize the
keep_wire
register:

wire keep_wire /* synthesis keep */;
----------------------------------------------------------------------------
---
You would search for keep_wire in the Node Finder, and you can make
assignments to it.

Additional information for preserving registers can be found in the chapter
on Synthesis (Volume 1, Section 3, Chapter 8)  of the Quartus II Handbook.
The URL is provided below:
http://www.altera.com/literature/hb/qts/qts_qii51008.pdf
See Table 1 for details on the synthesis options.

More information on SignalProbe and SignalTap, which are two complementary
debugging technologies can be found in the chapter on On Chip Debugging (
Volume 3, Section 4, Chapters 8 and 9) of the Quartus II Handbook. The URL's
are provided below:
For SignalProbe: http://www.altera.com/literature/hb/qts/qts_qii53008.pdf
For SignalTap: http://www.altera.com/literature/hb/qts/qts_qii53009.pdf

If you are using SignalTap do read the piece on Incremental Routing, which
may help reduce some of your compile time. I believe Gary in his reply to
your post was referring to SignalTap not SignalProbe, since its is SignalTap
that uses the RAM blocks in the device.

Hope this helps.

- Subroto Datta
Altera Corp.


----------------------------------------------------------------------------
----



Article: 69370
Subject: Re: Which board to buy? Status of open source tools?
From: "Martin Schoeberl" <martin.schoeberl@chello.at>
Date: Sat, 08 May 2004 16:39:19 GMT
Links: << >>  << T >>  << A >>
"Alex Gibson" <me@privacy.net> schrieb im Newsbeitrag
news:2g3rpkF404s8U1@uni-berlin.de...
>
> "Alex Gibson" <me@privacy.net> wrote in message
> news:2g3pdhF3vva3U1@uni-berlin.de...
> >
> > have a browse of http://www.digilentinc.com/index.html
> >
> > xilinx webpack is free  www.xilinx.com/webpack
> >
> > same with Quartus from altera
> > parallax were selling a few boards
> > also altera was selling some "student" boards
> > a while back
> >
> > Alex
>
>
> here is the link for the altera uni program board
> http://www.altera.com/education/univ/kits/unv-kits.html
>
>
That board comes with a pretty 'old' (and 'small') FPGA.
A little bit above your $200 limit, but with a Cyclone EP1C6 or EP1C12
(Altera's new low cost devices) and 1 MB fast memory:
http://www.jopdesign.com/cyclone/index.jsp



Article: 69371
Subject: Director of Applications/FPGA
From: redhook4u@yahoo.com (LK Allen)
Date: 8 May 2004 10:15:51 -0700
Links: << >>  << T >>  << A >>
If you know someone that would be interested, please forward my email.
 Any help you can give me would be much appreciated.  This position is
located in Silicon Valley(near Cisco's campus).
 
 
 
I answered some common questions below the job description, so please
take a moment to read them.
 
Director of Applications

 

You have a successful track record supporting ASIC and FPGA customers
with knowledge in HDL coding, synthesis, and P&R.  You have expertise
at the device level in high-speed I/O, embedded memory, PLLs, and
multipliers.   At the board level you are knowledgeable about
reference designs, device configuration, board integration, and signal
integrity.  Work closely with the design engineering team to refine
product definition and ensure product usability.  Run HDL designs on
the design platform, identify issues, collaborate with the development
team and drive resolution.  Strong customer skills and contacts with
ability to demonstrate platforms and products, train customers,
understand their applications, and devise solutions during debug and
system bring-up.  You will author handbooks and application notes to
promote adoption of our advanced products.

 

Successful candidate will be a skilled communicator who establishes
credibility with engineers, managers, and architects at customer sites
and at conferences.

He or she will lead by example and build a world class team.

 

Qualifications: BS/MS EE + 10 years experience in FPGA and ASIC
design/applications. Extensive experience in FPGA design, PCB issues
and customer interaction is required. Knowledge of Communications,
Storage, or Industrial vertical markets is a plus.

 
 
- How much funding have we received?

- Is there a second round in the near future?  Has it been closed?

 

We closed on our first round in May 2003.  We met our milestones for
developing a business plan, developing our software/simulation
platform, and proving 2x better capabilities with customer designs.

 

We closed our second round in April 2004.  We have top-notch VCs  

Sequoia Capital, USVP, and Horizon with semiconductor savvy general
partners sitting on our board.

 

- Why this company?

 

Programmable logic is booming, taking over a bigger and bigger
proportion of the semiconductor market.  We have a breakthrough
architecture that allows programmable logic to do things that it has
never done before.
 
 
Regards,
LK Allen IV
landon@atssi.com
landon4216@earthlink.net

Article: 69372
Subject: Re: Muxes : 64X1
From: Ray Andraka <ray@andraka.com>
Date: Sat, 08 May 2004 21:50:21 -0400
Links: << >>  << T >>  << A >>
Depending on your design, you could put these in a BRAM and
then have the uP read the BRAM.  Works well for reading back
values written to registers by the uP that you want to be
able to read back, in which case you have both your register
and the BRAM where the BRAM acts as a shadow register who's
sole purpose is to provide readback data to the uP.  For
registers written by the FPGA, you can work the registers
like a shift register to write them into a BRAM, then have
the uP read the BRAM.  It gains you random access without
the muxes and wires.

Gary Olson wrote:

> Question I have is I need a 42X1 Mux
> Actually I am muxing 42 16 bit databusses. The Timing is
> critical
> because the 42 16 bit words are read by a microcontroller.
> I am wondering the best way to MUX theses signals. I could
> use a 64X1 mux and syntesize out unused logic.
>
> Or I could use a 32X1, 16X1 with a 2X1 to merge the two
> muxed data paths.
>
> Does it make any difference at all what I do? Any other
> alternative approaches?
>
> Thank You,
> Gary Olson

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin
Franklin, 1759



Article: 69373
Subject: is it possible to design usb only with fpga?
From: "rat" <rattt@col.edu.cn>
Date: Sun, 9 May 2004 14:43:56 +0800
Links: << >>  << T >>  << A >>
Hi,
  Is it possible to make a USB 1.1 interface only with FPGA chip, I mean,
without addtional transceiver chip?
  Thanks a lot!

Regards,
rat



Article: 69374
Subject: Re: Easypath question (was "Hard-tocopy" rant)
From: acm <moleson@NOSPAM.yahoo.com.NOSPAM>
Date: Sun, 09 May 2004 09:52:48 -0400
Links: << >>  << T >>  << A >>
Easypath = EasyScrap...

Hey, buy our excess scrapped inventory!!!!




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