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I need to assign signals to the Spartan 150 in a fg256 package before the design is complete. I would like documention that list the pad to pin connection for the above mentioned part. That way I can assign inputs on the left with lsb on the bottoms. Would anybody point me to that data, please. Thanks Jerry EnglishArticle: 29851
Peter Alfke wrote:
>
> I don't think that 3-stating the 63 unused rows is any help.
I'd agree.
> Just analyze the sneak paths in a 3 x 3 array with nine resistors.
> Pulse one row High, while the other two rows are 3-stated.
> Now look at all the paths that can drive current into the column that is being
> measured...
<snip>
> > >From Larry Doolittle:
> > > When I have worked with an array like this, it was important to tie
> > > each column to a virtual ground, otherwise the columns "talked" to
> > > each other. Also, if Manfred's resistors really can vary down to
> > > 1 Ohm, you need something other than a "low current nfet" to drive
> > > the rows.
> > > - Larry Doolittle <LRDoolittle@lbl.gov>
But I think Larry is correct, you can either GND, or virtual gnd, the
'off' columns,
and measure the current in the required ON node.
The driver does have variable load current, but the 'sneak' paths are
one-way, and
(nominally) do not inject back into the measurement node
( assumes 0mV errors on virtual grounds )
Virtual Gnd is probably a new concept to FPGA designers :-)
It is essentially a current node, rather than a voltage node, and is
commonly
seen at the -ve input of a Opamp.
--- Current ----->--VG-+------ Resistor ----+-- Vout
| |\ |
| | \ |
+----|- \ |
| \___________+
| /
GND ----------|+ /
| /
|/
In this circuit, point Vg is within the (offset voltage+gain error) of
GND,
so long as the Vout is in the linear region.
'1R to 1 Meg' sounds a bit like homework to me, and not a real world
sensor :-)
-jg
Article: 29852You can get that from the 'bank' information in the pinout tables. More detail can be had via fpga_editor. "Jerry English" <jenglish@wherenet.com> wrote in message news:ee6fe8f.-1@WebX.sUN8CHnE... > I need to assign signals to the > Spartan 150 in a fg256 package > before the design is complete. I > would like documention that list the > pad to pin connection for the above > mentioned part. That way I can assign inputs on the left with lsb on the bottoms. Would anybody point > me to that data, please. > > Thanks > Jerry EnglishArticle: 29853
"Peter Alfke" <peter.alfke@xilinx.com> wrote in message news:3AAE7A90.BFDEDA38@xilinx.com... > > Erik Widding wrote: > > > 3. There are a few limitations in the simplest solution, and further work > > is still necessary. > > The "few limitations" are that the concept inherently does not work. > Some "limitation"! > I guess I thought Peter's and Larry's comments about the deficiency in the circuit were self explanatory. If one were to take my initial and flawed concept, replace each of the 64 fets with 64 fets, one for each of the resistors in a row, with the gates controlled in the same manner, the problem is solved. Now we are at the point where a spice simulation would be in order to determine whether or not the solution would work to one's requirements. Another solution would be to add 4096 diodes. So the economics of the solution are in fact different, as one now needs 4096 nfets, not the original 64 that I suggested. When posting the follow up, I thought that one "skilled in the art" would realize that this was the "over simplification" to which I referred. A suitable low current less than 10 ohm fet can be had for $0.05 each, plus the cost of placement. You will also need to add a 3.3v to 10v translator to drive the fets, one for each row. The second limitation is the "precision resistor" in the columns. To get a linear response, one would want to replace this with a current source, which basically adds an opamp in parallel with said resistor. The third limitation, is that if one is really measuring from 1K to 1M ohms with 8bit precision, he probably desires some sort of non-linear response, which he can accomplish by either: 1. Manipulating the current source in his ramp generator, in concert with the counter in his FPGA. - or - 2. Manipulating the counter in his FPGA. The fourth limitation... etc... I hope this resolves some of the confusion. I offer all of these ideas as food for thought. I am certainly interested in hearing of more reasonable solutions to this problem. Regards, Erik Widding. -- Birger Engineering, Inc. -------------------------------- 781.481.9233 38 Montvale Ave #260; Stoneham, MA 02180 ------- http://www.birger.comArticle: 29854
Hi All Warning Newbie present!! Im a little lost as this is my first FPGA design. While the below mentioned project works fine on a CPLD it gets "glitched" when loaded into an FPGA. Its real simple and I suspect there is something very basic Im missing. Imagine I know nothing about FPGAs. I have a very simple circuit, power rails etc to the FPGA and the I/Os arranged in banks of 8 to IDC headers.Connected to one header is a 8bit piano switch bank switched to lo and pulled hi via 10k resistors and the other is a bank of 8 LEDs. The internal schmatic consists of one FD latch. the Q going to an LED and the D going to a switch and the C going to a second switch. As expected the D is mirrored on the Q output on the low to hi transition of the clock. This works fine. However if the C is held low any of the other 8 switches (which remember are not internally connected or mentioned in the sch) can cause the D to be reflected on the Q output. I realise this is a bit hard to visualise. If anyone is interested I can send the project,sch or whatever. FS 2.1i. Im going crazy not being able to work this out. The rest of the project works fine. Cheers MarkArticle: 29855
Peter Alfke wrote: > > Phil Hays wrote: > > > "Theron Hicks (Terry)" wrote: > > > > > By the way, I could not even consider the VirtexII for my application if > > > Xilinx were giving them away. The reason is that they are not available > > > in a package that I can solder. > > > > Do you have a toaster oven? > More seriously, I met with a local small manufacturer, and it soon became > obvious that the days of hand-soldering are over. I'm not sure how serious I should be. If I was building a small board, as an educational or "hobby" or experimental project, with a single BGA (CS144 or FG256 at largest), I'd think about trying the method shown in this web site: http://www.seattlerobotics.org/encoder/200006/oven_art.htm I've seen it done (hmm... but not with a BGA), and my opinion is that using this method could work for BGAs. A few comments: First, for those outside the US the temperatures shown are F, not C. Second, you are not me, and I don't have a clue if it would be a good idea for you to try. You have to decide that for yourself. Clearly you need to not have such a costly part or board that you can't afford to ruin a few boards and/or parts learning. However if you do try it, there are several ideas I'd think about. The first is that solder paste application is probably more critical with a BGA than a TQFP, not because of opens, (which should be less of a problem than with TQFPs, as pin planarity should be better with the BGA), but because of shorts. The first thought would be to carefully put a consistent amount on each pad with a flat toothpick or similar (lots of hand work, doable, but ugh). The second would be to make a silk-screen of the pad layout and put the solder paste on the pads with that. Of course, if you have a reasonable small volume manufacturer nearby that you can afford, why would you bother? And getting the PCB designed and made is a significant project as well. -- Phil HaysArticle: 29856
Let me formulate the conclusion that the original idea of "scanning" a 64 x 64 matrix simply does not work. No matter what you do with the non-active drivers, each of them at any time has a certain voltage, ground or otherwise, and that voltage introduces sneak-currents. Diodes and fets work, but are more expensive and introduce their own errors. Interesting chat. Peter Alfke ========================== Erik Widding wrote: > "Peter Alfke" <peter.alfke@xilinx.com> wrote in message > news:3AAE7A90.BFDEDA38@xilinx.com... > > > > Erik Widding wrote: > > > > > 3. There are a few limitations in the simplest solution, and further > work > > > is still necessary. > > > > The "few limitations" are that the concept inherently does not work. > > Some "limitation"! > > > > I guess I thought Peter's and Larry's comments about the deficiency in the > circuit were self explanatory. If one were to take my initial and flawed > concept, replace each of the 64 fets with 64 fets, one for each of the > resistors in a row, with the gates controlled in the same manner, the > problem is solved. Now we are at the point where a spice simulation would > be in order to determine whether or not the solution would work to one's > requirements. Another solution would be to add 4096 diodes. > > So the economics of the solution are in fact different, as one now needs > 4096 nfets, not the original 64 that I suggested. When posting the follow > up, I thought that one "skilled in the art" would realize that this was the > "over simplification" to which I referred. A suitable low current less than > 10 ohm fet can be had for $0.05 each, plus the cost of placement. You will > also need to add a 3.3v to 10v translator to drive the fets, one for each > row. > > The second limitation is the "precision resistor" in the columns. To get a > linear response, one would want to replace this with a current source, which > basically adds an opamp in parallel with said resistor. > > The third limitation, is that if one is really measuring from 1K to 1M ohms > with 8bit precision, he probably desires some sort of non-linear response, > which he can accomplish by either: > 1. Manipulating the current source in his ramp generator, in concert with > the counter in his FPGA. > - or - > 2. Manipulating the counter in his FPGA. > > The fourth limitation... etc... > > I hope this resolves some of the confusion. I offer all of these ideas as > food for thought. I am certainly interested in hearing of more reasonable > solutions to this problem. > > Regards, > Erik Widding. > > -- > Birger Engineering, Inc. -------------------------------- 781.481.9233 > 38 Montvale Ave #260; Stoneham, MA 02180 ------- http://www.birger.comArticle: 29857
"Peter Alfke" <palfke@earthlink.net> wrote in message news:3AAEFC74.230C3FFF@earthlink.net... > Let me formulate the conclusion that the original idea of "scanning" a 64 x 64 > matrix simply does not work. No matter what you do with the non-active drivers, > each of them at any time has a certain voltage, ground or otherwise, and that > voltage introduces sneak-currents. > Diodes and fets work, but are more expensive and introduce their own errors. I will concede that scanning in its original offerred form will not work. But, as long as there is some sort of switch at every node, all 4K of them, it can be made to work. As is usually the case with engineering a solution, the portion of the design that I found completely uninteresting, and quickly glossed over, was the portion that caused the heartburn. :-( The various parts of this exercise that I find particularly interesting: 1. The economy of the Spartan-II parts is causing us to rethink data acquisiton altogether. 2. Implementing these "mostly digital" solutions still requires us to be good analog engineers. 3. Front end (architecture level) thinking about tolerance and calibration issues can make a great deal of difference. (i.e. using a single voltage ramp, instead of 64 in parallel, to do the conversion) 4. The implementation of the FPGA portion of this design is actually quite minimal. > Interesting chat. Indeed, it has been. Regards, Erik Widding. -- Birger Engineering, Inc. -------------------------------- 781.481.9233 38 Montvale Ave #260; Stoneham, MA 02180 ------- http://www.birger.comArticle: 29858
Im new to vhdl and i was wondering how to use both edges of clockArticle: 29859
Peter Alfke wrote: > Do you have numbers for the Offset voltage, and Common Mode range of the comparitors used for LVDS etc, in the Spartan II. ie, supposing the scanning is resolved, what are the simple analog capabilities of the FPGA pins ? > Let me formulate the conclusion that the original idea of "scanning" a 64 x 64 > matrix simply does not work. No matter what you do with the non-active drivers, > each of them at any time has a certain voltage, ground or otherwise, and that > voltage introduces sneak-currents. Yes, but they can be bridged, or nulled, so you can scan a matrix without series isolating elements, but you do need 64 virtual earth amplifiers ( tho in this case, you might choose 32 Amplifiers, and 128 drivers ) There are limits to the null, you are talking about offset voltage region errors, which multiple by 63 for all the 'off' channels, plus the resistor ratios. Resolving 100K to 0.5% can be calculated. If we take 10K on all 'off' channels, and 100K on the 'on' cross-point, which is a 10:1 safety ratio, then with a 3V drive signal, that's 30uA, 0.5% is 0.15uA, which is the current thru 63 x 10K, or 2.3nA per resistor, (assume all errors are the same direction ) and an offset voltage indicated of 23uV. So, not your LM741 class opamp, but available. A dynamic range of 1R to 1M is not practical. There is also scope to add SW nulling, where a calibration pass is done, to get all Vos levels, and then the first order R Value is used to calculate and remove the injection error effects. > Diodes and fets work, but are more expensive and introduce their own errors. > > Interesting chat.Article: 29860
I'm trying to setup an ethernet controller on a Xilinx Virtex chip and need to control the level1 PHY chip with information that is both on the CPLD and the Virtex FPGA. Does anyone know how to program both at the same time? I'm able to program one but in loading the other .svf or .bit the originally programmed chip looses its functionality. DaveArticle: 29861
Goran,
> Im new to vhdl and i was wondering how to use both edges of clock
since there are no FFs working on both clock edges, you will have to combine
two FFs which are clocked on a single clock edge, see example below. Keep in
mind that constraining such a thing should be done carefully, as the timing
of this circuit depends on the duty cycle of your clock!
-- example -----------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity example is
port(
clk: in STD_LOGIC;
rst: in STD_LOGIC;
slow: in STD_LOGIC;
clkout: out STD_LOGIC);
end example;
architecture bhv of example is
signal xr, xf: STD_LOGIC;
begin
process(clk, rst)
begin
if rst= '1' then
xr<= '0';
elsif rising_edge(clk) then
if slow= '0' then
xr<= not(xr);
end if;
end if;
end process;
process(clk, rst)
begin
if rst= '1' then
xf<= '0';
elsif falling_edge(clk) then
xf<= not(xf);
end if;
end process;
clkout<= xr xor xf;
end bhv;
-- example -----------------------------
Best regards
Felix Bertram
_____
Dipl.-Ing. Felix Bertram
Trenz Electronic
Duenner Kirchweg 77
D - 32257 Buende
Tel.: +49 (0) 5223 49 39 755
Fax.: +49 (0) 5223 48 945
Mailto:f.bertram@trenz-electronic.de
http://www.trenz-electronic.de
Article: 29862dear all, has anyone experience in writing c-code for a nios system from altera? i'm writing c-code for a 16-bit nios system and there are many problems... for example the interrupt-handling and of course the simulation of the source code. i'm also searching a simulator for this system. at the moment, i'm using modelSim (for timing-diagram), but a gui-tool would be better and less time-intensive. has anyone example-programs for a 16-bit nios system? especially with a pio-interface and isr's. or general, has anyone experience in developing a 16-bit nios system? thank's for answers marcoArticle: 29863
On Tue, 13 Mar 2001 11:40:06 +0100, Reinoud <dus@wanabe.nl> wrote: >Hal Murray wrote: >> >> >More seriously, I met with a local small manufacturer, and it soon became >> >obvious that the days of hand-soldering are over. But - at least here in the >> >Valley - such contract assembler are available and do the job for you. I >> >have been suggesting a hobby-friendlier package for the smallest Virtex-II >> >device, but that is a difficult business proposition. >> >> There are a couple of companies now in the business of making >> low volume multilayer PBs. I'll bet similar services will >> become available for soldering BGAs - there is interest/demand. > >BGA parts are practically inaccessible for low volume / experimental >designs for many of us (like at theuniversity - where I work). >Probably the most practical solution for ultra-low-volume users would >be an adapter board (e.g. BGA -> PGA) with decent power decoupling >on board. It would be easiest if preassembled adapters were >commercially available, but having just the boards (or gerbers) >available would go a long way. Xilinx? XUP? How about adding a config device and maybe a local oscillator on board, plus a heatsink and a fan? With a PGA connector or a PCB edge connector. Call them Socket X and Slot V or something... - BrianArticle: 29864
"Jim Granville" <jim.granville@designtools.co.nz> wrote in message news:3AAF1894.7A23@designtools.co.nz... > Do you have numbers for the Offset voltage, and Common Mode range of the > comparitors used for LVDS etc, in the Spartan II. No LVDS in Spartan-II, but various IOB configurations compare Vin against Vref. The extreme seems to be GTL, where VIL(max) = Vref-0.05 VIH(min) = Vref+0.05 The range on Vref seems to be something like 0.68V to 1.7V. So, put the IOBs into GTL mode and manipulate the voltage on Vref? The input common mode range for LVDS in Virtex-E seems to max at 2.2V so this would work over a wider range? (Austin) Is that OK?Article: 29865
Dear all, I have a long list of test vectors in a file which I need to read from my testbench. The xilinx web documentation says that the textio package is unsupported (I get an error also). Do I have to use another package/compiler to run my testbench? What are the alternatives? Any thoughts would be greatly appreciated. Many thanks.Article: 29866
The EPP port has some extra registers
BASEADDR 0x378 Not used in EPP mode
STATUS 0x379 Not used in EPP mode
CONTROL 0x37A Need to set bit 5 to enter EPP mode
LOADDR 0x37B Reading and writing to this will cause an EPP address
read or write
DATAPORT 0x37C EPP data port
This is at least one one byte wide and every one I've seen is two
bytes
So you can outpw to DATAPORT which will write two data bytes to the
EPP
Similarly inpw will read 2 data byte from the EPP port
You can use something like WIN95IO.DLL to talk to IO ports in
windows95/98/mil from C or VB. If you want to do it properly or you are
using NT (No Tinkering) then you'll have to buy some software to access
the IO the "Microsoft way". TVICHW32 is good and cheap and has an
evaluation version but is terribly slow. Have a look an
http://www.lvr.com for all the different ways of skinning this
particular cat.
For example this send an 8 bit address (0x54) and a 32 bit data value
(0x12345678) to the EPP port
union {
short int lsw[2];
long memval;
} conv;
conv.memval=0x12345678
vbOut (LOADDR,0x54);
vbOutw(DATAPORT,conv.lsw[0]);
vbOutw(DATAPORT,conv.lsw[1]);
I also spent a lot of time getting the latching of the strobe signal
sorted in my CPLD design (Lattice 1032 using ABEL and schmatic
capture). I'll send you my state machine if you want but it is designed
to interface with a DSP (SHARC 21061) and so is rather more complicated
than you would want.
John
"F.M. Fontaine" wrote:
>
> A few days ago there was a thread in this newsgroup regarding the
> implementation of a parallel port interface EPP in a FPGA. Having read the
> suggestions in this newsgroup this doesn't seem to be very complicated.
>
> However one thing that worries me a little is the driver software (for
> Win95). How can the EPP port be addressed? Is there a standard driver
> available to address the I/O registers? Should I adjust my BIOS setings to
> have a true EPP port on the LPT, or should it also work in the standard
> ECP-mode?
>
> Any suggestions regarding the driver issue are highly appreciated. Thanks.
>
> Filip Fontaine
Article: 29867Hello Jerry, I had the same problem with the XC2S200-FG456. (Spartan II) (I guess you are toalking about Spartan II 150). My solution was run PARTGEN of Design Manager (v3.2i) using: 'partgen -v 2s200fg456'. With your device I have used 'partgen -v 2s150fg256'. Another solution is to create an empry FPGA in FPGA Editor of Design Manager, and check the IOB (all the IOBs and be carefull because there are a lot UNBOUNDED ;-))) Be carefull again if this is wrong in the schematics... I hope this helps you. I have added the output of Partgen. pin PAD218 R1 6 IO R24C1 N.A. pin PAD221 M4 6 IO R23C1 N.A. pin PAD222 N2 6 IO R23C1 N.A. pin PAD225 L5 6 IO R22C1 N.A. pin PAD226 P1 6 IO R21C1 N.A. pin PAD228 L3 6 IO R21C1 N.A. pin PAD231 M2 6 IO R20C1 N.A. pin PAD232 L4 6 IO R19C1 N.A. pin PAD235 K4 6 IO R18C1 N.A. pin PAD236 L2 6 IO R18C1 N.A. pin PAD237 L1 6 IO R18C1 N.A. pin PAD240 K3 6 IO R17C1 N.A. pin PAD241 K1 6 IO R16C1 N.A. pin PAD244 K2 6 IO R15C1 N.A. pin PAD245 K5 6 IO R15C1 N.A. pin PAD247 J1 6 IO R14C1 N.A. pin PAD248 J4 6 IO R14C1 N.A. pin PAD249 H1 6 IO R14C1 N.A. pin PAD254 H4 7 IO R12C1 N.A. pin PAD256 G5 7 IO R11C1 N.A. pin PAD257 H2 7 IO R11C1 N.A. pin PAD258 G4 7 IO R11C1 N.A. pin PAD260 G2 7 IO R10C1 N.A. pin PAD261 F5 7 IO R10C1 N.A. pin PAD264 F4 7 IO R9C1 N.A. pin PAD265 F1 7 IO R8C1 N.A. pin PAD268 G3 7 IO R7C1 N.A. pin PAD269 F2 7 IO R7C1 N.A. pin PAD270 E1 7 IO R7C1 N.A. pin PAD273 E4 7 IO R6C1 N.A. pin PAD274 E2 7 IO R5C1 N.A. pin PAD277 F3 7 IO R4C1 N.A. pin PAD279 D2 7 IO R4C1 N.A. pin PAD280 E3 7 IO R3C1 N.A. pin PAD283 B1 7 IO R2C1 N.A. pin PAD284 A2 7 IO R2C1 N.A. pin PAD287 C2 7 IO R1C1 N.A. pin PAD2 B3 0 IO R1C2 N.A. pin PAD212 N5 5 IO R24C3 N.A. pin PAD5 C5 0 IO R1C3 N.A. pin PAD211 T2 5 IO R24C3 N.A. pin PAD6 A3 0 IO R1C4 N.A. pin PAD208 P5 5 IO R24C5 N.A. pin PAD9 D5 0 IO R1C5 N.A. pin PAD207 T3 5 IO R24C5 N.A. pin PAD10 E6 0 IO R1C6 N.A. pin PAD205 M6 5 IO R24C6 N.A. pin PAD12 A4 0 IO R1C7 N.A. pin PAD202 T5 5 IO R24C8 N.A. pin PAD15 D6 0 IO R1C8 N.A. pin PAD201 N6 5 IO R24C8 N.A. pin PAD16 B5 0 IO R1C9 N.A. pin PAD198 P6 5 IO R24C10 N.A. pin PAD19 A5 0 IO R1C10 N.A. pin PAD197 R6 5 IO R24C10 N.A. pin PAD20 B6 0 IO R1C11 N.A. pin PAD196 M7 5 IO R24C11 N.A. pin PAD21 C7 0 IO R1C11 N.A. pin PAD192 N7 5 IO R24C13 N.A. pin PAD25 E7 0 IO R1C13 N.A. pin PAD189 T6 5 IO R24C14 N.A. pin PAD28 D7 0 IO R1C15 N.A. pin PAD188 P7 5 IO R24C15 N.A. pin PAD29 C8 0 IO R1C15 N.A. pin PAD186 R7 5 IO R24C16 N.A. pin PAD31 A6 0 IO R1C16 N.A. pin PAD185 T7 5 IO R24C16 N.A. pin PAD32 D8 0 IO R1C17 N.A. pin PAD184 T8 5 IO R24C17 N.A. pin PAD33 A7 0 IO R1C17 N.A. pin GCLKPAD1 R8 5 IO N.A. N.A. pin GCLKPAD3 B8 0 IO N.A. N.A. pin GCLKPAD0 N8 4 IO N.A. N.A. pin GCLKPAD2 C9 1 IO N.A. N.A. pin PAD217 M3 6 IO R24C1 N.A. pin PAD38 A8 1 IO R1C20 N.A. pin PAD177 R9 4 IO R24C20 N.A. pin PAD40 D9 1 IO R1C21 N.A. pin PAD176 N10 4 IO R24C21 N.A. pin PAD41 A9 1 IO R1C21 N.A. pin PAD175 T9 4 IO R24C21 N.A. pin PAD42 E10 1 IO R1C22 N.A. pin PAD173 M10 4 IO R24C22 N.A. pin PAD44 A10 1 IO R1C23 N.A. pin PAD172 R10 4 IO R24C23 N.A. pin PAD45 D10 1 IO R1C23 N.A. pin PAD169 P10 4 IO R24C24 N.A. pin PAD48 B10 1 IO R1C25 N.A. pin PAD165 T10 4 IO R24C26 N.A. pin PAD52 C10 1 IO R1C27 N.A. pin PAD164 R11 4 IO R24C27 N.A. pin PAD53 A11 1 IO R1C27 N.A. pin PAD163 M11 4 IO R24C27 N.A. pin PAD54 B11 1 IO R1C28 N.A. pin PAD160 N11 4 IO R24C29 N.A. pin PAD57 A12 1 IO R1C29 N.A. pin PAD159 R12 4 IO R24C29 N.A. pin PAD58 D11 1 IO R1C30 N.A. pin PAD156 P11 4 IO R24C31 N.A. pin PAD61 A13 1 IO R1C31 N.A. pin PAD154 T13 4 IO R24C32 N.A. pin PAD63 B12 1 IO R1C32 N.A. pin PAD153 N12 4 IO R24C32 N.A. pin PAD64 D12 1 IO R1C33 N.A. pin PAD150 R13 4 IO R24C34 N.A. pin PAD67 A14 1 IO R1C34 N.A. pin PAD149 P12 4 IO R24C34 N.A. pin PAD68 C12 1 IO R1C35 N.A. pin PAD146 P13 4 IO R24C36 N.A. pin PAD145 T14 4 IO R24C36 N.A. pin PAD140 T15 3 IO R23C36 N.A. pin PAD139 M13 3 IO R23C36 N.A. pin PAD136 R16 3 IO R22C36 N.A. pin PAD135 M14 3 IO R22C36 N.A. pin PAD133 M15 3 IO R21C36 N.A. pin PAD130 L12 3 IO R20C36 N.A. pin PAD129 P16 3 IO R20C36 N.A. pin PAD124 K14 3 IO R18C36 N.A. pin PAD121 L16 3 IO R17C36 N.A. pin PAD120 K13 3 IO R17C36 N.A. pin PAD117 L15 3 IO R16C36 N.A. pin PAD116 K12 3 IO R15C36 N.A. pin PAD113 J14 3 IO R14C36 N.A. pin PAD112 K15 3 IO R14C36 N.A. pin PAD107 H14 2 IO R12C36 N.A. pin PAD105 H15 2 IO R12C36 N.A. pin PAD104 J13 2 IO R11C36 N.A. pin PAD101 G14 2 IO R10C36 N.A. pin PAD100 G15 2 IO R10C36 N.A. pin PAD97 G12 2 IO R9C36 N.A. pin PAD96 F16 2 IO R9C36 N.A. pin PAD93 G13 2 IO R8C36 N.A. pin PAD88 D16 2 IO R6C36 N.A. pin PAD87 F12 2 IO R6C36 N.A. pin PAD84 E15 2 IO R5C36 N.A. pin PAD82 E14 2 IO R4C36 N.A. pin PAD81 C16 2 IO R4C36 N.A. pin PAD78 E13 2 IO R3C36 N.A. pin PAD77 B16 2 IO R2C36 N.A. pin PAD179 N9 4 IO R24C19 N.A. pin PAD74 D14 2 IO_DIN_D0 R1C36 N.A. pin PAD91 E16 2 IO_D1 R7C36 N.A. pin PAD92 F15 2 IO_D2 R7C36 N.A. pin PAD103 G16 2 IO_D3 R11C36 N.A. pin PAD108 H16 2 IO_IRDY R13C36 N.A. pin PAD109 J15 3 IO_TRDY R13C36 N.A. pin PAD114 J16 3 IO_D4 R15C36 N.A. pin PAD125 M16 3 IO_D5 R18C36 N.A. pin PAD126 N16 3 IO_D6 R19C36 N.A. pin PAD143 N14 3 IO_D7 R24C36 N.A. pin PAD144 N15 3 IO_INIT R24C36 N.A. pin PAD72 B13 1 IO_CS R1C36 N.A. pin PAD71 C13 1 IO_WRITE R1C36 N.A. pin PAD253 G1 7 IO_IRDY R12C1 N.A. pin PAD252 J2 6 IO_TRDY R13C1 N.A. pin PAD73 C15 2 IO_DOUT_BUSY R1C36 N.A. pkgpin GND A1 -1 GND N.A. N.A pkgpin VCCINT C3 -1 VCCINT N.A. N.A pkgpin VCCINT C14 -1 VCCINT N.A. N.A pkgpin VCCINT D4 -1 VCCINT N.A. N.A pkgpin TDI A15 -1 TDI N.A. N.A pkgpin TDO B14 -1 TDO N.A. N.A pkgpin CCLK D15 -1 CCLK N.A. N.A pkgpin VCCINT D13 -1 VCCINT N.A. N.A pkgpin VCCINT E5 -1 VCCINT N.A. N.A pkgpin VCCINT E12 -1 VCCINT N.A. N.A pkgpin PROGRAM P15 -1 PROGRAM N.A. N.A pkgpin DONE R14 -1 DONE N.A. N.A pkgpin VCCINT M5 -1 VCCINT N.A. N.A pkgpin VCCINT M12 -1 VCCINT N.A. N.A pkgpin VCCINT N4 -1 VCCINT N.A. N.A pkgpin STATUS R4 -1 STATUS N.A. N.A pkgpin PWDN P4 -1 PWDN N.A. N.A pkgpin M2 R3 -1 M2 N.A. N.A pkgpin M0 N3 -1 M0 N.A. N.A pkgpin M1 P2 -1 M1 N.A. N.A pkgpin VCCINT N13 -1 VCCINT N.A. N.A pkgpin VCCINT P3 -1 VCCINT N.A. N.A pkgpin VCCINT P14 -1 VCCINT N.A. N.A pkgpin TMS D3 -1 TMS N.A. N.A pkgpin VCCO_0 F8 -1 VCCO_0 N.A. N.A pkgpin VCCO_0 E8 -1 VCCO_0 N.A. N.A pkgpin VCCO_1 F9 -1 VCCO_1 N.A. N.A pkgpin VCCO_1 E9 -1 VCCO_1 N.A. N.A pkgpin VCCO_2 H12 -1 VCCO_2 N.A. N.A pkgpin TCK C4 -1 TCK N.A. N.A pkgpin VCCO_3 J12 -1 VCCO_3 N.A. N.A pkgpin VCCO_3 J11 -1 VCCO_3 N.A. N.A pkgpin VCCO_4 M9 -1 VCCO_4 N.A. N.A pkgpin VCCO_4 L9 -1 VCCO_4 N.A. N.A pkgpin VCCO_5 M8 -1 VCCO_5 N.A. N.A pkgpin VCCO_5 L8 -1 VCCO_5 N.A. N.A pkgpin VCCO_6 J6 -1 VCCO_6 N.A. N.A pkgpin VCCO_6 J5 -1 VCCO_6 N.A. N.A pkgpin VCCO_7 H6 -1 VCCO_7 N.A. N.A pkgpin VCCO_7 H5 -1 VCCO_7 N.A. N.A pkgpin GND T16 -1 GND N.A. N.A pkgpin GND T1 -1 GND N.A. N.A pkgpin GND R15 -1 GND N.A. N.A pkgpin GND R2 -1 GND N.A. N.A pkgpin GND L11 -1 GND N.A. N.A pkgpin GND L10 -1 GND N.A. N.A pkgpin GND L7 -1 GND N.A. N.A pkgpin GND L6 -1 GND N.A. N.A pkgpin GND K11 -1 GND N.A. N.A pkgpin GND K10 -1 GND N.A. N.A pkgpin GND K9 -1 GND N.A. N.A pkgpin GND K8 -1 GND N.A. N.A pkgpin GND K7 -1 GND N.A. N.A pkgpin GND K6 -1 GND N.A. N.A pkgpin GND J10 -1 GND N.A. N.A pkgpin GND J9 -1 GND N.A. N.A pkgpin GND J8 -1 GND N.A. N.A pkgpin GND J7 -1 GND N.A. N.A pkgpin GND H10 -1 GND N.A. N.A pkgpin GND H9 -1 GND N.A. N.A pkgpin GND H8 -1 GND N.A. N.A pkgpin GND H7 -1 GND N.A. N.A pkgpin GND G11 -1 GND N.A. N.A pkgpin GND G10 -1 GND N.A. N.A pkgpin GND G9 -1 GND N.A. N.A pkgpin GND G8 -1 GND N.A. N.A pkgpin GND G7 -1 GND N.A. N.A pkgpin GND G6 -1 GND N.A. N.A pkgpin GND F11 -1 GND N.A. N.A pkgpin GND F10 -1 GND N.A. N.A pkgpin GND F7 -1 GND N.A. N.A pkgpin GND F6 -1 GND N.A. N.A pkgpin GND B15 -1 GND N.A. N.A pkgpin GND B2 -1 GND N.A. N.A pkgpin GND A16 -1 GND N.A. N.A pkgpin VCCO_2 H11 -1 VCCO_2 N.A. N.A pin PAD83 F13 2 IO_VREF_2 R4C36 N.A. pin PAD90 F14 2 IO_VREF_2 R7C36 N.A. pin PAD102 H13 2 IO_VREF_2 R11C36 N.A. pin PAD115 K16 3 IO_VREF_3 R15C36 N.A. pin PAD127 L13 3 IO_VREF_3 R19C36 N.A. pin PAD134 L14 3 IO_VREF_3 R21C36 N.A. pin PAD62 C11 1 IO_VREF_1 R1C32 N.A. pin PAD155 T12 4 IO_VREF_4 R24C31 N.A. pin PAD55 E11 1 IO_VREF_1 R1C28 N.A. pin PAD162 T11 4 IO_VREF_4 R24C28 N.A. pin PAD43 B9 1 IO_VREF_1 R1C22 N.A. pin PAD174 P9 4 IO_VREF_4 R24C22 N.A. pin PAD30 B7 0 IO_VREF_0 R1C16 N.A. pin PAD187 P8 5 IO_VREF_5 R24C15 N.A. pin PAD18 C6 0 IO_VREF_0 R1C10 N.A. pin PAD199 R5 5 IO_VREF_5 R24C9 N.A. pin PAD11 B4 0 IO_VREF_0 R1C6 N.A. pin PAD206 T4 5 IO_VREF_5 R24C6 N.A. pin PAD278 C1 7 IO_VREF_7 R4C1 N.A. pin PAD271 D1 7 IO_VREF_7 R6C1 N.A. pin PAD259 H3 7 IO_VREF_7 R10C1 N.A. pin PAD246 J3 6 IO_VREF_6 R15C1 N.A. pin PAD234 M1 6 IO_VREF_6 R19C1 N.A. pin PAD227 N1 6 IO_VREF_6 R21C1 N.A. "Jerry English" <jenglish@wherenet.com> wrote in message news:ee6fe8f.-1@WebX.sUN8CHnE... > I need to assign signals to the > Spartan 150 in a fg256 package > before the design is complete. I > would like documention that list the > pad to pin connection for the above > mentioned part. That way I can assign inputs on the left with lsb on the bottoms. Would anybody point > me to that data, please. > > Thanks > Jerry EnglishArticle: 29868
Has anyone used an Atmel AT17Cxxx in an 8Dip to configure an Altera FLEX10 FPGA? The parts are cheaper, I'm told. thanks, tomArticle: 29869
Marco Landert wrote: > > dear all, > > has anyone experience in writing c-code for a nios system from altera? > i'm writing c-code for a 16-bit nios system and there are many > problems... > or general, has anyone experience in developing a 16-bit nios system? Marco, What's the documentation like in the Excalibur development suite? I thought that the introduction of these CPU cores would have been greeted with more (or some) enthusiasm here, but there's been very little mantion of them. The documentation on the Altera web site is fairly limited, I suppose this may be putting people off. I also noticed the only 'testimonial' was from the VP of synopsys saying that their tools supported Excalibur, hardly a testimonial! I think Altera are going to have to put a bit more effort into supporting this is they want more take up/interest. They should have at least see a couple of detailed example designs documentated on the web site so you could see what's involved in implementing one of these processors. Nial.Article: 29870
On Wed, 14 Mar 2001 15:26:32 -0000, "Mark Anstice" <mark@des.co.uk> wrote: >Dear all, > >I have a long list of test vectors in a file which I need to read from my >testbench. The xilinx web documentation says that the textio package is >unsupported (I get an error also). Do I have to use another >package/compiler to run my testbench? What are the alternatives? Any >thoughts would be greatly appreciated. > >Many thanks. > You need to download the ModelSim Simulator for running a testbench. This simulator then supports the textio package. The VHDL-Compiler furnished with Xilinx WebPack is for synthesis only. Hope this helps Klaus Falser Klaus R&D Electronics Department Company : Durst Phototechnik AG Vittorio Veneto Str. 59 I-39042 Brixen Voice : +0472/810235 : +0472/810111 FAX : +0472/830980 Email : kfalser@IHATESPAMdurst.itArticle: 29871
nial, are there any documentations...? no, serious: the documentations (whitch you have to search) are not really detailed. the main problem is, that the 16-bit version includes bugs and (altera has became conscious of them) you don't know exactly what should works correct. if you know an adress, where i could find more information/ documentation/ example programs about nios, just tell me this. marco Nial Stewart schrieb: > Marco, > > What's the documentation like in the Excalibur development suite? > I thought that the introduction of these CPU cores would have been > greeted with more (or some) enthusiasm here, but there's been > very little mantion of them. > > The documentation on the Altera web site is fairly limited, > I suppose this may be putting people off. I also noticed the > only 'testimonial' was from the VP of synopsys saying that > their tools supported Excalibur, hardly a testimonial! > > I think Altera are going to have to put a bit more effort into > supporting this is they want more take up/interest. > > They should have at least see a couple of detailed example > designs documentated on the web site so you could see what's > involved in implementing one of these processors. > > Nial.Article: 29872
Mark schrieb: > > Hi All > Warning Newbie present!! > Im a little lost as this is my first FPGA design. While the below mentioned project works fine on a CPLD it gets "glitched" when loaded into an FPGA. > Its real simple and I suspect there is something very basic Im missing. Imagine I know nothing about FPGAs. > I have a very simple circuit, power rails etc to the FPGA and the I/Os arranged in banks of 8 to IDC headers.Connected to one header is a 8bit piano switch bank switched to lo and pulled hi via 10k resistors and the other is a bank of 8 LEDs. The internal schmatic consists of one FD latch. the Q going to an LED and the D going to a switch and the C going to a second switch. > As expected the D is mirrored on the Q output on the low to hi transition of the clock. This works fine. However if the C is held low any of the other 8 switches (which remember are not internally connected or mentioned in the sch) can cause the D to be reflected on the Q output. I realise this is a bit hard to visualise. If anyone is interested I can send the project,sch or whatever. FS 2.1i. Strange. Send me the schematics, I will have a look on it. -- MFG FalkArticle: 29873
Marco Landert <e-mail@landert.org> writes: : [...] : has anyone experience in writing c-code for a nios system from altera? : i'm writing c-code for a 16-bit nios system and there are many problems... : for example the interrupt-handling and of course the simulation of the : source code. i'm also searching a simulator for this system. [...] Are you aware of the NIOS 16/32-bit instruction-set simulators that are part of the GNUPro toolchain that comes with the Excalibur kit? - FChEArticle: 29874
Dear all, Currently I am employed with a leading VHDL /design house in the Netherlands called Lumino. In order to keep our leading position we would like to get in touch with international company's and VHDL specialists to share knowledge, capacity and projects. Also we would like to get informed about any previous experiences with outsourcing or subcontracting via the internet. Any information will be helpfull, Thanks in advance, Danny Niewzwaag danny@niewzwaag.com
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