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Nick Hartl ("nhartl[nospm]"@earthlink.net) wrote:
: You can by Foundation Base for $95 bucks. It contains all that you need for
: design. Schematic capture, simulation and Place and Route.
Don't the Xilinx (et al.) apologists get tired of saying this?
I personally cannot stomach binary-ware.
I will not run it,
I will not use it,
I can't support it,
Sam I am.
If it's not source code, it's not software. If I can't copy it,
port it, fix it, modify it, it's just so many useless bits on a disk.
So no, Foundation Base is _not_ "all that you need".
: > In particular I have XC2018, XC2064, XC3020 and XC3064 parts.
: Now this is a problem. XC2ks are no longer supported also the versions of
: 3ks that you name are not in the new Foundation box. Now if one could find a
: Foundation Xact 6.01 then you would be all set.
My point. If the "nearly free" ($95 binary-ware) were truly free,
or if those old parts actually had a programming spec, this problem
would be inherently tractable.
Time to crawl back in my hole. Maybe someday a hardware company will
have the guts to tell its users how to program the chip. Oops, Intel
already did that back in the '70s, and look how far it got them.
- Larry Doolittle <ldoolitt@jlab.org>
[ sorry for the posting delay, our news server croaked,
and it took me a while to find a backup ]
Article: 9526Hello Jamil, Dual port memory has two sets of address and data lines. It can be accessed by two different systems simultaneously except for the case of writing/reading to the same exact memory address. If this occurs, an arbitration is done to inhibit one side and sometimes this arbitration circuitry is built into the memory device. Dual port memory is useful for sharing data between two processors, peripheral devices on a system bus and many other applications. It differs from shared memory because the memory device has 2 seperate data and address buses which allows simultaneous access except as noted above. Shared memory uses conventional memory devices and relies on buffers to select between accesses thus only one system can access the memory at a time. hth, Dale J. Khatib wrote in message <3512bf98.4883349@news.planet.edu>... >What is the dual port memory? > >thanks in advanceArticle: 9527
Hi I need to access an Atmel chip AT88SC1608. I want to read and write into it using C. Pls let me know how. Thanx Anil -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 9528
Here you may find details on DPM circuits http://www.idt.com/specmem/Welcome_MultiPort.html J. Khatib wrote in message <3512bf98.4883349@news.planet.edu>... >What is the dual port memory? > >thanks in advanceArticle: 9529
Please check out MY SEMICONDUCTOR LINKPAGE at http://home.t-online.de/home/a.tillmann where you can find links to companies, organizations, research institutes and university research groups involved in semiconductor research and development. If you want me to add your URL please send me an e-mail. Best regards, Andreas TillmannArticle: 9530
Boulder; Design Engineer; High Speed Digital, FPGA, DSPs -Salaried; Full-Time; Excellent Benefits; Paid Relocation Requires a strong knowledge of Intel or Motorola micro-controllers and support circuitry. Must also have strong background with complex programmable logic devices and FPGAs. Experience with Digital Signal processors, stepper and micro-stepping drivers. Controllers are a big plus. This position requires 5 years of related experience. Please refer to JO# 4136RJS in your response. Richard Steinman Team Leader rjs@cmagroup.com IT & Software Solutions Team Career Marketing Associates http://www.cmagroup.com/IT.htmlArticle: 9531
Is this the newgroup for front page 98 97 people? Or am I in the wrong place? What does fpga mean???? MichelleArticle: 9532
Anyone know how to get the JTAG ports/pins to propagate into a structural Verilog netlist after compiling the design in M1? Thanks, BobArticle: 9533
Hi, We have an opportunity for an individual who has done some complex Circuit Board/FPGA design to work at a place where cutting edge technology is the norm, and one of the very best design staffs in the country awaits. This position is for someone who has between 3-10 years of high performance custom circuit design under his/her belt. You will be working on some of the "neatest" projects you've ever seen, and will become a stellar hardware designer for your efforts. Some of the "buzz": We are looking for High Speed Digital Designers, having some experience with PLD's, FPGA's (ASICS), complex designs (nothing simple at this place), understands timings, etc... Not a person who still needs a lot of instruction, we are hoping to find an individual who can stand alone and bring a project in from scratch to production. This is a great company! Our guarantee is this: If you go in and chat with these people, you WILL want to work there, especially if you can do this type of work. They are located on the North side of Chicago, near Skokie or Evanston, just off the Kennedy. Salary will be very nice, they're not cheap, as they're looking for the best we can bring in. Please E-mail or Fax us at: Hunter International E-mail: cleaner@starnetinc.com Fax: (815)356-9225 Thanks, Dave...Article: 9534
!!!n5mpa@mci2000.com!!! (Michelle) wrote: >Is this the newgroup for front page 98 97 people? Or am I in the wrong >place? What does fpga mean???? Michelle The is the newsgroup for 'Field Programmable Gate Arrays'.Article: 9535
Please visit our website: http://www.fpga-design.com/Article: 9536
Dear Sirs,
We are students in Ain Shams University - Faculty of Engineering -
Electric Power Section, in Egypt. We are in our last year. Our graduation
project is using the PLC (Programmable Logic Controller) in a real
application. We still can't decide the application. We thought you can help
us due to your great experience.
We will need some examples of applications fulfilling the following
conditions:
- Something that may be useful for us in the future as electric power
engineers.
- Something that is not very complicated, yet not very simple.
- Something useful for the society.
- Something including motion, as in electromechanical systems.
- Something that can be simulated, i.e. a prototype of it can be easily
made.
Knowing that our PLC device has :
20 I/O
Please reply, if possible, ASAP.
Thank you in advance for your concern and help. We appreciate your
cooperation very much.
Please reply at blushy_girl@mailcity.com
Article: 9537This is a multi-part message in MIME format. --------------8889557DC9E64046E842B3A2 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Dale E. Redford wrote: > > Hello Jamil, > > Dual port memory has two sets of address and data lines. It can be accessed > by two different systems simultaneously except for the case of > writing/reading to the same exact memory address. If this occurs, an > arbitration is done to inhibit one side and sometimes this arbitration > circuitry is built into the memory device. > > Dual port memory is useful for sharing data between two processors, > peripheral devices on a system bus and many other applications. It differs > from shared memory because the memory device has 2 seperate data and address > buses which allows simultaneous access except as noted above. Shared > memory uses conventional memory devices and relies on buffers to select > between accesses thus only one system can access the memory at a time. > > hth, > Dale > > J. Khatib wrote in message <3512bf98.4883349@news.planet.edu>... > >What is the dual port memory? > > > >thanks in advance Ref Xilinx 4000E and Spartan.... There is no arbitration logic provided or, in simplistic terms, needed. The DPSRAM in the parts have separate read and write data and address ports - you can be reading and writing the same address at the same time. Now...... does one really want to do that???? Well..... usually not but there have been occasions. -- Ed McCauley Bottom Line Technologies Inc. Specializing Exclusively in Xilinx Design, Development and Training Voice: (500) 447-FPGA, (908) 996-0817 FAX: (908) 996-0817 --------------8889557DC9E64046E842B3A2 Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Ed McCauley Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: Ed McCauley n: McCauley;Ed org: Bottom Line Technologies Inc. email;internet: edmccauley@bltinc.com title: President x-mozilla-cpt: ;0 x-mozilla-html: TRUE version: 2.1 end: vcard --------------8889557DC9E64046E842B3A2--Article: 9538
Richard, I just read your most recent post, and I'm trying to figure out if it's to me or not. You mentioned that I've made numerous posts complaining about a shipment, but I've only made two posts, and one of those was to respond to you. Maybe somebody else is posting, someone that you think is me? Also, you said you offered a shipment refund to me, and I've never received such an offer. I believe that you're thinking of somebody else. -PaulArticle: 9539
Richard, Whether or not you were referring to me about the numerous complaints you've received, I want to apologize now for those two messages that I did post. I should have left those issues in the past, where they belonged. From what you've said, my guess is, my experience was a rare one, and that usually APS has much better success shipping their product. I understand that I asked for a special date for delivery of the APS kit, and I asked this around Christmas time, and I realize that this is probably what messed things up for everybody. I can tell from the frustration of your last message that this is the point you're trying to make. And although this is the first I've heard of it, your offer to refund shipping costs I think is a sincere offer, an attempt to set things right. The offer's enough for me; I'm not interested in the refund. I'm just hoping that if you'll accept my public apology for my public complaints, that we can put the whole matter behind us. Sincerely, -PaulArticle: 9540
In article <3510F21F.3561@ife.ee.ethz.ch>, Thomas Sailer <sailer@ife.ee.ethz.ch> wrote: >Uwe Bonnes wrote: >> >> keiser anthony lynn <akeiser@ews.uiuc.edu> wrote: >> : I am trying to make an xchecker download program to run on Linux. >> : I have found the schematics on Xilinx's web page, but can find no >> : information on any of the "commands" that are obviously being stored >> : in the XC3042 and/or SRAM. Any help you can provide would be >> : appreciated. > >Depends on what you want to do, but maybe you can use Xilinx's >parallel cable, which consists only of two 74HC125 and therefore >should be easy to figure out. Agreed the above commentary is valid. Another approach is to ask Xilinx.. A reasonable question might well get you the info you've wanted... FWIW, Arnim. -- Arnim Littek arnim@actrix.gen.nz Actrix Networks Ltd. fax +64-4-801-5335 uucp/PPP/SLIP/BBS accounts tel +64-4-801-5225Article: 9541
Funny, I was digging through the Xilinx AllianceCORE products on their website, I was dumbfounded seeing a T1 framer there. Trick is, it's a _single_ framer, has NO elastic stores (according to the block diagram in the datasheet at least), and it takes 1236 or so CLBs, meaning it won't fit in anything smaller than a XC4036EX and apparently uses all the CLB's in a 4036. I checked the price of the device it is tailored to, it's about $500 in single units, add to that the $6000 cost of the core design. Now, call me an idiot (no, on second thought, don't), but Dallas Semiconductor sells a QUAD (4 of em baby!) T1 framer that has transmit and receive elastic stores on each one, and it fits in a teeny-tiny 128 pin thin flatpack. It costs about $83 in singles. They also have E1 equivalents, and also single-channel all-in-one solutions too. So if I want to handle four T1's with a Xilinx, I'd need four XC4036EX-HQ240's, roughly $2000 bucks. For a usable system I'd still need 4 transceivers and 4 bidirectional elastic stores too. Oh yeah, and pay $6000 for the license. Oh yeah, does board real-estate come free with that? With a DS21Q41A, I'd have one $83 chip, and add 4 transceivers. And I'd have lots of space left over, maybe I could put in a golf course. So, is there some logic behind providing a $2000 solution to an $83 problem, or what? I don't work for any of the makers of the previously mentioned products.Article: 9542
It's probably done in VHDL or Verilog....or just poorly implemented... Bryan Williams <bk&dontyabespamminme&willi@smart.net> wrote in article <3514933a.592570024@enews.newsguy.com>... > Funny, I was digging through the Xilinx AllianceCORE products on their > website, I was dumbfounded seeing a T1 framer there. Trick is, it's a > _single_ framer, has NO elastic stores (according to the block diagram > in the datasheet at least), and it takes 1236 or so CLBs, meaning it > won't fit in anything smaller than a XC4036EX and apparently uses all > the CLB's in a 4036. I checked the price of the device it is tailored > to, it's about $500 in single units, add to that the $6000 cost of the > core design. > > Now, call me an idiot (no, on second thought, don't), but Dallas > Semiconductor sells a QUAD (4 of em baby!) T1 framer that has transmit > and receive elastic stores on each one, and it fits in a teeny-tiny > 128 pin thin flatpack. It costs about $83 in singles. They also have > E1 equivalents, and also single-channel all-in-one solutions too. > > So if I want to handle four T1's with a Xilinx, I'd need four > XC4036EX-HQ240's, roughly $2000 bucks. For a usable system I'd still > need 4 transceivers and 4 bidirectional elastic stores too. Oh yeah, > and pay $6000 for the license. Oh yeah, does board real-estate come > free with that? > > With a DS21Q41A, I'd have one $83 chip, and add 4 transceivers. And > I'd have lots of space left over, maybe I could put in a golf course. > > So, is there some logic behind providing a $2000 solution to an $83 > problem, or what? > > I don't work for any of the makers of the previously mentioned > products. > > >Article: 9543
To me it looks like the original post has been cancelled. >Oh, Thank you! > >Do you happen to have one for Viewlogic ;-) That is an even much more >annoying key! I hear it can not be cracked... Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 9544
We offer digital design services for all your FPGA/CPLD solutions with all Xilinx and Orca devices. Please visit our Web site at: http://www.fpga-design.com/ Michelle Tran icommtek@fpga-design.comArticle: 9545
In article <3519eff5.6953027@news.netcomuk.co.uk>, Peter <z80@ds2.com> wrote: >To me it looks like the original post has been cancelled. > >>Do you happen to have one for Viewlogic ;-) That is an even much more >>annoying key! I hear it can not be cracked... Almost certainly someone is fishing... Arnim. -- Arnim Littek arnim@actrix.gen.nz Actrix Networks Ltd. fax +64-4-801-5335 uucp/PPP/SLIP/BBS accounts tel +64-4-801-5225Article: 9546
MASTER CLASS on RECONFIGURABLE COMPUTING
Call for Contributions
For an HTML version of this document with links see
http://www.cis.unisa.edu.au/~cisdak/RCMC/masterclass.html
The Concurrent Systems Laboratory of the Advanced Computing Research
Centre, within the School of Computer and Information Science at the
University of South Australia, is organizing a Master Class in
reconfigurable computing on Wednesday 30th September 1998 (followed by a
Workshop on the SPACE.2 reconfigurable computing platform on Thursday 1
October) at the University of South Australia's Levels Campus, which is
located less then 30 minutes drive from world renowned Australian wine
growing district of the Barossa Valley and only 15 minutes from Adelaide,
one of the major cultural centres of Australia.
Participants and contributors can combine their attendance with the 5th
Australasian Conference on Parallel and Real Time Systems (PART'98), to be
held in Adelaide on the 28th and 29th of Septemeber 1998, making a four day
program.
Contributions are sought from researchers in the field of Reconfigurable
Computing to make presentations in the Master Class of up to 50 minutes
duration on an aspect of work in progress in the field.
Areas of particular interest are:
* Programming languages
* Applications implemented on reconfigurable computer platforms
* Architectures for new machines
* Theory and practice of fast run-time reconfiguration
* Operating systems and development environments for reconfigurable
computing platforms
Suggested topics should be submitted in the form of an approximately
300 word abstract and a short CV of the speaker, and sent to:
Chair, Program Committee
Reconfigurable Master Class
School of Computer and Information Science
University of South Australia
Warrendi Road, Mawson Lakes, SA 5095
AUSTRALIA
Fax +61 8 8302 3381
email: David.Kearney@unisa.edu.au
----------------------------------------------------------------------------
David Kearney | cisdak@ares.levels.unisa.edu.au
,-_|\ Computer and Information |
/ \ Science |
\_,-*_/ University of South Australia |
v Warrendi Rd. The Levels 5095 |
Adelaide Australia |Ph +618 8302 3287 Fax +618 8302 3381
----------------------------------------------------------------------------
Article: 9547J. Khatib wrote: > What is the dual port memory? > > thanks in advance A dual-port memory has two independent access ports to a common memory. In the most general case, both ports can provide read and write access independent of each other. Obviously, there are tricky timing issues when both ports access the same memory cell.Dual-port memories are ideal for implementing FIFOs and communications mailboxes between asynchromous systems. Peter Alfke, Xilinx ApplicationsArticle: 9548
Ed McCauley wrote: > > Dale E. Redford wrote: > > > > Hello Jamil, > > > > Dual port memory has two sets of address and data lines. It can be accessed > > by two different systems simultaneously except for the case of > > writing/reading to the same exact memory address. If this occurs, an > > arbitration is done to inhibit one side and sometimes this arbitration > > circuitry is built into the memory device. > > > > Dual port memory is useful for sharing data between two processors, > > peripheral devices on a system bus and many other applications. It differs > > from shared memory because the memory device has 2 seperate data and address > > buses which allows simultaneous access except as noted above. Shared > > memory uses conventional memory devices and relies on buffers to select > > between accesses thus only one system can access the memory at a time. > > > > hth, > > Dale > > > > J. Khatib wrote in message <3512bf98.4883349@news.planet.edu>... > > >What is the dual port memory? > > > > > >thanks in advance > > Ref Xilinx 4000E and Spartan.... > > There is no arbitration logic provided or, in simplistic terms, needed. > The DPSRAM in the parts have separate read and write data and address > ports - you can be reading and writing the same address at the same > time. Now...... does one really want to do that???? Well..... usually > not but there have been occasions. > At least some of the dual port memories, such as Integrated Devices Technology (IDT) have a busy signal that locks out simultaneous writes to the same location. The other operations are simultaneously allowed. Quite useful in high speed data transmission between main processors and I/O processors. Some of the Dual port memories also implement hardware mailbox functions with interrupts automatically generated -- Don Labriola > -- > Ed McCauley > Bottom Line Technologies Inc. > Specializing Exclusively in Xilinx Design, Development and Training > Voice: (500) 447-FPGA, (908) 996-0817 > FAX: (908) 996-0817 > > --------------------------------------------------------------- > > Name: vcard.vcf > Part 1.2 Type: text/x-vcard > Encoding: 7bit > Description: Card for Ed McCauleyArticle: 9549
Don Labriola wrote: > > Ed McCauley wrote: > > > > Dale E. Redford wrote: > > > > > > Dual port memory has two sets of address and data lines. It can be accessed > > > by two different systems simultaneously except for the case of > > > writing/reading to the same exact memory address. If this occurs, an > > > arbitration is done to inhibit one side and sometimes this arbitration > > > circuitry is built into the memory device. The xilinx dual port memory has dual port read access, but only single port write access. With these memories, you can simultaneously read two locations or be writing one while reading another (or the same one). Since the second port is read only, there is no inherent need for arbitration. Contrasted with the memories in other FPGAs, such as the EAB in the altera, this is a better set-up IMHO. ALtera EABs get 'dual porting' by cycle splitting...that means that you get half the memory bandwidth, and more importantly no simultaneous read/write at different locations.
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