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Max+Plus II 8.2 can combine .sof files to generate .sbf, .rbf, pof..etc using command line. I am not sure of any way with Max+plus II 8.1 or earlier versions. Ying ying@csua.berkeley.edu In article <351A59A1.D1B4B9E3@singnet.com.sg>, yt <furnitec@singnet.com.sg> wrote: >Can Maxplus2 supports command line input to combine .sof files to .sbf ? >or any other method without using Maxplus2. > >Regards >Verasco >Article: 9651
Austin Franklin wrote: > > <suggestions of how to break Xilinx and Viewlogic security devices> > > > > How can you justify promoting the removal of security devices? > > You can't be serious? This has to be either a troll or from someone very > inexperienced in hardware keys. > > > Surely > > the resulting illegal copying of software (the use to which many would > > inevitably put this information) is against the interest of both the > > paying customers and those who make a living from providing and > > supporting the software? > > I have many reasons why I don't want the key. One is I use a notebook, and > carrying around the key (and 6 others) is ridiculous and risky. If I loose > the key (which they are easy to loose) or someone steals it while I'm out > of the office (much easier to steal than the computer it self, and it can't > be locked, the computer can) then I'm SOL. > > No one is promoting making illegal copies, or illegally using the software. > That is something you read into this. > > Anyway, it has been proven beyond the shadow of a doubt that companies are > NOT 'deprived' of their income by pirated software, as %99 of pirated > software is used by someone who would not have bought it in the first > place, also a good number of them, if they are using the software > regularly, eventually do buy it. It's the best marketing tool the software > industry has to offer. > > For me, and I would guess many other engineers in the EDA business who > > come here, the very existence of this thread is a sad occasion for the > > group. > > What's sadder to me is you assume people are going to use the key-removals > to promote illegal use of the software, when that is NOT the case at all. Exactly, No one in his right mind who is into some serious business will design products using pirated software.Sam Falaki > > > Austin Franklin > darkroom@ix.netcom.comArticle: 9652
>A question:- what is the position of software vendors towards replacing >dead dongles for users who are no longer under maintenance? This doesn't >seem to be made clear on shrink-wrap licenses. Strange, that... I would guess that it would vary. I just went through that with Aldec in eference to a legitimate copy of Susie v6.12 that I own. I paid $10,000 for it. When the dongle quit working, they soaked me for $250 to replace it. Absolutely unconcionable! I was livid. That's blackmail. What that is saying to me is this. "You may have paid $10,000 for the software, but we'renot going to let you use it unless you give us more money. The software is legitimate. There was/is no problem woth attempting to ilegaly use the software. I JUST WANTED TO USE THE SOFTWARE THAT I'D ALREADY PAID A FORTUNE FOR. Yes. I'm very much in favor of "cracks" that remove that kind of harassment from my life. Those who think otherwise can just go and get santimonious somewhere else. I'm not trying to steal anything. But, when you tell me that I can't use the software I've already paid for, then I've got a real problem with that. >For the record, neither I nor my company condone defrauding software >companies or their support operations, regardless of my grumbles about >dongles. Me neither! Tim Olmstead webmaster of the CP/M Unofficial web page email : timolmst@cyberramp.net MAIN SITE AT : http://cdl.uta.edu/cpm MIRROR AT : http://www.mathcs.emory.edu/~cfs/cpmArticle: 9653
"CodeLogic" (Digital & Software Design Services), provides a cost-effective outsourcing alternative for many aspects of your electronic and software product development: - FPGA and programmable logic design (VHDL) - Embedded and DSP firmware (C and Assembler) - Windows Test software and Apps (Delphi 3) - Technical Documentation & Tutorials (HTML, +other) For more details go to: http://home.intekom.co.za/codelogicArticle: 9654
Sam Falaki wrote: > > Good for Xilinx! > > They didn't even want to make me (little me) a measly > one-month loaner to at least evaluate their software. > I absolutely had to fork out a few $k if I wanted to > see how my designs would fit in their part. I now have > the Foundation kit limited to a useless 8k gates and even to > use that, I have to go through bureaucratic processes to > get authorisation codes (for 8k gates!). When will these > FPGA vendors finaly step out (like Actel) and provide > free software so users can easily compare between different > FPGA vendors (or maybe they are afraid of this?). And > guess what? Now that I am finaly ready to ship some protos, > which vendor will I use? Actel, and with their new MX series > devices I can make money in small production quantities and > ship them as stand-alone ASICs.! > > Sam Falaki > > David Pashley wrote: > > > In article <3519CE06.178C9C91@writeme.com>, Rick Collins > > <redsp@writeme.com> writes > > > > <suggestions of how to break Xilinx and Viewlogic security devices> > > > > How can you justify promoting the removal of security devices? Surely > > the resulting illegal copying of software (the use to which many would > > inevitably put this information) is against the interest of both the > > paying customers and those who make a living from providing and > > supporting the software? > > > > For me, and I would guess many other engineers in the EDA business who > > come here, the very existence of this thread is a sad occasion for the > > group. > > > > David Pashley Sam, You should call the Xilinx rep in your territory. They may be able to help you out with your delema.Article: 9655
David Pashley <david@fpga.demon.co.uk> wrote in article <LHjQJWA1F5G1MAMK@fpga.demon.co.uk>... : In article <3519CE06.178C9C91@writeme.com>, Rick Collins : <redsp@writeme.com> writes : : <suggestions of how to break Xilinx and Viewlogic security devices> : : How can you justify promoting the removal of security devices? Surely : the resulting illegal copying of software (the use to which many would : inevitably put this information) is against the interest of both the : paying customers and those who make a living from providing and : supporting the software? : : For me, and I would guess many other engineers in the EDA business who : come here, the very existence of this thread is a sad occasion for the : group. : : David Pashley rk: first, i do not promote the unlicensed use of software. that being said, there are some cases where 'breaking the dongle lock' may perhaps be justifiable, for the sake of argument. let's say, for instance, that when one upgrades a computer to a faster clock speed one can no longer run software cause the dongle reads fail. happenned to me and i became an unhappy customer. another instance may be when the newer printer drivers with another piece of software which talk back and forth to the printer aren't consistent with the dongle. and the dongle may be get damaged, printers don't work, and one gets headaches. turns out i get headaches and became an even less happy. so, what is one to do? get a bunch advil, perhaps, but that just says the headache will come back later. for problem #1, faster computer upgrade, which shut me down. i was fortunate that the cae vendor decided to remove the dongle from the security system, which was elimated. made everybody happy. do people steal their software? i would suppose so. but i don't. for problem #2, contention for parallel port, i had to switch to an older, stupider driver and run my machine that way. and now i'm stuck printing at 1/4 the resolution that the printer is capable of. unless i remove dongle, load new printer driver, bleah, bleah, bleah. can i perhaps get one printer driver somewhere that works printer at full spec and is compatible with cae software and won't burn things out? probably, but are YOU willing to pay me to figure out how to get all this fixed. i've wasted many, many hours on this nonsense and that is not a very good use of my time. perhaps the cae vendors should figure this stuff out and give out decent instructions and solutions to the problems they create. rkArticle: 9656
> > > > I'm afraid there's no official FAQ. No doubt one or two people who've > produced informative websites will post their addresses. > > However, in nearly five years in this group, I've never seen anyone > criticised for asking questions, so feel free to ask away. > > David > Thanks David, I'll do that. Ian.Article: 9657
In article <351813B4.9DE25395@computer.org>, Vitit Kantabutra <vkantabu@computer.org> wrote:
> Thanks. Yes, I've written a paper about it and submitted it to ICCD '98 a few
> days ago. I'll send you a copy via email. I just didn't want to send a paper
> to a newsgroup.
>
I'd also like to take a look at it. Please send it to me too.
Thanks,
--Andrew
Article: 9658
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Ian Stevenson wrote in message <01bd5913$d85769e0$3a9602c3@default>...
>Is there a FAQ for this group? I would be grateful if anyone can point me
>in the right direction.
>Cheers,
>Ian
>
>--
>--------------------------------------------------------------------------
>Spam block: Reply to
>ianstevenson@no-junk.saqnet.co.uk
>only remove the text 'no-junk'
>=====================================
Article: 9659You may find the Xilinx application note "Efficient Shift Registers, LFSR Counters, and Long Pseudo-Random Sequence Generators" useful. It's an Adobe Acrobat file available at http://www.xilinx.com/xapp/xapp052.pdf . ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Peixin Zhong wrote in message <351BCE2D.41C6@ee.princeton.edu>... >Hi, > >Does anyone know about implementing random number generator in FPGA? > >Thank you very much, > >Peixin ZhongArticle: 9660
rk wrote: > > > later. > > for problem #1, faster computer upgrade, which shut me down. i was > fortunate that the cae vendor decided to remove the dongle from the > security system, which was elimated. made everybody happy. do people > steal their software? i would suppose so. but i don't. > > for problem #2, contention for parallel port, i had to switch to an older, > stupider driver and run my machine that way. and now i'm stuck printing at > 1/4 the resolution that the printer is capable of. unless i remove dongle, > load new printer driver, bleah, bleah, bleah. can i perhaps get one > printer driver somewhere that works printer at full spec and is compatible > with cae software and won't burn things out? probably, but are YOU willing > to pay me to figure out how to get all this fixed. i've wasted many, many > hours on this nonsense and that is not a very good use of my time. perhaps > the cae vendors should figure this stuff out and give out decent > instructions and solutions to the problems they create. > > rk > I ran into the printer driver problem. My solution was to get one of those parallel port ISA cards. NOw I've got 3 parallel ports, one of which is dedicated to the keys. I've seen others use a port switch. Neither is elegant but they work. I'm not sure the new xilinx security (using the serial number of the Cdrive) is any better. One one hand, you don't tie up the parallel port and don't have keys to loose. On the other hand, I can't load the SW onto my laptop and take it with me anymore. Also, what happens when my drive gives up the ghost or I decide to trade up? -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka The Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs for digital signal processing, computing and control applications.Article: 9661
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Article: 9662Use Linear Recursive Sequence (LRS) generator. A program is available from our website which displays different sequences and correlates them against one another. You can download the manual which contains an article explaining the details of using shift registers to generate the sequences. Portions of it appeared in an RF Design article --as LRSs are used in Direct Sequence Spread Spectrum , wireless communications, as spreading codes. Basically they are shift register chains with feedback taps which (if taps are selected properly) have a repeat length of (2^n)-1, such that all possible numbers --except an all zeros condition-- are pseudo randomly cycled through. For example using 4 registers you can generate (2^4)-1 or 15 numbers (1-15) in random order. I think the X84 board downloadable labs also have a VHDL example of implementing an LRS generator with programmable tap lenght and fills. Both can be downloaded from : http://www.associatedpro.com/aps Peixin Zhong wrote: > Hi, > > Does anyone know about implementing random number generator in FPGA? > > Thank you very much, > > Peixin Zhong -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com 3003 Latrobe Court richard@associatedpro.com Abingdon, Maryland 21009 Phone: 410.569.5897 Fax:410.661.2760 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 9663
Hi I'm trying to use ISP Synario Starter which I downloaded from lattice. When I try to fit the design I get a message: Updating: Fitter Report Starting: 'L:\ISPSYN50\SYNDPM.EXE -i tach.tt2 -if pla -p ispLSI1016-90LJ44' Received process exit status -1 Possible system problem to spawn child process Done: failed with exit code: -001. The readme file states that there must be some environment variables be set for syndpm to run. Does anybody know the names and values of those variables? May there be other reasons for syndpm not to run? Thank Yuo very much, beniArticle: 9664
In article <351be40a.20946229@news.netcomuk.co.uk>, Peter <z80@ds2.com> writes > >>There you go again. Where did I talk about "promoting illegal use"? > >Here's your text: > >How can you justify promoting the removal of security devices? Surely >the resulting illegal copying of software (the use to which many would >inevitably put this information) is against the interest of both the >paying customers and those who make a living from providing and >supporting the software? > Exactly. I talk about "promoting the removal of security devices", which, as everyone (including me) has said is definitely not the same thing as "promoting illegal use". You imply that I accuse the original posters of dishonest motives, when in fact I said that dishonest activity - by others - could result from their actions. The distinction is important. DavidArticle: 9665
Paul Walker wrote in article ...
>In article <3515B9E9.3D4B2192@xilinx.com>, Peter Alfke
><peter.alfke@xilinx.com> writes
>>Dual-port memories are ideal
>>for implementing FIFOs and communications mailboxes between asynchromous
>>systems.
>
>Yes.
>
>But can anyone explain why some of Xilinx competitors provide genuine
>dual-port RAM and then insist that both ports are clocked by the same
>clock?
>
>Yet these same chips provide for multiple clocks and so are presumably
>intended for asynchronous systems.
...snip..
>
>Does anyone know of any others that allow dual-port, dual clock access,
>to a reasonable number of separate memories per chip?
>
Atmel's NEW AT40K FPGAs have just what you are looking for in dual-port,
dual clock access, fast SRAM. We call it FreeRAM(tm) because you don't lose
core cells when you use the RAM. Each RAM block is 32X4 and was designed for
high speed FIFOs based applications. For more info. on AT40K FPGAs or to
register for FREE IDS5.0 FPGA software
http://www.atmel.com/fpga_software.html
Martin Mason
Atmel Corp.
Article: 9666z80@ds2.com (Peter) wrote: :Some of these belong to programs "no longer supported", and if such a :dongle breaks, the investment in that program goes down the plughole. :Don't forget - one has a right to use a piece of s/w without a time :limit. My investment in such "no longer supported" software is well :over $10k, and when Xilinx stop supporting the XACT6 dongle this :figure would have increased by another $4k. Not to mention the growing tendency to incorporate a time-lock in the dongle (or its software). Many CAE packages are now sold for, say $9K, with a $1500 annual maintenance fee (real figures, from one major vendor). The dongle disables itself on a set date, & I have to purchase a new licence to re-activate it. Now that sucks, for two reasons: 1. I may choose to go un-maintained, and accept the implications (no support, no updates or bug fixes). 2. Some day, the vendor will decide to stop supporting that product, & my investment is a total loss. If they intend to RENT us the software, then let them say so, and charge us a rental price, not a purchase. Also the (all too common) license clause that prohibits transferring the license to any other person. If I have purchased an item, it's MINE. Mine, to sell to another if I choose. As before, if they mean to rent it, let's pay rental, not purchase. A further gripe is the replacement policy. The vendors blandly state they will replace a damaged (& returned) dongle, but not a lost or stolen one. We are simply advised to insure the dongle to the full price of the software. My insurance agent all-but refused outright to look at the proposal. He asked what the dongle itself was worth: I hazarded $30. "That's all we can cover it for".Article: 9667
Hi, We have an opportunity for an individual who has done some complex Circuit Board/FPGA design to work at a place where cutting edge technology is the norm, and one of the very best design staffs in the country awaits. This position is for someone who has between 3-10 years of high performance custom circuit design under his/her belt. You will be working on some of the "neatest" projects you've ever seen, and will become a stellar hardware designer for your efforts. Some of the "buzz": We are looking for High Speed Digital Designers, having some experience with PLD's, FPGA's (ASICS), complex designs (nothing simple at this place), understands timings, etc... Not a person who still needs a lot of instruction, we are hoping to find an individual who can stand alone and bring a project in from scratch to production. This is a great company! Our guarantee is this: If you go in and chat with these people, you WILL want to work there, especially if you can do this type of work. They are located on the North side of Chicago, near Skokie or Evanston, just off the Kennedy. Salary will be very nice, they're not cheap, as they're looking for the best we can bring in. Please E-mail or Fax us at: Hunter International E-mail: cleaner@starnetinc.com Fax: (815)356-9225 Thanks, Dave...Article: 9668
Peter wrote: > > Hello, > > There are two speeds in USB: 1.5mbit/sec and 12 mbit/sec. <snip> > I want to make a USB peripheral device, not a hub. The FPGA would be > talking to a fast and cheap 8/16-bit CPU with DMA, e.g. a Z180. Look at the Siemens C541 / C452 USB chips, these are OTP, with a C51 core included, and do both 12 / 1,5MHz rates. If you were going to bolt a small uC next to it anyway, this would make more sense.. ( What I want is a USB _HOST_ device, that us uC connectable... ) - jim granville. -- ======= Manufacturers of Serious Design Tools for uC and PLD ========= = Specialists in Development tools for C51 cored controllers = Leaders in Rapid Application Development SW for C51 uC = Ask for our Controller & Tools selector Guides = mailto:DesignTools@xtra.co.nz Subject : Selc51ToolsArticle: 9669
This information looks very helpful. Thanks. Ian. Steven K. Knapp <sknapp@optimagic.com> wrote in article <6fjgkh$12d@dfw-ixnews10.ix.netcom.com>... > While there's no official FAQ for this group, you may find the FAQ on The > Programmable Logic Jump Station useful at http://www.optimagic.com/faq.html. > > In general, The Programmable Logic Jump Station is a comprehensive set of > links to nearly all matters related to programmable logic. > > Featuring: > --------- > > --- FPGAs, CPLDs, FPICs, etc. ---Article: 9670
In article <6fmih9$67t@dfw-ixnews8.ix.netcom.com>, Martin Mason <mtmason@ix.netcom.com> writes > Atmel's NEW AT40K FPGAs have just what you are looking for in dual-port, >dual clock access, fast SRAM. In which case the data sheet had me completely mistaken. Your text does indeed say that read is totally asynchronous. The figure on Page 10 of the data sheet shows a single clock going into several latches and into the array. The figure on page 11 shows a completely asynchronous RAM. If one of your major selling points is to use separate clocks, it would be nice to see a figure showing their use. Another problem with the RAMs is that they are four-bits wide, which means three are needed for a "byte" of nine bits, but there are enough RAMs on each chip that this is not too serious. Thanks for pointing out that the new ATMEL are suitable. In other respects they looked quite appropriate, and are now even more so. Paul -- Paul Walker 4Links phone/fax paul@walker.demon.co.uk P O Box 816, Two Mile Ash +44 1908 http://www.walker.demon.co.uk Milton Keynes MK8 8NS, UK 566253Article: 9671
On Sat, 28 Mar 1998 16:17:30 -0500, Ray Andraka <no_spam_randraka@ids.net> wrote: >I'm not sure the new xilinx security (using the serial number of the >Cdrive) is any better. One one hand, you don't tie up the parallel port >and don't have keys to loose. On the other hand, I can't load the SW >onto my laptop and take it with me anymore. if you ask them nicely they may let you have a licence file for your portable. they did for me, anyway. evan (ems@nospam.riverside-machines.com)Article: 9672
You could also try TextPad (www.textpad.com). This is a really neat
shareware text editor for Windows. As far as I'm aware there is no
specific support for VHDL but there is a "Clip Library" capability
that would let you build your own as you go along (for instance free
libraries already exist for HTML, Visual Basic, PERL, Clipper,
JavaScript, etc
--
Regards
Mark
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Vulcan ASIC Ltd - The ASIC and EDA Solution Company
Tel: +44 (0)1763 248163 Fax +44 (0)1763 241291
--- www.vulcanasic.com ---
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Article: 9673Esperan specialize in supplying independent, application orientated VHDL and Verilog based training and have very close relationships with most of the main EDA and FPGA vendors such as Synopsys, Mentor, Viewlogic and Xilinx, our courses are recommended or re-sold by many of them. Due to our rapid expansion in the provision of VHDL and Verilog training services in the US and Europe. We are actively seeking to recruit consultants as trainers to out source the delivery of the training courses to, on a week by week basis. In addition to the obvious financial benefits our experience with other consultants has shown that delivering the training courses provides an excellent opportunity for the consultant to market their own, and their organizations expertise to potential customers. Primarily we want to to talk with Designers/Consultants who have: * Real world experience of VHDL and/or Verilog based design using synthesis. Use of FPGAs would be a distinct advantage. * Good communication skills and the ability to explain complex topics in a clear, concise manner. * Availability for periods of up to one week for between four and ten weeks per year. * A willingness to travel. We own and develop all the training material, but subcontract the delivery to consultants. All the logistics of the courses, such as marketing, software licenses, training materials, presentation materials etc. are managed by Esperan. If you could answer the following questions to give me a summary of your experience to date I shall be in touch. How many years experience of VHDL/Verilog? What real design experience have you had? Does it include Synthesis? How many ASIC's or FPGA's have you synthesized? What experience of testbench design have you had? What design tools have you used? What would your availability be during the year for training (ie. 6 five day course )? When would you be available to start? Please send me an up to date resume'. Many Thanks Simon Moreton (Training Manager).Article: 9674
******************************************************************************
ISSS'98 FINAL CALL FOR PAPERS
11th INTERNATIONAL SYMPOSIUM ON SYSTEM SYNTHESIS
Hsinchu, Taiwan, R.O.C., December 2-4, 1998
******************************************************************************
IMPORTANT NEWS:
Upon to many requests the paper submission dead-line will be
postponed
to 4/13.
******************************************************************************
ISSS'98 is the 11th in a very successful series of symposia oriented
towards design automation professionals. At the symposium the latest
results in emerging system design and synthesis technologies are
presented.
Original technical papers on, but not limited to, the following topics
are invited:
System-level synthesis: Partitioning, transformations, design reuse,
quality measure, estimation, specification languages and models,
intermediate forms, embedded processor synthesis.
Hardware-software co-design: Hardware/software tradeoffs, interfaces
and communications, co-simulation, co-emulation and co-synthesis,
embedded system architectures, system exploration, system testbench
development, design automation for rapid system prototyping.
Programmable (multi-) processor-based design and synthesis: ASIPs, code
generation, instruction-set specification, design and simulation,
high-level code transformations.
System design experience and methodologies: Application-specific
parallel/distributed systems, industrial telecom, robotics, vision,
video, audio and speech processing systems, formalized design
methodology, process management.
Embedded and real-time system software: Software development, constraint
specification, process scheduling, real-time operating systems,
distributed systems.
High-level and architectural synthesis: Datapath, control, memory, and
interface synthesis from behavioral specifications, clocking/timing
optimization, physical design models for high-level tradeoffs,
hardware accelerators/coprocessors.
Synthesis for low power, testability and verifiability in the above areas.
---------------------------------------------------------------------------
Submitted papers should be 6 pages or less in IEEE 2-column style (10pt),
as close as possible to the final content. They should clearly specify
contributions and results, and include a separate cover page with the
following: paper title, complete name, address, telephone, fax, and email
address of each author, identification of the corresponding author, and
the
category (numbered 1-7 above) most closely matching the paper's content.
Papers exceeding the page limit will be returned to the authors.
Submissions
simultaneously sent to other forums will not be considered. The symposium
proceedings will be published by the IEEE Computer Society Press.
Everyone is strongly encouraged to submit the paper and cover page
electronically as explained on our web page
(http://www.cs.nthu.edu.tw/~isss98/ under the "Call for papers/submission
instructions"). If you do not have access to a web browser you may also
send the uuencoded gzipped (standard) Postscript paper and separate cover
page (in ASCII format) to the email address ``isss98@cs.nthu.edu.tw''.
If electronic submission is infeasible, 8 copies of the paper should be
send along with the cover page to the Program Chair at the following
address:
Allen C.-H. Wu, ISSS'98
Computer Science Department
Tsing Hua University
Hsinchu, Taiwan 30043
Tel: 886-3-5715131 ext 3517
Fax: 886-3-5723694
Email: chunghaw@cs.nthu.edu.tw, isss98@cs.nthu.edu.tw
===========================================================================
Author's schedule:
Submission deadline: April 13, 1998
Notification of Acceptance: June 5, 1998
Camera-ready copies: July 5, 1998
============================================================================
Steering Committee:
General Chair: Francky Catthoor, IMEC
Honorary Chair: C. L. Liu, Tsing Hua University
Program Chair: Allen C.-H. Wu, Tsing Hua University
Publications Chair: Liang-Gee Chen. Taiwan University
Panels Chair: Nikil Dutt, University of California, Irvine
Publicity Co-Chairs: Jyuo-Min Shyu, Industrial Technology Research
Institute
Ing-Jer Huang, Sun Yat-Sen University
Finance Chair: Wen-Zen Shen, Chiao Tung University
Local Arrangement Chair Steve Y.-L. Lin, Tsing Hua University
Past Chair: Frank Vahid, University of California, Riverside
============================================================================
Technical program committee:
Marleen Ade, K.U. Leuven
Gaetano Borriello, Univ. Washington
Raul Camposano, Synopsys
Nikil Dutt, U.C. Irvine
Rolf Ernst, Tech. Univ. Braunschweig
Masahiro Fujita, Fujitsu
Daniel Gajski, U.C. Irvine
Cathy Gebotys, Univ. Waterloo
Yu-Chin Hsu, Avant!
Ahmed A. Jerraya, TIMA
Kayhan Kucukcakar, Motorola
Fadi Kurdahi, U.C. Irvine
Steve Y.L. Lin, Tsing Hua Univ.
Paul Lippens, Philips
Jan Madsen, Tech. Univ. Denmark
Lev Markov, Mentor Graphics
Peter Marwedel, Univ. Dortmund
Vijay Nagasamy, VSIS Inc.
Yukihiro Nakamura, Kyoto Univ.
Sanjiv Narayan, Ambit Design Systems
Kevin O'brien, Leda
B. Ramakrishna (Bob) Rau, HP Labs.
Wolfgang Rosenstiel, Univ. Tubingen, FZI
Edwin Sha, Univ. Notre Dame
Leon Stok, IBM
Donald Thomas, CMU
Diederik Verkest, IMEC
Kazutoshi Wakabayashi, NEC
Robert Walker, Kent State Univ.
Wayne Wolf, Princeton
Hiroto Yasuura, Kyushu Univ.
******************************************************************************
Check the WWW at ``http://www.cs.nthu.edu.tw/~isss98/'' for the latest
ISSS'98 related information.
Sponsored by
IEEE CS Technical Commitee on Design Automation (approval pending)
and
ACM SIGDA (approval pending).
In Cooperation with
Ministry of Education, R.O.C.(approval pending) and
National Science Council, R.O.C.(approval pending).
******************************************************************************
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