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Hi folks, We're selling an Altera MAX+Plus II package, (unused and still sealed). It's the full "Magnum" version including VHDL support, manual, CD-ROM, hardware dongle, maintainance (upgrades and tech support) and registration card. It cost over $7000 but we're seeking the highest offer. This is a good opportunity for a potential designer who's budget conscious. Thanks, - Chris cook2001@hotmail.com -- ------------------------------------------------------------------- Note: when replying, please remove the "_" prefix from the address.Article: 10076
Hi, I am working on an XC4025E FPGA with Synopsys (UNIX version). I would like to write some data in a SRAM at each edge of my clock, and for this I must delayed my Write Enable signal from 4 or 5 ns? Could you give me some ideas to introduce a delay in Xilinx FPGA? Is it possible to use a clock buffer (BUFGS) on my Write Enable signal to do this? I need your help... Thanks!Article: 10077
Antoine Lecerf wrote: > > Hi, > > I am working on an XC4025E FPGA with Synopsys (UNIX version). > > I would like to write some data in a SRAM at each edge of my clock, and > for this I must delayed my Write Enable signal from 4 or 5 ns? > > Could you give me some ideas to introduce a delay in Xilinx FPGA? > Is it possible to use a clock buffer (BUFGS) on my Write Enable signal > to do this? > > I need your help... > > Thanks! If you use the XC4000 RAMs in synchronous mode, and all input interface signals come from flip-flops, it should work just fine without special delay elements: the flip-flop delays should be sufficient to cover the data and write-enable hold time, which is probably around 0 ns. Regards, Jan -- =================================================================== Jan Decaluwe === Easics === Design Manager === VHDL-based ASIC design services === Tel: +32-16-395 600 =================================== Fax: +32-16-395 619 Interleuvenlaan 86, B-3001 Leuven, BELGIUM mailto:jand@easics.be http://www.easics.comArticle: 10078
I would say that you are barking up the wrong tree. I assume you are trying to write to an external async SRAM in a single clock cycle. This is not something that anyone will recommend unless you can use external logic to generate a gating signal. You should never try to generate a quantifiable delay inside of an FPGA. The specs on the part are not that well defined. For example, you said you wanted about 4 ns. Xilinx says the minimum delay should be estimated at 25% of the maximum delay (and even this is not guaranteed). So to be confident that you will get 4 ns over the range of all variables, you would need to design in a delay of 16 ns. If you can tolerate this much maximum delay, your design might work. But you can see the problem. It would be much better to either generate the timing signals to the SRAM in external components that are built to give known time delays. Or you could use a synchronous SRAM. Or use a two up clock and generate the signals synchronously. Rick Collins Antoine Lecerf wrote: > > Hi, > > I am working on an XC4025E FPGA with Synopsys (UNIX version). > > I would like to write some data in a SRAM at each edge of my clock, and > for this I must delayed my Write Enable signal from 4 or 5 ns? > > Could you give me some ideas to introduce a delay in Xilinx FPGA? > Is it possible to use a clock buffer (BUFGS) on my Write Enable signal > to do this? > > I need your help... > > Thanks! -- Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 10079
> > So why not have several "flavor" of CLB's? There are certainly enough > > models of FPGA's out there to support that. > Because there is such a thing as lawsuits and intellectual property. > > Scott Taylor - DSP Fibre Channel Systems What do you mean? I don't understand. Yes, of course, there are such things are law suits and intellectual property. But that doesn't mean that Xilinx can't either come up with their own different "flavors" of CLBs, or pay someone else for a license. Plus, being a patented inventor myself, I don't see small variations on CLB architecture as patentable.Article: 10080
This sort of thing, unless it can be avoided altogether by design, is best done by *externally* generating a delayed version of your main clock (e.g. RC delay and a schmitt buffer) and feeding it in. >I would like to write some data in a SRAM at each edge of my clock, and >for this I must delayed my Write Enable signal from 4 or 5 ns? > >Could you give me some ideas to introduce a delay in Xilinx FPGA? >Is it possible to use a clock buffer (BUFGS) on my Write Enable signal >to do this? Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 10081
APS has prototyping tips and hints as well as an on line VHDL tutorial located on its website. APS has FPGA Test boards available for XILINX LUCENT and ATMEL FPGAs with associated low cost software including VHDL, VERILOG, and Router options. APS also sells several other engineering support tools, as well as some of the lowest prices on FPGA software tools including the XILINX Foundation Series Software. You can see the tools as well as the VHDL tutorial and EDA Newsletters at:: http://www.associatedpro.com http://www.associatedpro.com/aps_sup.html http://www.associatedpro.com/aps_newsletter.com -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com 3003 Latrobe Court richard@associatedpro.com Abingdon, Maryland 21009 Phone: 410.569.5897 Fax:410.661.2760 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 10082
I am doing some research on fault tolerance using FPGAs. For this research, I need to find out what are the different kinds of faults that occur in FPGAs, and their causes, frequencies etc. Where can I find this information? Thanks, Sunondo GhoshArticle: 10083
Antoine Lecerf wrote: > Hi, > > I am working on an XC4025E FPGA with Synopsys (UNIX version). > > I would like to write some data in a SRAM at each edge of my clock, and > for this I must delayed my Write Enable signal from 4 or 5 ns? > > Could you give me some ideas to introduce a delay in Xilinx FPGA? > Is it possible to use a clock buffer (BUFGS) on my Write Enable signal > to do this? > > I need your help... > > Thanks! Thank you very much to all of those who answered my question. I give you more details about my problem. My SRAM is an 512k8 extern asychronous SRAM and my FPGA is a XC4025E-2. At each front edge of my clock, I put the adress and data but also my Write Enable signal. I disable my Write Enable signal on the back edge of my clock. But to write data inside the SRAM, I must wait a stable address, and that's why I need to introduce a delay (between 4 and 30 ns) to my Write Enable signal. I know that it's better to introduce a delay with some extern components. But in our case, for many reasons we prefer to introduce this delay inside the FPGA. My addresses are calculate on clock before that I put them outside the FPGA. To introduce my delay, I probably have two possibilities but I'm bot sure: 1) I can configure my address outputs with a fast slew rate and my Write Enable signal with a slow slew rate. ---> The delay wil be probably too short. 2) I can use a clock buffer (BUFGS) on my Write Enable signal to introduce this delay. Give me yours ideas, please... Thanks! AntoineArticle: 10084
William Jones wrote: > > Hello, > I was wondering if there are any 'good' high-level language to > hardware compiler's in existence. > > Bill J. If you really wants to know what is up in this field, look at http://www.compilogic.com They presented a very powerfull C2Verilog-compiler on FCCM'98. They could even handle pointers(!) without any problems. See you, HagenArticle: 10085
APS has prototyping tips and hints as well as an on line VHDL tutorial located on its website. You can see the tools as well as the VHDL tutorial and EDA Newsletters at:: http://www.associatedpro.com http://www.associatedpro.com/aps_sup.html http://www.associatedpro.com/aps_newsletter.html -Article: 10086
John, You can usually get a fast response if you send your problem to Altera technical support at sos@altera.com. In any case, I have seen this problem before. I guess you are using Max+Plus II version 7.2? If so, you need to download a patch (or the latest programming software). Check out http://www.altera.com/html/products/7_2pch1.html Ying ying@csua.berkeley.edu In article <353F9085.1156C0A4@tpts4.seed.net.tw> you write: >Hi all: > I've use altera 10K20 (240 pin) in my design, > but when I use the BYTEBlaster to download the >sof file, I found the fpga didn't work, all I/O pins >are present high or Hi-Z, I'm sure the download >procedure was successful, the MaxPlus II tell me >it work fine, and I had see the all signal is work when >download(Status, DCLK, D0, Conf, CONF_DONE) >and CE, MSEL0, MSEL1 is connected with ground, >why the chip don't work, please someone help me >thanks > > John Huang >Article: 10087
Antoine Lecerf wrote: > > My SRAM is an 512k8 extern asychronous SRAM and my FPGA is a > XC4025E-2. > At each front edge of my clock, I put the adress and data but > also my Write Enable signal. I disable my Write Enable signal on the back > edge > of my clock. > But to write data inside the SRAM, I must wait a stable address, and > that's why > I need to introduce a delay (between 4 and 30 ns) to my Write Enable > signal. > > I know that it's better to introduce a delay with some extern components. > But in > our case, for many reasons we prefer to introduce this delay inside the > FPGA. > > My addresses are calculate on clock before that I put them outside the > FPGA. > > To introduce my delay, I probably have two possibilities but I'm bot sure: > > 1) I can configure my address outputs with a fast slew rate and my Write > Enable signal with a slow slew rate. > ---> The delay wil be probably too short. > > 2) I can use a clock buffer (BUFGS) on my Write Enable signal to introduce > > this delay. > > Give me yours ideas, please... > > Thanks! > Antoine -- What you are trying to do is very clear. We are trying to tell you that what you want to do is not a good idea and most likely won't work. If you give me an idea of the timing data, I could tell you a little better if it will work or not. What is your clock freq? What is the write enable min time for the SRAM? What is the setup time for the address and data for the SRAM? As I said in an earlier post, I tried to do what you are describing, writing to an external async SRAM in a single clock cycle. If the clock cycle is anywhere near the cycle time of the SRAM, you won't be able to do it without violating spec'd timing requirements. It may work, it may work over temp and voltage. But Xilinx won't guarantee it to work. No one specs their parts with tight minimum delays and it is the minimum delay that you will need to depend on, not the maximum. But with some timing data, I can tell you if it is feasible. Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 10088
Antoine Lecerf wrote: > > Antoine Lecerf wrote: > > > Hi, > > > > I am working on an XC4025E FPGA with Synopsys (UNIX version). ... > My SRAM is an 512k8 extern asychronous SRAM and my FPGA is a > XC4025E-2. >... Use a 2x clock. If the 2x and 1x clocks are generated externally and are applied to the FPGA through separate pins, you will need to be careful about clock skew when you cross clock domains, but it is not all that complicated (this avoids having to clock the entire design at the 2x clock). You can pull off interleaved read/write to random addresses at better than 40 MHz (25ns read cycle, 25ns write cycle) in a 4025E-2 part and 12ns external SRAM if you are careful. The Address, data and controls need to be registered by the 2x clock in the IOBs using the FAST (all outputs) and NODELAY (data inputs) attributes. THe controls and address/data should be clocked on the opposite edges of the 2x clock. You will need to instantiate at the CLB level to do it in Synopsis. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka The Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs for digital signal processing, computing and control applications.Article: 10089
On Sat, 25 Apr 1998 22:42:39 GMT, Antoine Lecerf <lecerf00@gel.ulaval.ca> wrote: >Hi, > >I am working on an XC4025E FPGA with Synopsys (UNIX version). > >I would like to write some data in a SRAM at each edge of my clock, and >for this I must delayed my Write Enable signal from 4 or 5 ns? > >Could you give me some ideas to introduce a delay in Xilinx FPGA? >Is it possible to use a clock buffer (BUFGS) on my Write Enable signal >to do this? I have read all the other replies to this, but when you are real, real desperate, two invertors in series with an "X" attribute on the net in between might work. Floorplan it and it's a little bit better. Delay 5-150 nsec -- varies from compile to compile. Tends to be a bit lower than that in reality. Much better to find a sychronous way to do it. Most RAM actually doesn't mind long WR signals -- I am driving the same RAM and I have more problems with hold than with setup. In my case I have a 2X clock, but have used fast WR and slow ADDR and DATA buffers to control the hold time.. -- Gavin Melville gavin@cypher.co.nzArticle: 10090
Hello.
I am using FLEX10K100 from Altera for a prototyping
board.
While designing the board, I am wondering which I/O pins I should select
for the external I/O. I mean I would like to place two FIFOs and memory
controller on the FLEX10K100 and fix the I/O pins on PCB like the
following.
While the memory controller and FIFOs are fixed, blocks are variable
depending on some application.
|||||||
---------------------------------------------
| |memory controller| |
| ----------------- |
| | |
I/O --|------- ------- ------- ------ ------|-- I/O
--|FIFO |-|block1|-|block2|-..|block3|--|FIFO||--
--|------ ------- ------- ------ ------|--
| |
|____________________________________________|
I think the placement and routing of later designed blocks are dependent
on the glue logics.
Can you give me any advice for selecting I/O pins for external interface
logic?
Article: 10091Someone made a suggestion that, I believe, was on the right track, most others, I believe, were a bit to analytical and complicated (just my opinion guys ;-). If I understand correctly what you want to do, and there are no other 'implications' then you can route the signal through a CLB. As was suggested, the delay characteristics of these elements are not so 'quantifiable' ...BUT.... they track. What I mean by this is all delays will be at a some % +- from each other NOT one at max and one min. So, if all delays are say +-10% (which is a reasonable thing to assume) relative to each other you can calculate how much of a delay you need. Say you needed a minimum minimum 2ns setup and a maximum minimum of 5ns. Say a CLB has a min 1.5ns max 4.5ns (plus extra routing) I believe you would be fine. Remember, XACT timing is MAX, and so is simulation timing derived from XACT information. Understanding what makes up the variations in delays is important too in order to create accurate internal delays. One example is the more pips on a route, the more effected it is by temp/voltage. I could write volumes about this, but that would probably confuse a simple answer. Let me know if you want more information, or if this is enough to get you started in the right direction. Just as a note, for the internal Asynch SRAM, you can gate the WE with the inverted clock, or possibly even a delayed clock and still make all timing...if you are very carefull with placement, routing and doing your timing calculations. Remember timing tracks... Austin Franklin darkroom@ix.netcom.com Antoine Lecerf <lecerf00@gel.ulaval.ca> wrote in article <3542672B.94B2B0B5@gel.ulaval.ca>... > Hi, > > I am working on an XC4025E FPGA with Synopsys (UNIX version). > > I would like to write some data in a SRAM at each edge of my clock, and > for this I must delayed my Write Enable signal from 4 or 5 ns? > > Could you give me some ideas to introduce a delay in Xilinx FPGA? > Is it possible to use a clock buffer (BUFGS) on my Write Enable signal > to do this? > > I need your help... > > Thanks! > > >Article: 10092
In article <3542DE8E.37B9@isu.edu>, kantviti@isu.edu wrote: > > > > So why not have several "flavor" of CLB's? There are certainly enough > > > models of FPGA's out there to support that. > > Because there is such a thing as lawsuits and intellectual property. > > > > Scott Taylor - DSP Fibre Channel Systems > > What do you mean? I don't understand. Yes, of course, there are such > things are law suits and intellectual property. But that doesn't mean > that Xilinx can't either come up with their own different "flavors" of > CLBs, or pay someone else for a license. Plus, being a patented > inventor myself, I don't see small variations on CLB architecture as > patentable. > You assume that the owners are willing to license, at any reasonable price, or at all. Xilinx bought someone a while back, Quicklogic? Altera bought Intels programmable logic. I suspect both were to get rights to logic cell configurations. There have been some other purchases along those lines also, but my memory is fuzzy just now. Atmel seems to willing in this area. They have some Altera "supersets" for the 7032 and 7128 (EPLDs rather than FPGAs). I was not real impressed by ABEL when I used the AT1500 (7032 equivalent), though I did find Atmel helpful. By the way, if you use a third party programmer, Atmel has a serial EEPROM (instead of EPROM), AT17C128. Being able to re-use them can save big bucks during debugging. One of our customers says he typically uses 100 pieces during new product debugging. He could buy a third party programmer for what he would save the first time. I use the Atmel serial prom for Altera Flex parts from 8636 and down. Atmel might have a bigger one by now. There is a conversion utility from Atmel called AT2ALT on their web site. It adds 9 bits of 1 to the front of the file. That and the reset polarity is the difference (Atmel and Xilinx parts have programmable poloarity). The conversion utility will also allow Xilinx serial proms to be used on [8000 series] Altera FPGAs. I originally wrote a kludge version in BASIC, but Martin Mason had it re-done in something high level with a nice easy to use interface. at2alt input_file.ext output_file.ext I try to use ISP now, but the Atmel serial proms are useful when changes are likely. Scott Taylor - DSP Fibre Channel Systems -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 10093
In article <3543C81E.3FD55C3C@yahoo.com>, Rickman <spamgoeshere1@yahoo.com> wrote: > > No one specs their parts with tight minimum delays and it is the minimum > delay that you will need to depend on, not the maximum. > As an unrelated aside, one of our customers claims Lattice does on their EPLDs. The customer relies on that delay and it seems to work. I personally would rather not, but it is not my design. Scott Taylor - DSP Fibre Channel Systems -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 10094
This situation is not so easy for synchronous rams either. It sure would be
nice if the next generation of FPGAs would fix this problem by providing
"clock output pads" which give a guarenteed (and controllable) relationship
between the output clock and any clocked pads which use the same clock.
They also need a final gate for this case of generating the WE signal for
asynchronous SRAMs. But given that this is not yet available:
In article <354386EE.59E0A319@gel.ulaval.ca>,
Antoine Lecerf <lecerf00@gel.ulaval.ca> wrote:
>My SRAM is a 512k8 extern asychronous SRAM and my FPGA is a XC4025E-2. At
>each front edge of my clock, I put the adress and data but also my Write
>Enable signal. I disable my Write Enable signal on the back edge of my
>clock. But to write data inside the SRAM, I must wait a stable address, and
>that's why I need to introduce a delay (between 4 and 30 ns) to my Write
>Enable signal.
So you're saying that you are now using:
address_out=address@clk
data_out=data@clk
we_n=~((write_gate@clk)&clk)
(where @ is a D-flip-flop).
First off, this situation is glitchy: If the write_gate was high on the
previous cycle you'll get a glitch on we_n at the rising clock edge since
that will arrive at the nand-gate before (write_gate@clk). So you really
want to have a delayed clock for generating we_n:
we_n=~((write_gate@clk)&dclk)
(you could also use the inverted clock: we_n=~((write_gate@clk)&~clk); this
fixes the glitch but gives you a hold time problem with the ram instead).
Getting a delayed clock is pretty easy since the XC4025 has so many global
extra clock buffers. For example: dclk=bufg(~bufg(~clk)) (I.E., two
inverters and two clock nets: I'm guessing your synthesis tool won't
optimize out explicit bufg()s. Another way is to feed the main clock out
through a pad and back into the chip through another pad. This is good
because you can then use an external network to control the delay if you
need to.
As a safety check I would look at the timing of the signals with a scope and
a can of freeze-it, just to make sure I'm not near the edge.
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 10095Ying C. <ying@soda.CSUA.Berkeley.EDU> 次寫入到主題 <6i0e0f$afb$1@agate.berkeley.edu>... > > > John, > > You can usually get a fast response if you send your problem to Altera > technical support at sos@altera.com. > > In any case, I have seen this problem before. I guess you are using > Max+Plus II version 7.2? If so, you need to download a patch (or the > latest programming software). > > Check out http://www.altera.com/html/products/7_2pch1.html Thanks, Ying Are you chinese? The FAE of Altera has tell me this bug of their software, and I have downloaded the patch file, thank you tell me this. The maxplus II is too expensive, My version is student edition, the altera sales give me this version , I've purchased Cypress WarpIII, Xilinx's software, but I don't want to purchase MaxPlus II, I spend too much money buy tools, I prefer to buy LA or DSO rather than other tools, Anyway, Thanks a lot with your help! John HuangArticle: 10096
Look at MAX7000E device. Koichi SuzukiArticle: 10097
Hi John Check VCC-INT and VCC-IO and GND. Koichi SuzukiArticle: 10098
>I have read all the other replies to this, but when you are real, real >desperate, two invertors in series with an "X" attribute on the net in >between might work. Floorplan it and it's a little bit better. >Delay 5-150 nsec -- varies from compile to compile. Tends to be a >bit lower than that in reality. While we are discussing bodges (:)) I would prefer to bring out the signal to be delayed to a pin, and bring it back in via another pin. Then, connect an RC delay between the two pins. If the delay is really short, say 5-10ns, there should not be any need for a schmitt trigger. Although one could achieve that too, using a bit of positive feedback (via a resistor) from a 3rd pin which is a buffered version of the input pin. So, with 2 or 3 pins, you can have a nice predictable delay. Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 10099
Antoine Lecerf <lecerf00@gel.ulaval.ca> wrote:
>
>I would like to write some data in a SRAM at each edge of my clock, and
>for this I must delayed my Write Enable signal from 4 or 5 ns?
>
>Could you give me some ideas to introduce a delay in Xilinx FPGA?
>Is it possible to use a clock buffer (BUFGS) on my Write Enable signal
>to do this?
>
I'm not sure how to reliable insert a specific delay into an FPGA.
Maybe another trick might help in your case: you might be able to
achieve the desired timing by combining your write signal with the
clock in an OR-gate:
______ ______
--| |---write_l----| OR |----- WE_L
| FF | | |
+-|c | +-----| |
| ------ | -------
| |
clock -----------------+
write_l _____: :__________:___
\_________/ :
: : :
clock :____ :_____ :___
_____| |____| |____|
: : :
WE_L _____:____ :__________:___
: \____/ :
: : :
This way your write signal is low only in the second half of your
clock cycle. Would this solve the problem in your case?
The timing of your write signal would depend on the duty cycle of the
clock and the output delay of the signal.
Hope it helps
Stefan
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