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> > My main interest is in techniques for voltage conversion. I've heard of > > designs which use small DC-DC converters distributed across the board to > > provide ample current at 3.3V. Any experience or suggestions with this? > > Any suggestions on which DC-DCs to use? > > The motherboard industry seems to be standardizing on programmable > converters for generating CPU core voltages. PowerTrends, for example will > offer a converter that can generate 1.3V to 3.5V at 32 amps with 90% > efficiency in a fairly small plug-in package. I believe PowerTrends 'trends' are towards $$$$$$$$$$$. My clients need to make more money on the products than the vendor of the DC/DC converter ;-) They are nice products though... AustinArticle: 10226
Often the use of a DC/DC converter only makes sense depending on the load. If you are making any type of analog measurement, Dc/dc often causes noise that can couple to the i/o. FWIW - radio gear often uses lots of small linear regulators with control lines to enable/disable for power control. Dc/dc parts caused too many spurs requiring added LC filters, negating any size advantage. Just my own opinions...Article: 10227
In a previous article madarass@cats.ucsc.edu (Rita Madarassy) writes: : ; :With all due respect, I do not understant why anybody likes Linux. ;It is obvious any UNIX like platform is fading away. Check out the guys :from SUN: their system looks more and more like an NT. ;The finally realized UNIX sucks. : ;UNIX was never designed for interfacing with humans. It was rather designed :to interface with phones! ; :The PCs were blessed with an operating system designed for human beings ;(WIN 95 and even WIN NT). So why do you want to make your machine stupid :by adding LINUX? ;Tell me about a serious EDA tool in the market that is rational enough :to code for LINUX!! WIN 95 and WIN NT arn't designed for human beings as much as they are design to make human part of the machine. You can hardly get it to do anything useful unless you are sitting in front of it and interact with it on a continuous basis. For me, there is no problem with unix being designed to interface with automatons, as much of the jobs that I run are spawned off through scripts and daemons with minimal user interventioin.Article: 10228
Good afternoon -- My name is Amy Bharucha and I am a recruiter at SUN. I apologize if this is inappropriate, but I am looking for an extremely high-profile position and wondered if I could ask your help. The picoJAVA design group here at SUN is looking for a skilled and experienced Simulation Engineer for the JAVA smartcard project. We need someone familiar with performance modeling, C/C++ and JAVA. The ideal candidate would have strong coding background and would be familiar with computer architecture and HW. If any of you would even mind pointing me in the right direction --- ie other places to post, people to talk to, that would be great. Again. I apologize if I have offended anyone by posting this here .... I simply need some help!! Sincerely, Amy Bharucha Staffing@SMEArticle: 10229
Jim McCloskey wrote: > I'm currently migrating a 5V digital design to a mix of 5V and 3.3V > logic (mix of FPGAs and ASICS). Only a 5V supply is available. Any > good > info on 5V to 3.3V migration, small DC-DC converters, layout > considerations, logic interfacing, etc. would be appreciated. It depends on the amount of current at 3.3V . For less than an amp, a linear 3-terminal ( low drop-out version ) regulator may be unbeatable, but for heavier current it makes sense to use a dc-to-dc converter from Maxim, Linear Technology, Cherry or others. Ever since the Pentium has asked for programmable Vcc, there are plenty of such designs around. Regarding interface levels, be concerned about a 5-V rail-to-rail signal driving a 3.3-V input and forward-biasing the ESD diode.. Be also concerned about power sequencing. Both problems are solved in all XC4000XL devices: they are "5-V tolerant" and draw no input current at 5-V input, even if their own Vcc is zero. And if you are worried about 3.3-V being up while 5-V is down, you can use the 5 V as active Ligh Global Output 3-state on the XC4000XL side. And then there is 2.5 V, and soon 1.8 V and 1.3 V, and so on. Peter Alfke, Xilinx ApplicationsArticle: 10230
> I'm not trying to push Atmel on anyone, but I have always felt that > highly pipelined archtectures was the one place where their chips made > sense. This is especially true if your design is one which flows across > the chip so that each stage can directly connect output to the next > stage input. This is because of the limited routing resources. > > Have either of you looked at their products? I have been hearing some > good things about the 40K family. But it doesn't have the high number of > cells that you get with the 6K family. > > Rick Collins > > rickman@XYwriteme.com > > remove the XY to email me. I've used the 6K extensively (the Atmel FIR filter app note was lifted directly from my 1992 PLDCon paper which is posted on my website), and played with the 40K some. Both are nice devices (The fact that the 6k is a 10 year old design and is still a competitive part says something). I left Atmel out of the earlier discussion because the question was which of Xilinx or Altera was a better choice for DSP applications. The AT6K really shines in bit serial applications, and compares favorably with the xilinx 3k for bit parallel. The fast carry chain, the ability to use CLBs as delays, more flexibility in the cells and better routing resource make the xilinx 4KE and later parts a better choice for bit parallel stuff however. The two biggest shortcomings of the 6K are the insufficient routing and the lack of a fast carry. Additionally, the set of functions achievable in a single cell is a small subset of 2 and 3 input functions, so the designer is stuck doing alot of DeMorgan and other things to minimize logic delays, as well as doing lots of floorplanning up front. These shortcomings make the device somewhat clumsy for bit parallel arithmetic. A one bit serial adder, for instance, requires 6 cells (part of my work years back worked out these combinations) even though the each cell is essentially a half-adder. This is mostly because of routing and cell functionality restrictions. Because of the very limited routing, the color clash problem, and the limited functionality of the cells, extensive handcrafting is required to get the most out of AT6K parts. 125Mhz+ DSP designs are possible with the old -2 silicon...if you are really good. The 40K addresses many of the problems of the 6K: The cell is more flexible and no longer requires 6 cells to make a full adder, the 'color clash' problem is gone (color clash refers to the A and B outputs of the 6K cell... the old interact software colored the A connections red and the B conections blue. A could only connect to A unless you waste a cell the do a crossover route. The problem was that on some functions the input or output could only be on the A or B. The registered output for instance has to output on A). The new part also has a greatly improved local bus route system that essentially provides better than 5x the routing resource. The 40K also adds 32x4 dual port rams at the corner of every 4x4 cell block. An advantage the 40K had over the Xilinx (at the time of introduction) was cost. However with xilinx's introduction of the Spartan line, I think that advantage has more or less evaporated. In certain applications, the AT40K will run rings around the Xilinx because of the comparatively fast cell times. For general purpose DSP work, the jury is still out (ie I haven't played enough with the 40K yet to form a solid opinion) as to which is the better choice. The 40K's biggest handicap appears to be it's lack of a fast carry chain. The distributed RAM is a little harder to work with than the xilinx for distributed arithmetic, but it is workable. Also, the number of registers in the 40K is not much different than xilinx, so there isn't much advantage there (40K20 is 32x32 cells with 1 register per cell where xilinx 4020 is 28x28 cells with 2 registers per cell). An AT6010 is an array of 80x80 cells with a register in each, so for register rich designs the 6K might still be the better choice (extensive shift registers, bit serial designs etc) even if it means doing alot of the handcrafting thing. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka The Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs for digital signal processing, computing and control applications.Article: 10231
Prof. Vitit Kantabutra wrote: > > I'm new to fpga's, and am trying to implement a 12-bit input/output > (17-bit internal) parallel radix-4 CORDIC pipeline (using my own > algorithm). I'm wondering whether I should use Xilinx 4K, Spartan, or > Atmel. > > By the way, I figured out how to do carry-save adders in my particular > application in Xilinx 4K (my application involves reducing 4 binary > operands into two, then with a regular adder from two down to one) -- > Just use the two full adders that are stuck together in the same CLB on > different levels. Then I don't seem to waste anything, so to speak. See my post discussing Atmel under DSP in ALtera or Xilinx. As I think I mentioned before, your application is probably a good fit to the Atmel. The only thing that might get you is the cross routing between CORDIC stages. The AT6K does not have sufficient routing to do a bit parallel CORDIC without wasting many cells for routing (then it gets too slow) I think the AT 40K fixes this enough to be able to route it mostly on the local and express busses. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka The Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs for digital signal processing, computing and control applications.Article: 10232
Hi, One of the requirements of my FPGA design is to have a fast 19-bit adder. How do I instantiate or infer a fast carry-logic adder in FPGA Express? I read the XSI Design Guide, it said to use LogiBlox components. However, inside FPGA Express, I can't use the Logiblox library. For example: LIBRARY logiblox; USE logiblox.mvlutil.ALL; USE logiblox.mvlarith.ALL; USE logiblox.logiblox.ALL; gives me errors that it's not recognizing the library. Thanks in advance.Article: 10233
Hi, One of the requirements of my FPGA design is to have a fast 19-bit adder. How do I instantiate or infer a fast carry-logic adder in FPGA Express? I read the XSI Design Guide, it said to use LogiBlox components. However, inside FPGA Express, I can't use the Logiblox library. For example: LIBRARY logiblox; USE logiblox.mvlutil.ALL; USE logiblox.mvlarith.ALL; USE logiblox.logiblox.ALL; gives me errors that it's not recognizing the library. Thanks in advance.Article: 10234
David Braendler wrote:
> I am trying to use the C++ code provided with the HOT Works
> board to interface with the board via software. Unfortunately I am
> having major difficultiies in doing this. There are a few reasons :
> (a) I dont know what is in the device driver, and hence have no idea
> if
> this is working correctly.(The code uses the device driver)
> (b) The code provided doesn't read in CAL files correctly, nor does
> the
> executables provided by VCC.
>
> I have contacted VCC a few times for help but there is a curious lack
> of
> response from them.....
>
> If anyone has used the C++ code to interface to the HOT Works board, I
>
> would love to get a couple of pointers on how to get started.
>
> Dave Braendler.
> Centre for Intelligent Systems.
> Swinburne University.
I already helped dave (I hope:) but you know how it is
any question about support must be answered. We
are very swamped with hundreds of new users. I'm
sorry if I can't get to each question as fast as needed.
Thanks
(a previous question asked about borland support)
Subject:
Re: [Fwd: Hot Works Development System]
Date:
Tue, 21 Apr 1998 11:26:47 -0700
From:
Steve Casselman <sc@vcc.com>
To:
John Schewel <jas@vcc.com>, dbraendler@swin.edu.au
References:
1
John Schewel wrote:
> pls cc me
> --
>
> Best Regards,
> John Schewel, VP Marketing & Sales
> Virtual Computer Corp.
> http://www.vcc.com
>
>
>
-------------------------------------------------------------------------------------------------------------
>
> Subject: Hot Works Development System
> Date: Tue, 21 Apr 1998 11:56:05 +1000
> From: David Braendler <dbraendler@swin.edu.au>
> To: jas@vcc.com
>
> John,
>
> I have recently obtained a copy of the VCC Hot Works
> development system. Unfortunately I am having some trouble in
> interfacing
> to the board using the C++ source code provided (RALlib). I have
> contacted
> VCC on two previous occasions to ask for some pointers, and have not
> yet
>
> recieved a reply. I would appreciate it if you could give me some idea
>
> of how to proceed as there seems to be some major problems with the
> code
>
> provided. (Your website offers some tips on fixes, but these have not
> worked)
>
> The major problem seems to be that the software does not
> (a) Read in sym files correctly. Well it does, but it doesn't see the
> EOF as it should.
I don't support Borland (I can only support one complier right now)So
I'm not sure what the problem might be. Try and use pci_test to load the
symbol table.Use lsym to load the sym file you can then use rsym read
back the stateof registers by using the names in the symbol table.
> (b) CheckBoard seems to always return false, no matter what I do.
>
> I had thought that one of the problems may be that I am using Borland
> C++
> 5, and the software has not been tested on this platform. However the
> executables
> which you provide on the CD for the ADDER examples do not work either
> -
> it responds with
>
> "Board Initialise Error
> Please check you have a CAL file present"
>
> which I do.
>
> Do you know if this problem is due to a mistake that I am making, or
> is
> it a problem on your end of things?
>
Do me a favor if you could and try and use the Borland debugger.Also the
files in the adder directory need to be renamed if you don't
go through the entire tutorial. Make sure that you copy adder4bk.cal
to adder4.cal - make any name changes that need to be make.
Let me know if this helps.
--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com
--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com
Article: 10235Wen-King Su <wen-king@myri.com> wrote: : WIN 95 and WIN NT arn't designed for human beings as much as they are : design to make human part of the machine. You can hardly get it to do : anything useful unless you are sitting in front of it and interact with : it on a continuous basis. For me, there is no problem with unix being : designed to interface with automatons, as much of the jobs that I run are : spawned off through scripts and daemons with minimal user interventioin. I once counted how many mouse clicks I needed from a change in a schematic capture to the waveform of a simulated fpga in the Quicklogic Quickwork tools. I counted till 30. Missing one step results in unexpected output, where you wonder for some time what has gone wrong. Argh! I want a make command! Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Free Software: If you contribute nothing, expect nothing --Article: 10236
Uwe Bonnes wrote: > > Wen-King Su <wen-king@myri.com> wrote: > > : WIN 95 and WIN NT arn't designed for human beings as much as they are > : design to make human part of the machine. You can hardly get it to do > : anything useful unless you are sitting in front of it and interact with > : it on a continuous basis. For me, there is no problem with unix being > : designed to interface with automatons, as much of the jobs that I run are > : spawned off through scripts and daemons with minimal user interventioin. > > I once counted how many mouse clicks I needed from a change in a schematic > capture to the waveform of a simulated fpga in the Quicklogic Quickwork > tools. > > I counted till 30. > > Missing one step results in unexpected output, where you wonder for some > time what has gone wrong. Argh! > > I want a make command! I'm using the the Xilinx M1.4 software under NT at the moment (I'd prefer to be using Linux). I used the GUI software until I figured out that all the tools are actually 32 bit console apps. I NOW use make which if just SO MUCH better! ErikArticle: 10237
In message <6hjgpc$ga4$1@nnrp1.dejanews.com> - channing-wen@usa.net writes: >I'd like to designs a arbiter which process two, four and >more interrupt request cause the controller can acknowledg- >ing with no priority -- just "first come, first serve", >how to implement it with less cell ? I had a similar problem a while ago, until I realized there was no need to use a "classical" arbiting strategy (though there may be in your application). In its place, I realized a scanner would work just fine. In fact, this would inherently implement something close to a classical round-robin arbiter. In my case, I am scanning 8 inputs at 60ns per input, for a worst-case latency of 480ns. I use similar designs for both interrupt and DMA requests. If your system is asynchronous, you'll of course need metastable synchronizers on the inputs. I'd be curious if anyone's ever seen this before. Not that I'm going to run out and patent it (too late now!), but if I'm the originator of the concept, I hereby christen this approach the "Dunn Arbiter"! Michael DunnArticle: 10238
Steve Dewey wrote: > = > In article <ErxMC3.6KA@world.std.com> jcooley@world.std.com "John Coole= y" writes: > = > > Steve Dewey <Steve@s-deweynospam.demon.co.uk> wrote: > > >Why can't I take my Altera VHDL and run it on another _cheap_ vendor= -specific > > >VHDL tool, eg cypress warp ? > > > > > >Sorry if these are obvious and reveal a lack of insight on my part. > > > > The quick answer is that Altera is primarily interested in getting yo= u to > > buy and use Altera chips. Cypress wants you to buy Cypress chips. N= either > > company really cares about you if you're going to use someone else's > > FPGAs, hence the disincentive towards having their compilers being > > compatiable. If you want universiality, go to vendors who are financ= ially > > motivated to keep you universal: the EDA vendors. (EDA stands for "E= lectronic > > Design Automation" and is just a fancy way of saying "the guys who ma= ke > > software used for chip design".) For example, if you buy Synopsys, E= xemplar, > > Synplicity, or any of the other software from an EDA vendor for FPGA > > synthesis, it will work with Altera, Xilinx, Cypress, etc. BECAUSE it= 's > > the EDA vendor's bread & butter to let their customers CHOOSE between= > > competing FPGA vendors. > > > > (Sorry if I appear to be explaining the obvious to you, but you said = you were > > a newbie who didn't understand these issues.) > > > > - John Cooley > > > Err... Let me clarify: I have not attempted to port VHDL code developed= > in Altera's Maxplus to Cypress' Warp. I was asking whether it would be = feasible > or not. Actually I have both. I do find the syntax very close. I had programs which I wrote for Synopsys and with very little change I ported it to Altera. The main difference was between the two, of where to pu the package file. Of course Cypress is much cheaper and it appears to be a subset of Altera. For example it unfortunatelly does not have "Generate", while Altera does. (So the answer is: Most of the time it is feasable.) -- = Lengyel S=E1ndor Hass, alkoss, gyarapits, S a haza f=E9nyre der=FCl. (K=F6lcsey)Article: 10239
Daniel i Oscar Sanchez wrote: > HI: > > .How can we recognize the nets from the Netlist? Is it possible that in > the layout the gates are named ? > > The program we use is Design Framework II. > > The Hit-kit version is 2.40. > > The process is > Cell/Block Ensemble & Preview ;we start from Composer Schematic and > finish with the layout.Then we get extracted view.And from this view we > make: Tools->Simulation->Other. Simulation->Netlist/Simulate(with > Spice). The Netlist that we get begins with a list like this(is much > longer): > * net 0 = gnd! > * net 0 = gnd! > * net 1 = /o<21> > * net 2 = /160 > * net 3 = /44 > * net 4 = /822 > * net 5 = /463 > * net 6 = /766 > ... > > * net 927 = /60 > * net 928 = /782 > * net 929 = /331 > * net 930 = /634 > * net 931 = /275 > * net 932 = /578 > > Here we can recognize the input and output nets , but not the internal > ones. > That's what we would like to get.(For instance: net 500 = / w<23>) I think the right newsgroup is news:comp.cad.cadence for you. UtkuArticle: 10240
In article <354E877F.45AF@isu.edu>#1/1, kantviti@isu.edu wrote: > > I'm new to fpga's, and am trying to implement a 12-bit input/output > (17-bit internal) parallel radix-4 CORDIC pipeline (using my own > algorithm). I'm wondering whether I should use Xilinx 4K, Spartan, or > Atmel. > > By the way, I figured out how to do carry-save adders in my particular > application in Xilinx 4K (my application involves reducing 4 binary > operands into two, then with a regular adder from two down to one) -- > Just use the two full adders that are stuck together in the same CLB on > different levels. Then I don't seem to waste anything, so to speak. > Your way of thinking is good. It is the right way to do.Thank you -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 10241
If anyone would like an entrance ticket to the Embedded Systems Show
which is taking place at Olympia, London on the 13th and 14th May, email
your address to sales@computer-solutions.co.uk.
On show at the Computer Solutions stand will be the following new
products:-
Windows based RS232 debugger
Embedded C & C++ for Motorola micros
68HC12DG120 In-circuit emulators
Flash and ROM Emulators
Super fast Ethernet BDM Emulators
Embedded TCP/IP, Web Server and Browser
Embedded DOS & W95 Compatible file system
Not to mention COMSOLs Embedded Engineers Web Site
Regards, Chris
-----------------------------
Chris Stephens E-mail: sales@computer-solutions.co.uk
Computer Solutions Ltd. Phone & Fax: +44 (0)1 932 829 460
1a New Haw Road, Addlestone,
Surrey, KT15 2BZ England http://www.Computer-Solutions.co.uk
For the largest range of embedded microprocessor development tools in the UK
Article: 10242MD wrote: > > In message <6hjgpc$ga4$1@nnrp1.dejanews.com> - channing-wen@usa.net > writes: > > >I'd like to designs a arbiter which process two, four and > >more interrupt request cause the controller can acknowledg- > >ing with no priority -- just "first come, first serve", > >how to implement it with less cell ? > > I had a similar problem a while ago, until I realized there was no need > to use a "classical" arbiting strategy (though there may be in your > application). In its place, I realized a scanner would work just fine. > In fact, this would inherently implement something close to a classical > round-robin arbiter. In my case, I am scanning 8 inputs at 60ns per > input, for a worst-case latency of 480ns. I use similar designs for > both interrupt and DMA requests. > > If your system is asynchronous, you'll of course need metastable > synchronizers on the inputs. > > I'd be curious if anyone's ever seen this before. Not that I'm going to > run out and patent it (too late now!), but if I'm the originator of the > concept, I hereby christen this approach the "Dunn Arbiter"! > > Michael Dunn Been there done that -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka The Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs for digital signal processing, computing and control applications.Article: 10243
Hi, Is it true that there is no production anymore (due to problems) of the Altera EPF10K100 speedgrade 1, package BGA 356 pins? When this isn't true, where can I get these components VERY FAST ? I ordered them by our distributor (the only one in Belgium for Altera) and they can't say when they can deliver them. We need them very urgent (1-2 weeks) Please help us !! Peter Brandt DSP-VLSI Design engineer Philips ITCL Interleuvenlaan 10 3000 Leuven, Belgium Peter.brandt@leu.ce.philips.comArticle: 10244
I just realize that I incorrectly wrote :
>I did not use BALE nor AEN, just nIORD & nIOWR (I'm doing only
>in the I/O space).
This is indeed wrong !
One MUST use AEN=0 as a qualifier for the decoder !!!
Otherwise, the board will respond when it's not supposed to
(like during DMA transfers and corrupt the transfer data,
a rather unpleasant experience !)
Bert Cuzeau
FPGA Design Expert
Paris - France
to defeat junk mail,
remove the "y" in the following address :
AyLSE@compuserve.com
Web :
http://ourworld.compuserve.com/homepages/alse
Article: 10245
This is a follow up to my posting from last week entitled "Enforcing Clock Enable Connection in Synthesis",
regarding problems we have experienced in synthesizing clock-enabled logic with Exemplar and
Synplicity tools. I would like to thank everyone for the many thoughtful responses I received.
In particular, Stuart Clubb of Saros Technology (English Exemplar Rep) provided a very cogent
analysis of the phenomenon, and generated lovely "simple failing subset" examples. Nicely done!
Specal thanks to Hoa Dinh of Exemplar, who invented what I consider to be quite an elegant work-around,
which we are now incorporating. Hoa's solution is to separate the clock enable term from the rest
of the combinatorial logic, using two separate processes, and intermediate signals, as illustrated
in the code below (which is adapted from one of Stuart's examples).
In the first architecture, "mixed_up_clock_enables", the "result" DFFE's end up with a combinatorially
driven ENA signal, which is undesirable in some applications (such as ours) due to timing
considerations. The second architecture, "beautiful_clock_enables", preserves the essential logic, but
forces the synthesis tool to connect the clock enables as a separate, dedicated net, allowing the
combinatorial logic in this section multiple clock cycles to settle out, as long as the clock enable meets
the global clock timing.
This is definitely a good, interim fix. However, it adds code complexity and an unnecessary layer of indirection.
The long term fix, I believe, is for the synthesis tools to recognize the sanctity of clock enables directly somehow,
(or through attributes, compiler options, or constraints). Tool guys, are you listening?
Thanks,
Tom Meagher (last name pronounced "mar", don't ask why...)
tomm@icshou.com
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
--============================================================
ENTITY test IS
--============================================================
PORT (
clk : IN STD_LOGIC ;
aclr_n : IN STD_LOGIC ;
clk_ena : IN STD_LOGIC ;
condition : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
rst_s : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0) ;
data_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) ;
result : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
) ;
END test ;
--============================================================
ARCHITECTURE mixed_up_clock_enables OF test IS
--============================================================
SIGNAL data_aff : std_logic_vector (3 DOWNTO 0) ;
SIGNAL data_bff : std_logic_vector (3 DOWNTO 0) ;
BEGIN
all_in_one : PROCESS ( clk, aclr_n )
BEGIN
IF ( aclr_n = '0' ) THEN
result <= (OTHERS => '0') ;
data_aff <= (OTHERS => '0' ) ;
data_bff <= (OTHERS => '0' ) ;
ELSIF( clk'event and clk = '1' ) THEN
IF (clk_ena = '1') THEN
IF (rst_s = '1') THEN
data_aff <= (OTHERS => '0' ) ;
data_bff <= (OTHERS => '0' ) ;
result <= (OTHERS => '0') ;
ELSE
data_aff <= data_a ;
data_bff <= data_b ;
CASE (condition) IS
WHEN "00" =>
result <= data_aff - data_bff ;
WHEN "01" =>
result <= data_bff - data_aff ;
WHEN "10" =>
result <= data_aff + data_bff ;
--when "11" => --un-comment these 2 lines and it synths OK
-- result <= data_bff + data_aff ;
WHEN OTHERS =>
NULL ;
END CASE ;
END IF ;
END IF ;
END IF ;
END PROCESS ;
END mixed_up_clock_enables ;
--============================================================
ARCHITECTURE beautiful_clock_enables OF test IS
--============================================================
SIGNAL data_aff : std_logic_vector (3 DOWNTO 0) ;
SIGNAL data_bff : std_logic_vector (3 DOWNTO 0) ;
SIGNAL result_s : std_logic_vector (3 DOWNTO 0) ;
--create intermediate variables
SIGNAL i_data_aff : std_logic_vector (3 DOWNTO 0) ;
SIGNAL i_data_bff : std_logic_vector (3 DOWNTO 0) ;
SIGNAL i_result : std_logic_vector (3 DOWNTO 0) ;
BEGIN
--this process connects the clock enables, and samples the combinatorial signals
sequential_logic:
PROCESS(aclr_n, clk)
BEGIN
IF aclr_n='0' THEN
result_s <= (others => '0') ;
data_aff <= (others => '0' ) ;
data_bff <= (others => '0' ) ;
ELSIF RISING_EDGE(clk)THEN
IF clk_ena='1' THEN
result_s <= i_result ;
data_aff <= i_data_aff ;
data_bff <= i_data_bff ;
END IF;
END IF;
END PROCESS;
--this process generates the combinatorial logic
combinatorial_logic :
PROCESS
(
rst_s,
condition,
data_a,
data_b,
result_s,
data_aff,
data_bff
)
BEGIN
i_data_aff <= data_aff;
i_data_bff <= data_bff;
i_result <= result_s ;
IF (rst_s = '1') THEN --synchronous reset
i_data_aff <= (OTHERS => '0' ) ;
i_data_bff <= (OTHERS => '0' ) ;
i_result <= (OTHERS => '0') ;
ELSE
i_data_aff <= data_a ;
i_data_bff <= data_b ;
CASE (condition) IS
WHEN "00" =>
i_result <= data_aff - data_bff ;
WHEN "01" =>
i_result <= data_bff - data_aff ;
WHEN "10" =>
i_result <= data_aff + data_bff ;
--when "11" =>
-- i_result <= data_bff + data_aff;
WHEN OTHERS =>
NULL ;
END case ;
END IF ;
END PROCESS ;
result <= result_s;
END beautiful_clock_enables ;
Article: 10246In article <6ihd7o$i1q@darkstar.ucsc.edu>, Rita Madarassy <madarass@cats.ucsc.edu> wrote: > >With all due respect, I do not understant why anybody likes Linux. More and more of us are liking Linux because it is so much more stable than Win(95|NT|whatever). I run Linux at home and recently had an uptime (ie I didn't have to reboot) of 64 days. The only reason I had to shut the system down was that we were having some electrical wiring done in our house and had to shut off all of the power - otherwise it probably would have gone for another 64 days. You'd be hard pressed to find a Win(95|NT|whatever) stay up for that long - unless, perhaps, it is only running a screen saver all that time ;-) >It is obvious any UNIX like platform is fading away. Check out the guys >from SUN: their system looks more and more like an NT. >The finally realized UNIX sucks. Well, their systems look more like PCs, but I don't think that Solaris has been hamstrung to look like (and act like) NT yet. With Linux you can get the best of both worlds - fast, cheap hardware (standard PCs) and the power and stability of UNIX. > >UNIX was never designed for interfacing with humans. It was rather designed >to interface with phones! > >The PCs were blessed with an operating system designed for human beings >(WIN 95 and even WIN NT). So why do you want to make your machine stupid >by adding LINUX? If Win(95|NT|98|whatever) is a blessing, I'd hate to see what a curse would be like. There are a couple of efforts underway in the Linux world to make it as easy to use as any Windows machine. The KDE desktop is already quite stable and usable and at least as easy to use as NT. The GNOME project is also making rapid progress with help from RedHat. Within 6 months the ease of use issue (or lack thereof) will not be a valid reason for rejecting Linux - you'll have to think up some other excuses. >Tell me about a serious EDA tool in the market that is rational enough >to code for LINUX!! There are getting to be more of these all of the time - there are Linux advocates everywhere! philArticle: 10247
In article <354FAD72.C9A@REMOVE-THIS.fairlightesp.com.au>, Erik de Castro Lopo <erikd@zip.com.au> wrote: > >I'm using the the Xilinx M1.4 software under NT at the moment (I'd prefer to >be using Linux). If you want the Xilinx software (or any other EDA software for that matter) running on Linux then you have to make some noise. Call up Xilinx (or send'em e-mail) and demand a Linux version. If enough people do this they'll start to get the idea. Chances are good that some software engineer(s) at Xilinx already has it running on Linux. Its a matter of convincing the suits to release it - customers need to demand it. philArticle: 10248
Tom, What was the difference in simulation clock rate? In case you didn't get copies of the several e-mails, Steve passed my comments to Altera inside tech support. The gist is that the 10KA clock enables are improved over the 10K clock enables. Neither one is especially fast compared to other global signals. In both cases having more than one or two clock enables negates any benefits. A better alternative would be to have a local clock enable F/F in each LAB driven by a master. I expect that will get faster clock rates than most anything else. Scott Taylor - DSP Fibre Channel Systems -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 10249
>More and more of us are liking Linux because it is so much more stable >than Win(95|NT|whatever). I run Linux at home and recently had an uptime >(ie I didn't have to reboot) of 64 days. The only reason I had to shut >the system down was that we were having some electrical wiring done in our >house and had to shut off all of the power - otherwise it probably would >have gone for another 64 days. You'd be hard pressed to find a >Win(95|NT|whatever) stay up for that long - unless, perhaps, it is only >running a screen saver all that time ;-) I am the last man to support MS but this is simply not true. I have been running NT4 since about 8/96, and cannot recall crashing it with any "normal" app. I have crashed it many times (hung it, actually) by screwing around with the SCSI HD/CDROM/tape subsystem, and similar, but that's to be expected. Normal apps do have bugs (plenty of bug-ridden C++ bloatware out there, and more every day) but usually one can just terminate the app without it affecting anything else. I run around 100 apps, mostly CAD/EDA, including some old DOS ones >10 years old, quite a lot of win3.x apps, some win32s apps, a lot of win32 apps. Show me a way to crash NT (yes, there are many ways, mostly to do with misconfigured or defective hardware) and I will show you a way to crash any other PC O/S. NT does have many areas which could have been done much better, e.g. its crappy memory management which forces anyone doing anything serious to get >64MB RAM. But even my 128MB cost me peanuts, relatively speaking. Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.
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