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Hi everyone, I have a some questions about CPLD vs FPGA 1. When would you use CPLD and when would you use FPGA? 2. What are the effects of the ARCHITECTURE (macrocells, logic cells, routing, etc.) of both the CPLD and FPGA on the SPEED and chip AREA of the circuits implemented in them? 3. Is it true that the extra routing in FPGA makes it slower than CPLD? 4. So, which is more advantageous? Oh, another question. I'm using Altera Maxplus2 CAD tool. When implementing state machines, is the automatically generated state assignment always the best one? What is the guideline in doing state assignment, if we're to do it manually? Thank you. ( o )===::: BobbyArticle: 10276
Prof. Vitit Kantabutra wrote:
>
> I'm new to fpga's, and am trying to implement a 12-bit input/output
> (17-bit internal) parallel radix-4 CORDIC pipeline (using my own
> algorithm). I'm wondering whether I should use Xilinx 4K, Spartan, or
> Atmel.
>
> By the way, I figured out how to do carry-save adders in my particular
> application in Xilinx 4K (my application involves reducing 4 binary
> operands into two, then with a regular adder from two down to one) --
> Just use the two full adders that are stuck together in the same CLB on
> different levels. Then I don't seem to waste anything, so to speak.
--
I wonder if you really are getting the full two bits per CLB with this
approach. If I understand the carry save adder correctly, then you need
to have a register on each sum bit and the carry bit. If I understand
what you are doing with the CLB carry chain, you are using the two bits
in the CLB together and using the carry out of the CLB. In essence you
are doing a carry save add, but two bits at a time. The problem is that
you still need to use a second CLB for your two bit adder. Unless Xilinx
has changed something in the latest XC4000 series chips, the carry chain
can not connect to the general routing. So you have to use a half of a
CLB to add a carry in, and a half of a CLB to get to the carry out. See
the ascii art diagram below. You will need to view with a mono-spaced
font.
CI A1 B1 A2 B2
| | | | |
__V__ _V_V_ _V_V_ _____
| | | | | | |
| | FC | | | FC | |
| |--->| | |--->| |
| | | | | | |
|_____| |_____|_____| |_____|
| | |
V V V
S1 S2 CO
You will find that this is not a fast way to generate the carry anyway.
The slowest path here is in the CI, through the carry chain, to the
clock at the CO (4.1 ns). I calculate a clock to clock delay (without
routing) of 5.7 ns for the XC4000XL-1, for a clock freq of 175 MHz. Not
bad, but if you use the two CLBs to directly generate the carry and sum
you get a clock to clock delay (without routing) of 2.5 ns or 400 MHz.
If you connect multiple CLBs to use larger adders, the delay goes up by
only 0.2 ns per pair of bits. So for four bits, it is 5.9 ns, for 8 bits
it is 6.3 ns... You see that it does not cost very much in delay to
extend the length of the adder.
I checked the data book, and found that the Fast Carry in and out of the
CLB can be connected to the general routing. But I doubt that this is a
lot faster than the numbers I have above. But if you do that, you only
need 1.5 CLBs for two bits of adder plus a carry out (all registered).
Am I anywhere near what you were thinking?
Rick Collins
rickman@XYwriteme.com
remove the XY to email me.
Article: 10277Peter Alfke wrote: > Regarding the use in life support applications, I want to bring to > your attention a standard disclaimer issued by every semiconductor > company I know. > In our case it is phrased: > > "Xilinx products are not intended for use in life support appliances, > devices, or systems. Use of a Xilinx product in such applications > without the written consent of the appropriate Xilinx officer is > prohibited." > ( Last paragraph on the inside front cover of our data book). > > As I said, every manufacturer who understands the danger of a > liability lawsuit has issued such a statement somewhere. > > Peter Alfke, Xilinx Applications hi peter, does the disclaimer typically apply to hi-rel devices bought under the military specifications? rkArticle: 10278
If it is specified with the lines floating there is usually quite a drop with the lines pulled to a rail. This is normal for CMOS. Also if the temperature is less than max this will help too. Simon -------------------------------------------------------------------------------------------------------- peterc <peterc@hmgcc.gov.uk> wrote: >Peter Alfke wrote: >> > ><snip> > >> You can achieve microamp consumption with XC3000L, but also with the >> more modern XC4000XL devices if you: >> >> * turn off the internal oscillator ( is already the default) >> * turn off all internal longline pull-ups >> * turn off all I/O pull-ups and pull-downs and define the voltage >> on every unconnected or unused pin by driving it High internally >> * minimize all internal activity :-) >> * run at a low voltage, closer to 3.0 than 3.6 V >> * avoid high temperatures >> > >The xilinx data book states 5mA Quiescent for 4000XL (1998 page 4-72). >This is with a note that all I/O is tri-state and floating, no output >load, no active input or longline pull-ups. > >Does the current really come down to microamps by following your other >recommendations. It seems a large drop in current from the maximum >quiescent, or is the max quiescent specified quite high so that there >may be a large variation between batches. > >Would Xilinx be able to gaurentee a lower max quiescent under certain >conditions? Opinions expressed herein are solely my own and may or may not reflect my opinion at this particular time or any other.Article: 10279
An application page has been generated showing the details of the APS-X208 debug board and its unique control software at: http://www.associatedpro.com/x208/prod/X208stuff.html The X208 architecture contains two FPGAs--one for interfacing to the ISA BUS (INTERFACE FPGA) and one socketed and connected to a large number of interface connectors (TEST FPGA). Both FPGAs can be fully customized and controlled by users, or the users can use the EASY INTERFACE SOFTWARE provided. The EASY INTERFACE sets up the interface FPGA as bridge chip between the ISA BUS and the test FPGA, establishing an FPGA LOCAL bus between the INTERFACE and TEST FPGA. The INTERFACE FPGAs address is set up via hardware jumpers and then allows the use of the WIN95 X208.EXE program to automate many of the processes in the FPGA development and test process. -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com 3003 Latrobe Court richard@associatedpro.com Abingdon, Maryland 21009 Phone: 410.569.5897 Fax:410.661.2760 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 10280
You have to be careful with this. The following example should work for
inserting GLOBAL buffers in the XILINX and other VHDL compilers. I remember
however that Exemplar had a problem with the buffers not actualling
instantiating (which they subsequently fixed) in XILINX parts.
One problem you may have in the XVHDL metamor compiler is that it
automatically inserts global buffers where it feels they are needed.This can
be a nice feature unless you have already placed the pins. If the clock
driving those pins are not attached to the correct FPGA pins (primary or
secondary global clock FPGA pins) you get an error when you go to place and
route the part. The answer is to turn off the automatic insertion of the
global buffers and to insert them yourself. Turning off the automatic
insertion is done in an argument file in the XVHDL compiler. A detailed tech
note describing exactly how to do this is described in the X84 tech note
section of our website http://www.associatedpro.com in particular at
http://www.associatedpro.com/x84/support/x84_sup.html ,
If you are using the Accolade PeakFPGA version of the Metamor compiler you can
turn off the automatic insertion from the windows interface.
The following code is an example using the APS-X84 board. A global buffer
component -BUFGS- (done once) is created and in this case is instantiated
three times to create three distinct buffers. This same procedure should work
for any VHDL compiler.
If you have an X84 board there is C code available which will control the
board and exersize the VHDL code example provided. If you don't have one, get
one (-: , they are low cost, and are excellent for implementing and solving
problems just like this one (-:
The X84 boards come with labs and VHDL examples on CD which really save you
tons of time. It also comes with the Accolade PeakVHDL simulator and PeakFPGA
compiler in usable demo format.
(see http://www.associatedpro.com/x84/prod/x84_ds.html )
Also check out our VHDL free on line lab and our free newsletter which can be
subscribed to. They all provide tips and hints on using FPGAs and VHDL in
particular.
The following code shows the use of a secondary Global buffer in VHDL
(among other things)
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Associated Professional Systems, Inc.
-- 3003 Latrobe Court, Abingdon, MD 21009
--------------------------------------------------------------------------
--
-- Project: Example VHDL file for APS X-84 Board
-- 2 number SORT
-- Date: 23 November 97
-- Author: Richard Schwarz
-- Title: APS-X84 READ WRITE sort
--
-- Description:
--
--
--
-- Contents:
---
-- Generics:
--
-- Version: 1.0
--
-- Revision History:
--------------------
-- Rev:
-- Date:
-- Author:
-- Description:
--
--
--------------------------------------------------------------------------
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library METAMOR;
use METAMOR.attributes.all;
library SYNOPSYS;
use SYNOPSYS.std_logic_arith.all;
use SYNOPSYS.std_logic_unsigned.all;
ENTITY X84RD_WR IS
PORT
(
WRin: IN std_logic;
RDin: IN std_logic;
LED: OUT std_logic;
CLKin: IN std_logic;
--eight bit IO bus
DataBus: INOUT std_logic_vector(7 downto 0)
);
attribute pinnum of DataBus : signal is "P10,P9,P8,P7,P6,P5,P4,P3";
attribute pinnum of WRin : signal is "P17";
attribute pinnum of RDin : signal is "P18";
attribute pinnum of LED : signal is "P35";
attribute pinnum of CLKin : signal is "P13";
END X84RD_WR;
----------------------------------------------------------------
----------------------------------------------------------------
ARCHITECTURE behave OF X84RD_WR IS
-- Data Storage Registers
signal IOByte_0 : STD_LOGIC_VECTOR(7 downto 0);
signal IOByte_1 : STD_LOGIC_VECTOR(7 downto 0);
signal BigNum : STD_LOGIC_VECTOR(7 downto 0);
signal LitNum : STD_LOGIC_VECTOR(7 downto 0);
signal TempDataBus : STD_LOGIC_VECTOR(7 downto 0);
signal cnt : INTEGER range 1 downto 0;
signal rd, wr, clk : STD_LOGIC;
component BUFGS
port (I: in std_logic;
O: out std_logic);
end component;
BEGIN
WRBUF: BUFGS port map (I => WRin, O => WR);
RDBUF: BUFGS port map (I => RDin, O => RD);
CLKBUF: BUFGS port map (I=> CLKin, O=> CLK);
LED <= '1' when IOByte_0 > IOByte_1 else '0'; --is last number larger
DataBus <= TempDataBus when RD = '1' else "ZZZZZZZZ";
-- DO IO
WRITE: PROCESS(WR,RD)
BEGIN
if (WR'EVENT AND WR = '1') then
IOByte_1 <= IOByte_0;
IOByte_0 <= DataBus;
Cnt <= 0;
end if;
if (RD'EVENT AND RD = '1') then
if cnt = 0 then
TempDataBus <= LitNum;
cnt <= cnt +1;
else
TempDataBus <= BigNum;
end if;
end if;
END PROCESS;
--Do computations with clock
Compute: PROCESS(CLK)
BEGIN
if IOByte_0 > IOByte_1 then
BigNum <= IOByte_0;
LitNum <= IOByte_1;
else
BigNum <= IOByte_1;
LitNum <= IOByte_0;
end if;
END PROCESS;
END behave;
Rickman wrote:
> Michael Schmid wrote:
> > Hi,
> >
> > I'm working with Xilinx XACT-M1.3. I wrote my design in VHDL.
> > Now I have the same problem with a XC4013XL chip. Because of not using
> > the global clock buffers I have enormous clock skew.
> >
> > So I've tried to use the BUFGS. I've clicked the "generic clock buffers"
> > button in the options-menu of XACT-M1. But after implementation the
> > buffers are not used.
> >
> > Now my question:
> > How can I use the BUFGS in VHDL ?
>
> --
> I have never done an entirely VHDL design. I use schematics at the top
> level to link everything together. My suggestion would be to add a top
> level schematic where you can manually place a BUFGS on the clock input.
>
> If you don't want to use a schematic, why not try giving Xilinx a call
> at 800-624-4782? What are you using for the front end? Are you using
> Foundation, or are you using one of the third party vendors? If you
> don't have support, let me know and I will give them a call about this.
>
> Rick Collins
>
> rickman@XYwriteme.com
>
> remove the XY to email me.
--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Richard Schwarz, President EDA & Engineering Tools
Associated Professional Systems (APS) http://www.associatedpro.com
3003 Latrobe Court richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897 Fax:410.661.2760
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Michael Schmid wrote:
> Rickman wrote:
> >
> > Vo To wrote:
> > >
> > > Hello,
> > >
> > > I'm using the Xilinx Foundation Series software to implement my FPGA
> > > design. One of the biggest problem with my design are frequent hold time
> > > errors (running at 25 Mhz, clock cycle = 40 ns) reported during timing
> > > simulation.
> > >
> > > If I reduce the clock to 12.5 Mhz, the hold time errors disappear and
> > > the signals are valid and my state machine works fine.
> > >
> > > Are the hold time errors caused from assigning too wide a signal bus?
> > > For example, in a clock cycle, I need to drive 32 internal signals to
> > > the external bidirection pins. Is it too much for the XC4025E to change
> > > 32 flip-flops in 40ns?
> > >
> > > To test this out, I reduced to using 8 lines of signal. At 25 Mhz, the
> > > simulation did not report hold time errors. If I increase to 16 lines,
> > > hold time errors occurs.
> > --
> > I don't know the particulars of your circuit, but my guess is that you
> > are not using the global clock routing. If you don't use the global
> > clock routing, as you add more FFs, the data path does not slow down,
> > but your clock routing does. This will have the data from the previous
> > stage changing from the current clock edge, before the clock reaches the
> > next stage.
> >
> > To fix this, you need to bring the clock onto the chip through a BUFGS
> > rather than an IBUF. Change this buffer and your hold time violation
> > should go away. BTW, you should never get a hold time violation in any
> > FPGA. This is caused by your data delay being too SHORT, which is
> > something that should never happen. If your data path delay is too LONG,
> > you will get setup time violations.
> >
> > Rick Collins
> >
> > rickman@XYwriteme.com
> >
> > remove the XY to email me.
> --
>
> Hi,
>
> I'm working with Xilinx XACT-M1.3. I wrote my design in VHDL.
> Now I have the same problem with a XC4013XL chip. Because of not using
> the global clock buffers I have enormous clock skew.
>
> So I've tried to use the BUFGS. I've clicked the "generic clock buffers"
> button in the options-menu of XACT-M1. But after implementation the
> buffers are not used.
>
> Now my question:
> How can I use the BUFGS in VHDL ?
--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Richard Schwarz, President EDA & Engineering Tools
Associated Professional Systems (APS) http://www.associatedpro.com
3003 Latrobe Court richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897 Fax:410.661.2760
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Article: 10281
TITLE: FPGA Eng
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Article: 10282On Fri, 08 May 1998 09:08:23 -0400, Ray Andraka <no_spam_randraka@ids.net> wrote: >Routing in FPGAs is becoming the limiting factor on speed. Its almost >to the point that logic is free and the routing is what you are buying. >Still, if you floorplan your design, you can greatly improve the delays >caused by routing. Agreed. That's one of the problems of ASIC vs FPGA. Hook your fast gates up with fast metal in an ASIC, or hook fast(ish) LUTs up with metal-via-poly-junction-poly-via-metal slow (relatively) SRAM interconnect. It's funny though. Many moons ago I was designing 4000 series -4 parts (non-E), which had a 4 ns CLB delay (-5's had 5 ns etc.) and then suddenly a -4 4000E becomes 2.7 ns, but I seem to recall no change in chip-level performance numbers such as clk2q. Wonder where all that delay went? Surely not a smoke and mirrors job with the hidden routing? Lucent followed suit by quoting the LUT delay separately from the output multiplexer of the PFU. Still, at least they still quote it. Oh, and Altera had input routing, output routing, bypass, combinatorial, and all that stuff too. However, 85% routing delay sounds high, but can be reached if you have very high fan-out, although 11 levels of logic suggests that a different synthesis strategy may be required. (Like another tool?). :-) StuartArticle: 10283
rk wrote: > Peter Alfke wrote: > .... > > > "Xilinx products are not intended for use in life support > appliances, > > devices, or systems. Use of a Xilinx product in such applications > > without the written consent of the appropriate Xilinx officer is > > prohibited." > > ( Last paragraph on the inside front cover of our data book). > > > > As I said, every manufacturer who understands the danger of a > > liability lawsuit has issued such a statement somewhere. > > > > Peter Alfke, Xilinx Applications > > hi peter, > > does the disclaimer typically apply to hi-rel devices bought under the > > military specifications? > > rk This disclaimer has nothing to do with the actual reliability of the devices. Some people, including me, actually believe that hi-rel devices are no better than commercial parts; they have just been tested and documented more thoroughly. That by itself does not really make them more reliable ! The disclaimer is obviously there to prohibit applications that might, worst case, lead to horrendous product-liability lawsuits. We have no choice in this matter, until someone "kills all the lawyers"... ( I recently had a lawyer threatening me with "$ 500,000 or more" for a fender-bender accident. I am all for the Shakespeare solution... ) Peter Alfke, speaking for himself. Peter Alfke, Xilinx Apps.Article: 10284
MMmmm Intresting. What synth tool are you using? Most tools will pop out BUFG's all by themselves. It seems obvious that your tool is not doing so. So the best work around is to manually instantiate them. Is it possible that the clock nets of interest are derived on chip? One should use BUFS for chip produced clocks. Maybe the synth tool has some problem with this. Wonder why the "use generic clocks" in XACT did not work? The reason for this is that the switch allows the tool to change BUFP to BUFS and vice-a-versa(sp?). Basicly you tell the tool to treat all BUFs as BUFGs. How ever this does no good what so ever if you have no buffers at all! Have FUN Nick Michael Schmid wrote: > Rickman wrote: > > > > Vo To wrote: > > > > > > Hello, > > > > > > I'm using the Xilinx Foundation Series software to implement my FPGA > > > design. One of the biggest problem with my design are frequent hold time > > > errors (running at 25 Mhz, clock cycle = 40 ns) reported during timing > > > simulation. > > > > > > If I reduce the clock to 12.5 Mhz, the hold time errors disappear and > > > the signals are valid and my state machine works fine. > > > > > > Are the hold time errors caused from assigning too wide a signal bus? > > > For example, in a clock cycle, I need to drive 32 internal signals to > > > the external bidirection pins. Is it too much for the XC4025E to change > > > 32 flip-flops in 40ns? > > > > > > To test this out, I reduced to using 8 lines of signal. At 25 Mhz, the > > > simulation did not report hold time errors. If I increase to 16 lines, > > > hold time errors occurs. > > -- > > I don't know the particulars of your circuit, but my guess is that you > > are not using the global clock routing. If you don't use the global > > clock routing, as you add more FFs, the data path does not slow down, > > but your clock routing does. This will have the data from the previous > > stage changing from the current clock edge, before the clock reaches the > > next stage. > > > > To fix this, you need to bring the clock onto the chip through a BUFGS > > rather than an IBUF. Change this buffer and your hold time violation > > should go away. BTW, you should never get a hold time violation in any > > FPGA. This is caused by your data delay being too SHORT, which is > > something that should never happen. If your data path delay is too LONG, > > you will get setup time violations. > > > > Rick Collins > > > > rickman@XYwriteme.com > > > > remove the XY to email me. > -- > > Hi, > > I'm working with Xilinx XACT-M1.3. I wrote my design in VHDL. > Now I have the same problem with a XC4013XL chip. Because of not using > the global clock buffers I have enormous clock skew. > > So I've tried to use the BUFGS. I've clicked the "generic clock buffers" > button in the options-menu of XACT-M1. But after implementation the > buffers are not used. > > Now my question: > How can I use the BUFGS in VHDL ?Article: 10285
Jacob W Janovetz wrote: > madarass@cats.ucsc.edu (Rita Madarassy) writes: > > >With all due respect, I do not understant why anybody likes Linux. > >It is obvious any UNIX like platform is fading away. Check out the guys > >from SUN: their system looks more and more like an NT. > >The finally realized UNIX sucks. > > >UNIX was never designed for interfacing with humans. It was rather designed > >to interface with phones! > > >The PCs were blessed with an operating system designed for human beings > >(WIN 95 and even WIN NT). So why do you want to make your machine stupid > >by adding LINUX? > >Tell me about a serious EDA tool in the market that is rational enough > >to code for LINUX!! > > LINUX machine:> uptime > 10:03am up 33 days, 23:33, 4 users, load average: 0.00, 0.01, 0.00 > ^^ > ^^ >>Good reason.>> > > > That's one reason. > > Cheers, > Jake > > -- > janovetz@uiuc.edu | Once you have flown, you will walk the earth with > University of Illinois | your eyes turned skyward, for there you have been, > | there you long to return. -- da Vinci > PP-ASEL | http://www.ews.uiuc.edu/~janovetz/index.htmlArticle: 10286
When you say Foundation though I tend to think not just of the place and route tools but the front end stuff (schematics, state machine editor, simulator and such). I know nothing about Lunix ( outside of the usual common knowledge stuff (free, sort of like UNIX)) but I would guess that porting the front end stuff would be a real mess because of all the graphics that are part of it. The place and route tools because they are really command line driven and already running on unix, I would guess could move to Lunix fairly easy. I am sure that if enough requests are heard for a Lunix place and route tool the market will listen. Have FUN Nick Andrew Veliath wrote: > Hi, > > I'm using Xilinx Foundation M1.3 for a class, and am wondering if > Xilinx will release a Linux version. Under 95 things start to become > unstable after a day or two for me (sometimes after a few hours even), > and I have to reboot (I don't want NT either). > > I know they do make some software for various Unices, but a Linux > version would be excellent. > > -- > Andrew Veliath > andrewtv@usa.net, veliaa@rpi.eduArticle: 10287
Gack, nobodies replied to this? It is Saturday now and this show a Tuesday post, surprising. It is a pretty well documented process. When you run LogiBLOX you have the option of creating a VHDL implimentation template. This produces a *.VHI file. The "component" and "port map" to use the part are in this file. No library calls in Express are needed because all Express does is hook-up a black box of the instatiated Logiblox component. The program NGDbuild in the XACT_M1 tools takes care of merging the Logiblox made netlist into the netlist supplied by Synopsys. Optimization of the Logiblox component is not performed in Express because it is already "optimal" from Logiblox. There is a click box to allow Express to infer a GSR function even with a "black-box" instatiated block. Check this out if you need a user GSR. Have FUN!! Nick Vo To wrote: > Hi, > > One of the requirements of my FPGA design is to have a fast 19-bit > adder. > > How do I instantiate or infer a fast carry-logic adder in FPGA Express? > I read the XSI Design Guide, it said to use LogiBlox components. > However, inside FPGA Express, I can't use the Logiblox library. For > example: > > LIBRARY logiblox; > USE logiblox.mvlutil.ALL; > USE logiblox.mvlarith.ALL; > USE logiblox.logiblox.ALL; > > gives me errors that it's not recognizing the library. > > Thanks in advance.Article: 10288
Pete out lined the basic idea for low power design. Low-volts, run them as low as is possible with out leaving the rated operating range. 3k-Ls. And you have the other....slow clocks. I have made slow clock circuits with such parts that run under 100uA and standby at less then a uA. One thing Pete did not mention is a standard design trick with slow stuff at low power. Never use a standard counter if at all possible. Use only ripple counters. They are real slow, but because they only clock each register when it actually has to change they use much less power. There are some other cute clock tricks I used in the past to stop the clock to un-used at a particular time sections of the logic. Most of them involved using the falling edge for clock control and the rising edge for logic. This works fine in a slow system. Note often using the supplied clock enables on the a chip still clocks the register, it is just that the output is feed back when the clock is disabled. So one must actually stop the from clock going to the register to save maximum power. Have FUN!! Nick Phil Cook wrote: > I am beginning research on doing using a FPGA to implement a > digital circuit for an implantable cardio defibrillator. Due to the > nature of the product, low power consumption is a primary concern. > I was wondering if any one has any documentation or advice on > doing a low power, low frequency design using an FPGA. The chip > will only need to be clocked at a few hundred hertz. > > Any help would be appreciated. > TIA , > > Phillip Cook.Article: 10289
Pete out lined the basic idea for low power design. Low-volts, run them as low as is possible with out leaving the rated operating range. 3k-Ls. And you have the other....slow clocks. I have made slow clock circuits with such parts that run under 100uA and standby at less then a uA. One thing Pete did not mention is a standard design trick with slow stuff at low power. Never use a standard counter if at all possible. Use only ripple counters. They are real slow, but because they only clock each register when it actually has to change they use much less power. There are some other cute clock tricks I used in the past to stop the clock to un-used at a particular time sections of the logic. Most of them involved using the falling edge for clock control and the rising edge for logic. This works fine in a slow system. Note often using the supplied clock enables on a chip still clocks the register, it is just that the output is feed back when the clock is disabled. So one must actually stop the from clock going to the register to save maximum power. Have FUN!! Nick Phil Cook wrote: > I am beginning research on doing using a FPGA to implement a > digital circuit for an implantable cardio defibrillator. Due to the > nature of the product, low power consumption is a primary concern. > I was wondering if any one has any documentation or advice on > doing a low power, low frequency design using an FPGA. The chip > will only need to be clocked at a few hundred hertz. > > Any help would be appreciated. > TIA , > > Phillip Cook.Article: 10290
I have been working with a XC3142-3PP132 FPGA. I am using Xilinx's Foundation Basic (Schematic Capture design entry) design tools and am configuring the Xilinx using an Atmel AT17C128 Serial EPROM in the Master Serial Mode. My problem is that nearly everytime I burn a new program into the PROM I get different results. The Xilinx appears to configure just fine and parts of my design work fine. But if I make a change to one part of the schematic (or no changes at all) then something changes in a completely different part of the schematic that wasn't touched. All of the IPADs and OPADs are pin-locked using the LOC attribute. Some of the things that are happening are simply crazy. For instance: I have a 4-bit counter (CB4CE) with CE tied to VCC and CLR tied to GND. The first three bits work but I get no output from the 4th bit or from CEO. I also have a quadrature clock generator using an FD and an FD_1 block clocked with the same signal. The output signal from the FD block is at half the frequency of the clock signal (as expected) but the output from the FD_1 block is at the SAME frequency as the clock signal. Plus a number of other crazy and intermittant things. If I use a different Xilinx (I have three of these parts) I get identical results and reconfiguring the Xilinx doesn't seem to make a difference. So it does appear to be something in the bitstream. It's as if the schematic netlister (or something else further down the line) is randomly choosing to disconnect and/or misconnect a few of the pins each time. It's driving me insane. If anyone has ever experienced this type of behavior before or has any suggestions I would greatly appreciate them. TIAArticle: 10291
In a previous article Nick Hartl <"nhartl[no spm]"@earthlink.net> writes: : ;When you say Foundation though I tend to think not just of the place and :route tools but the front end stuff (schematics, state machine editor, ;simulator and such). I know nothing about Lunix ( outside of the usual :common knowledge stuff (free, sort of like UNIX)) but I would guess that ;porting the front end stuff would be a real mess because of all the :graphics that are part of it. Actually graphics is the easy part for the de facto standard for Unix workstations is the X-window system. The virtual graphic interface is all the same no matter which Unix machine you use. It remains to be seen whether Apple's Rhapsody (based on NeXT OS, which is based on Mach -- another unix like OS) will contain an X-windows interface. If it does, and if it also give us windows that run command shell, then I would say the greatest threat to the traditional Unix workstation makers isn't Wintel, but the revived Apple.Article: 10292
In article <355502E8.EEA3AEB6@earthlink.net>, Nick Hartl <Remove, "[no", "spm]", from, address.> wrote: >When you say Foundation though I tend to think not just of the place and >route tools but the front end stuff (schematics, state machine editor, >simulator and such). I know nothing about Lunix ( outside of the usual >common knowledge stuff (free, sort of like UNIX)) but I would guess that >porting the front end stuff would be a real mess because of all the >graphics that are part of it. If the Xilinx tools alread run on various Unix platforms (I'm not too sure, but I think they at least run on Suns) then it won't be hard to port the GUI to Linux. The only problem might be if they develop their GUI on Windows using MFC and then port to UNIX using some tool like Bristol or Mainsoft - neither of those tools support Linux yet, however, they could use the Willows TWIN API (which is free & under GPL, see: www.willows.com) to do the porting from Windows to Linux. Either way, porting the GUI should be doable - of course the best thing is to do GUIs in Java, TCL/TK or some other portable GUI toolkit to avoid being locked into the Windows platform. > >I am sure that if enough requests are heard for a Lunix place and route >tool the market will listen. BTW: it's Linux not Lunix. philArticle: 10293
Sidharta wrote:
> 1. When would you use CPLD and when would you use FPGA?
CPLD - control logic (fsms). some simple datapath stuff.
use when you need predictable timing. do not use
for XOR-intensive circuits. typically, the chips
are highly routable.
FPGAs - complex datapath stuff, slow or XOR-intensive ccts.
simple FSMs (small fan-out and small fan-in to each
state). large circuits. chips can be more difficult
to route than CPLDs (not-so-uncommon problem: have
enough logic cells, but the tools can't route it).
> 2. What are the effects of the ARCHITECTURE (macrocells, logic cells,
> routing, etc.) of both the CPLD and FPGA on the SPEED and chip AREA of the
> circuits implemented in them?
if you need high speed or good density, architecture is very important.
you would benefit from matching the target cct to the device before
starting
a new design. if you have to learn a new device though, it may be
faster
to stick with what you already know...
if attainging high speed and area use are not important to you, then
the specific architecture won't affect you much.
> 3. Is it true that the extra routing in FPGA makes it slower than CPLD?
more or less, yes.
> 4. So, which is more advantageous?
FPGAs can handle larger circuits.
CPLDs tend to dissipate significant static power.
> Oh, another question. I'm using Altera Maxplus2 CAD tool. When
> implementing state machines, is the automatically generated state
> assignment always the best one? What is the guideline in doing state
nope. it uses one-hot for FPGAs (FLEX 6000, 8000, or 10K designs)
and a dense binary encoding for everything else (MAX 7000, 9000, etc).
the best encoding is usually your own encoding, but it is not the
easiest!
> assignment, if we're to do it manually?
if your FSM has many 'branches' from a top-level state, and each
branch goes through a few states (linearly), then i find the
following scheme works well: use a one-hot encoding to represent
each branch, and a binary encoding for the few states within each
branch.
carefully designing the state assignment to match outputs (Moore
design) may help your outputs, but it may make the FSM logic
itself more complex.
guy
Article: 10294In article <6j37rs$73h$1@newman.pcisys.net>, William L. Bahn <bahn@bfe.com> writes >I have been working with a XC3142-3PP132 FPGA. I am using Xilinx's >Foundation Basic (Schematic Capture design entry) design tools and am >configuring the Xilinx using an Atmel AT17C128 Serial EPROM in the Master >Serial Mode. > >My problem is that nearly everytime I burn a new program into the PROM I get >different results. The Xilinx appears to configure just fine and parts of my >design work fine. But if I make a change to one part of the schematic (or no >changes at all) then something changes in a completely different part of the >schematic that wasn't touched. All of the IPADs and OPADs are pin-locked >using the LOC attribute. > [snipped] Do different PROMS programmed from the same bitstream give identical results? After no material change to the schematic or any settings, is the new bitstream identical to the old one? (DOS file compare) -- Keith WoottenArticle: 10295
I Made $3000 in 1 week, and you can too!!!! This WORKS! But you must follow my instructions and do everything just like I say. I had to read this a couple of times to fully understand how it works. But once you get the hang of it, it is easy. So if you need some extra cash, and would like to earn it by doing nothing, then it is worth it. I like this, because it is like I'll scratch your back if you scratch mine But to fully understand, read on....................... THIS REALLY CAN MAKE YOU EASY MONEY! A little while back, I was browsing some newsgroups and came across an article similar to this that said you could make thousands of dollars within weeks with only an initial investment of $6.00! So I thought, "OK, why not try this, if its a scam I'll only lose $6.00.". Anyway, it said that you send $1.00 to each of the 6 names and address stated in the article. You then place your own name and address in the bottom of the list at #6, and post the article in some newsgroups(There Are Thousands!) or email it to some people. No catch, that was it. The main difference between this system and others is that you have a mailing list of 6 instead of 5. This means that your average gain will be approximately 15 times higher!!! So after talking to a few people, I thought, what have I got to lose except 6 stamps and $6.00, right? But like most of us I was a little skeptical and a little worried about the legal aspects of it all. So I checked it out with the U.S. Post Office (1-800-725-2161) and they confirmed that it is indeed legal! I then invested the measly $6.00, and stamps. Well, GUESS WHAT.....within 7 days, I started getting money in the mail! I was shocked! I still figured it would end soon, and didn't give it another thought. But the money just kept coming in. In my first week, I made about $36.00 dollars. By the end of the second week I had made a total of over $1,000.00!!!!!! In the third week I had over $10,000.00 and it's still growing. This is now my fourth week and I have made a total of just over $42,000.00 and it's still coming in VERY rapidly! It's certainly worth $6.00, and 6 stamps, I spent more than that on the lottery!! Let me tell you how this works and most importantly, why it works.....also, make sure you print a copy of this article NOW, so you can get the information off of it as you need it. The process is very simple and consists of 3 easy steps: STEP 1: Get 6 separate pieces of paper and write the following on each piece of paper "PLEASE PUT ME ON YOUR MAILING LIST. + your name and address." Now get 6 US $1.00 bills (or equivalent in your local currency) and place ONE inside EACH of the 6 pieces of paper so the bill will not be seen through the envelope to prevent thievery. Next, place one paper in each of the 6 envelopes and seal them. You should now have 6 sealed envelopes, each with a piece of paper stating the above phrase, your name, your address, and a $1.00 bill. What you are doing is creating a service by this. THIS IS ABSOLUTELY LEGAL! STEP 2: Mail the 6 envelopes to the following addresses: #1 E. Balum Steinwegstraat 23 3072-SL Rotterdam Netherland; #2 M. Coban Gaullachergasse 45/1 1160 Vienna Austria #3 P. Marques 39 Fairbairn Green London SW9 7RR UK #4 ALI HARON 126 Kampong Sg.Penchala, 60000 Kuala Lumpur MALAYSIA #5 J. Haw 5th A street, Phase I Ecoland Subdivision, Davao City 8000 Philippines #6 Andres Vasquez P.O. Box 3745 Santiago Chile STEP 3: Now take the #1 name off the list that you see above, move the other names up (#6 becomes #5, #5 becomes #4, etc...) and add YOUR Name as #6 on the list. STEP 4: Change anything you need to, but try to keep this article as close to original as possible. Now, post your amended article to some newsgroups (I think there are close to 24,000 newsgroups) and/or email it to some people. remember, the more you post, the more money you make! Don't know HOW to post in the newsgroups? Well do exactly the following: --------------------------------------------------------------------------- DIRECTIONS - HOW TO POST TO NEWSGROUPS --------------------------------------------------------------------------- Step 1: You do not need to re-type this entire letter to do your own posting. Simply put your cursor at this letter, press CTRL - A Select All). At this point the entire letter should be highlighted. Then press CTRL - C (Copy) this will copy the entire highlighted document into your computer’s memory. Step 2: Open a blank 'notepad' file and place your cursor at the top of the blank page. Then press CTRL-V (Paste). This will paste a copy of the letter into notepad so that you can add your name to the list. Remember to eliminate the #1 position, move everyone up a spot (re-number everyone elses positions), and add yourself in as #6. Step 3: Save your new notepad file as a .txt file. If you want to do your postings in different sittings, you'll always have this file to go back to. --------------------------------------- FOR NETSCAPE USERS: --------------------------------------- Step 4: Within the Netscape program, go to the pull-down window entitled 'Window' select 'NetscapeNews'. Then from the pull down menu 'Options', select 'Show all Newsgroups'. After a few moments a list of all the newsgroups on your server will show up. Click on any newsgroup you desire. From within this newsgroup, click on the 'TO NEWS' button, which should be in the top left corner of the newsgroups page. This will bring up a message box. Step 5: Fill in the Subject. This will be the header that everyone sees as they scroll through the list of postings in a particular group. Step 6: Highlight the entire contents of your .txt file and copy them using the same technique as before. Go back to the newsgroup 'TO NEWS' posting you are creating and paste the letter into the body of your posting. Step 7: Hit the 'Send' Button in the upper left corner. You're done with your first one! Congratulations... ----------------------------------------------- INTERNET EXPLORER USERS: ----------------------------------------------- Step 4: Go to newsgroups and select 'Post an Article'. Step 5: Fill in the subject. This will be the header that everyone sees as they scroll through the list of postings in a particular group. Step 6: Highlight the entire contents of your .txt file and copy them using the same technique as before. Go back to the newsgroup 'TO NEWS' posting you are creating and paste the letter into the body of your posting. Step 7: Hit the 'Send' Button in the upper left corner. You're done with your first one! Congratulations... ---------------------------------------------------------------------------- --------------------- THAT'S IT! All you have to do is jump to different newsgroups and post away, after you get the hang of it, it will take about 30 seconds for each newsgroup! **THE MORE NEWSGROUPS YOU POST IN, THE MORE MONEY YOU WILL** **MAKE!!** That's it! You will begin receiving money from around the world within days! You may eventually want to rent a P.O.Box due to the large amount of mail you receive. If you wish to stay anonymous, you can invent a name to use, as long as the postman will deliver it. **JUST MAKE SURE ALL THE ADDRESSES ARE CORRECT.** Now the WHY part: Out of 200 postings, say I receive only 5 replies (a very low example). So then I made $5.00 with my name at #6 on the letter. Now, each of the 5 persons who just sent me $1.00 make 200 postings, each with my name at #5 and only 5 persons respond to each of the original 5, that is another $25.00 for me, now those 25 each make 200 posts with my name at #4 and only 5 replies each, I will bring in an additional $125.00! Now, those 125 persons turn around and post 200 with my name at #3 and only receive 5 replies each, I will make an additional $626.00! OK, now here is the fun part, each of those 625 persons post 200 letters with my name at #2 and they each only receive 5 replies, that just made me $3,125.00!!! Those 3,125 persons will all deliver this message to 200 newsgroups with my name at #1 and if still 5 persons per 200 newsgroups react I will receive $15,625,00! With a original investment of only $6.00! AMAZING! And as I said 5 responses is actually VERY LOW! Average is probable 20 to 30! So lets put those figures at just 15 responses per person. Here is what you will make: at #6 $15.00 at #5 $225.00 at #4 $3,375.00 at #3 $50,625.00 at #2 $759,375.00 at #1 $11,390,625.00 When your name is no longer on the list, you just take the latest posting in the newsgroups, and send out another $6.00 to names on the list, putting your name at number 6 again. And start posting again. The thing to remember is, do you realize that thousands of people all over the world are joining the internet and reading these articles everyday, JUST LIKE YOU are now!! So can you afford $6.00 and see if it really works?? I think so... People have said, "what if the plan is played out and no one sends you the money? So what! What are the chances of that happening when there are tons of new honest users and new honest people who are joining the internet and newsgroups everday and are willing to give it a try? Estimates are at 20,000 to 50,000 new users, every day, with thousands of those joining the actual internet. Remember, play FAIRLY and HONESTLY and this will work. You just have to be honest. Make sure you print this article out RIGHT NOW, also. Try to keep a list of everyone that sends you money and always keep an eye on the newsgroups to make sure everyone is playing fairly. Remember, HONESTY IS THE BEST POLICY. You don't need to cheat the basic idea to make the money!! GOOD LUCK to all and please play fairly and reap the huge rewards from this, which is tons of extra CASHArticle: 10296
William L. Bahn wrote: > I have been working with a XC3142-3PP132 FPGA. I am using Xilinx's > Foundation Basic (Schematic Capture design entry) design tools and am > configuring the Xilinx using an Atmel AT17C128 Serial EPROM in the > Master > Serial Mode. > > My problem is that nearly everytime I burn a new program into the PROM > I get > different results. The Xilinx appears to configure just fine and parts > of my > design work fine. But if I make a change to one part of the schematic > (or no > changes at all) then something changes in a completely different part > of the > schematic that wasn't touched. All of the IPADs and OPADs are > pin-locked > using the LOC attribute. > > Some of the things that are happening are simply crazy. For instance: > > I have a 4-bit counter (CB4CE) with CE tied to VCC and CLR tied to > GND. The > first three bits work but I get no output from the 4th bit or from > CEO. > > I also have a quadrature clock generator using an FD and an FD_1 block > > clocked with the same signal. The output signal from the FD block is > at half > the frequency of the clock signal (as expected) but the output from > the FD_1 > block is at the SAME frequency as the clock signal. > > Plus a number of other crazy and intermittant things. If I use a > different > Xilinx (I have three of these parts) I get identical results and > reconfiguring the Xilinx doesn't seem to make a difference. So it does > > appear to be something in the bitstream. It's as if the schematic > netlister > (or something else further down the line) is randomly choosing to > disconnect > and/or misconnect a few of the pins each time. It's driving me insane. > > If anyone has ever experienced this type of behavior before or has any > > suggestions I would greatly appreciate them. > > TIA Bill, what you are experiencing is definitely not normal. Since DONE must go High, I assume that the configuration process itself works properly. Do you have a synchronous design, using global clock(s)? Asynchronous designs can be very nasty. You can analyze a specific item, e.g. the fourth counter bit not toggling, in XACT, the graphics editor. It shows every internal connection. Other thoughts: try hot and cold, that pinpoints parametric problems ( I mean really hot, like 100 degres and really cold, minus 40 degr using cold spray). And, although I have not heard anything bad about Atmel SPROMs recently, there is always that doubt in my mind... I am out-of-town for 10 days, but I bet that you will find your problem, and perhaps laugh about the reason for it. "The more mysterious the problem, the more trivial the cause" Peter Alfke, Xilinx ApplicationsArticle: 10297
Thanks for the tip. I'm still pretty new to VHDL. NestorArticle: 10298
Is there anybody who can send me ( or tell me where to find ) the programming algorithms for PALCE22v10 / GAL22v10 devices ? Thanks. Vito VenezianiArticle: 10299
>another unix like OS) will contain an X-windows interface. If it does, >and if it also give us windows that run command shell, then I would say >the greatest threat to the traditional Unix workstation makers isn't >Wintel, but the revived Apple. It would be, if a lot of people actually had Apple hardware. Certainly here in the UK, Apple are virtually unknown outside the print services and graphical design industry - very few "engineer" types use them. Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.
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