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A sales rep told me about DynaChip about two days ago. DynaChip's main claim to fame is that they are supposed to make the fastest FPGA's. Apparently the speed costs though, I think the parts are about twice as much as a comparable Xilinx. So if you can make your function work in Lucent, Xilinx, etc. that can save you some money DynaChip Corporation 1255 Oakmead Parkway - Sunnyvale, California 94086 Phone: 408-481-3100, Fax: 408-481-3136 eMail: support@dyna.com - Internet: http://www.dyna.comArticle: 10726
Thilo Thiessenhusen wrote: > Vdd > | > --- > | | > | | R > --- > _ | _ > OBUFT _>--------o---------<_ IBUF > > What is the maximum resistance that guarantees a valid input level > at any time? Would 100K be O.K.? > > [The actual configuration is a bit more complicated since there is > a sensor between OBUFT and the dot, which can switch between > open and about 10-20K]. > > Thilo > The relevant parameter is the input leakage current, specified as being less than +/- 10 microamps. This would give a 1 V drop over a 100 kilohm resistor, just barely acceptable in a 5-V system. In reality, the input leakage current is far less, closer to 100 nA than to one microamp, which means that even several hundred kilohms would assure proper pull-up. ( But this is not formally guaranteed, because we avoid the testing of very low currents, because it takes too much test time ). Of course this means that you must deactivate the internal pull-up resistor, which by default appears on every input. Obviously, such a high-impedance input can easily be disturbed by capacitive crosstalk on the pc-board, and I would also advise to keep the two neighboring pins on the chip very quiet, to avoid crosstalk in the leadframe. If the application is slow, you can decouple the input capacitively to ground, which would eliminate all these potential crosstalk problems. Peter Alfke, Xilinx ApplicationsArticle: 10727
Does anyone have behavioral VHDL models of the Xilinx XC6000 primitives used with velab? -- Jim Frenzel, Assoc. Professor phone: (208) 885-7532 Electrical Engineering, BEL 213 fax: (208) 885-7579 University of Idaho, MS 1023 email: jfrenzel@uidaho.edu Moscow, ID 83844-1023 USA www: http://www.uidaho.edu/~jfrenzelArticle: 10728
Lars, We do low volume ASICs. I would advise prototyping with the FPGA of your choice and once it is functional we can give you a much faster, lower cost masked device with Zero NRE. In our technology you can run at 100Mhz plus with ease. Regards, Kash Johal MacroTech Semiconductor 408 360 0430 Lars <larsher@online.no> wrote in article <35810460.729A@online.no>... > Hi, > What are the fastest and biggest FPGA available in samples within next > few months? > > The reason for me asking is that we have a large design that has to run > fast, 66MHz. I know this does not sound too hard, but within these 15ns > a 64 bit magnitude comparing (data greater or less than a register > value) and 180 bit equality comparing has to be done. This plus alot of > other logic adds up to over 100K ASIC gates. So the FPGA has to be big. > We can accept pipelineing to some extent, but this requires also more > resources in registers to hold data. > > The alternative is of cource ASIC, but our vloumes are low, so FPGA > would be great. > > Has anyone done 64 bit magnitude comparator in an FPGA before? > Does anyone have a feel about if this is feasable or not in an FPGA? > Any input from you FPGA experts would be nice. >Article: 10729
Don Husby wrote: > > larsher@online.no wrote: > > The reason for me asking is that we have a large design that has to run > > fast, 66MHz. I know this does not sound too hard, but within these 15ns > > a 64 bit magnitude comparing (data greater or less than a register > > value) and 180 bit equality comparing has to be done. This plus alot of > > other logic adds up to over 100K ASIC gates. So the FPGA has to be big. > > We can accept pipelineing to some extent, but this requires also more > > resources in registers to hold data. > > Lucent does pretty good with wide functions. They claim to have their > 3T80 part available now. > Adding up the numbers for the -6 Speed grade, it can do a 64-bit arithmetic > function in ~13ns. If you include routing delays, this will probably > exceed your 15ns requirement. > > However, it's very easy to pipeline this function. Registers are essentially > free. A 2-deep 64-bit pipelined comparator with input and output > registers would take 9 PFU (Programmable Funcion Units) which is about > 2% of the 3T80. (A single PFU can be an 8-bit comparator with 8-bit register > at its input and 1-bit register at its output) > My guess is that this could easily run at 100MHz with their -5 speed grade. > > A 180-bit pipelined equality comparator would also have similar performance. > Each PFU can do a 16-bit equality-compare. SLICs (Supplimental Logic and > Interconnect Cells) can be used to OR the outputs. My guess is that it would > take less than 15 PFU to implement this function and could possibly be > done in a single 15ns cycle. It would take 23 PFU if you want to include a > 180-bit input register. The 3T80 has 484 PFU arranged in a 22x22 array. I could kick myself... HARD! I haven't looked at the Lucent stuff lately because they are hard to deal with when you are a small volume user. But I just looked at their web site and found that they have a 3T+ series that includes a PCI bus interface! We could have dropped an entire 208 pin chip from our design by using their 3T+But then I don't think I would have gotten the level of support that I am getting from Xilinx. As I said before, Lucent pretty much ignores the smaller accounts. I would have loved to have tried their chip though. -- Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 10730
On Fri, 12 Jun 1998 17:14:44 +0300, "Arie Zychlinski" <ariez@ibm.net> wrote: You might want to check out : Surviving the ASIC Experience Online Price: $72.00 By Schroeter, John; Softcover; 205 Pages Published by Prentice Hall; 11/1991; ISBN: 0138778388 There's some info about it at Computer Literacy - www.clbooks.com Here's a link to the title : http://www.clbooks.com/sqlnut/SP/search/gtsumt?source=&isbn=0138778388 If you end up buying this or any other title(s) at Computer Literacy, Use this code : FriendOfChrisH when you place your order. It will give you an additional 15% discount on anything you buy. Just enter this in the "Let us know how you found us or enter referral code" box. (This code will work for anyone) I hope this info is helpful. Chris (at) Huebner (dot) com >I am an experienced user of FPGAs, doing also conversion to ASIC from FPGAs. >Yet, (as the conversion is done in Orbit, AMI, ...) I have lack of knowledge >on the ASIC field (such as , but NOT only: the processes during the >production, the impact on using gate-array vs. standard-cell and other >issues.) > >I am looking for a recommendation on a tutorial book. Can any one suggest >one ? > >Thank you in advance. > > >Article: 10731
LAnder7735 wrote: > DynaChip's main claim to fame is that they are supposed to make the fastest FPGA's. They did't have fast carry chains of Xilinx, so they were slower than Xilinx for things that could use the fast carry chains. Didn't work for my design, but Dynachip's FPGAs have some neat features, might be worth a look for some designs. -- Phil Hays "Irritatingly, science claims to set limits on what we can do, even in principal." Carl SaganArticle: 10732
There are various progs around which can convert Jedec into equations. (I have never used one myself). What you do after that I am not clear about. Since you cannot get these old parts any more, why do you need a PLD assembler which supports them? I would imagine my old freebie CUPL3 supports them but as I say if you cannot get them... >I am tasked with understanding an old design that used the Altera EP1210, >which is equivalent to the Intel 5C121. Both of these PLDs are long since >discontinued. I have the Jedec files but no logic equations. > >I have PLDShell versions 4 and 5, both of which appear to be too new to >understand the EP1210/5C121. Altera's tech support had a datasheet for the >part, but no old software available. > >Can anyone point me to, or send me, a version of PLDShell old enough to cover >this part, or another means of disassembling the Jedec file to recover the >logic equations? Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 10733
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Article: 10734Hello ASIC decision maker: we are ASIC design house that have expertize starting from FPGAs to all the way to full custom chips. If you need ASIC design services please visit us at following URL.We also specialize porting your existing FPGA design to full ASIC. http://www.iss-us.com/AsicTeam.htm Thanks. Khan.Article: 10735
Please visit and comment on my Electronics and Electrical Engineering pages located at: http://www.users.globalnet.co.uk/~metad/eee.htm Containing: Introduction to EEE Resources (over 100 web links) Employment Statistics and newspaper excerpts Engineering Poems, Quotations and Jokes EEE at Glasgow University In addition my homepage (http://www.users.globalnet.co.uk/~metad/) contains: A section about me My CV A James Bond Section A guestbook 500+ cool links in the "new look" bookpage Cool background MIDI and graphics Literary quotations Photo Album Awards Page Poems... Basically, something for everyone! PLEASE VISIT VIA MY MAIN HOMEPAGE ADDRESS! Please send you comments via the guestbook or by Email (containing your full name and Email and webpage addresses) and visit via http://www.users.globalnet.co.uk/~metad/. Thanks Scott Johnston metad@globalnet.co.ukArticle: 10736
Yeah right! Make 6 other suckers sign up 6 each more suckers ad infinitum. How many friends and family members are gonna fall for this one?? So Mr Klukan has to resort to newsgroup sales to get Admax off his back. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Article: 10737
In article <6m1ssl$fsf$1@news-1.news.gte.net>, Keith Christensen <radiopro@gte.net> wrote: >Yeah right! Make 6 other suckers sign up 6 each more suckers ad infinitum. >How many friends and family members are gonna fall for this one?? So Mr >Klukan has to resort to newsgroup sales to get Admax off his back. > >~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >From: beaver@usa.net (J Klukan) >Newsgroups: comp.arch.embedded,comp.arch.fpga,comp.arch.storage >Subject: Free Computer (Read--Easy, No money down) >Date: Fri, 12 Jun 1998 06:07:41 GMT >X-Newsreader: Forte Free Agent 1.0.82 >NNTP-Posting-Host: 208.132.56.50 >Message-ID: <3580c820.0@news.bigsky.net> [snip] [I won't do him the "service" of spreading his "nonsense" by including a copy of it here...] >-Jeremy > >PS: This is not spam. I have posted it to newsgroups that I have >found computer-related material in. Please do not criticize me for >that. Sorry, "Jeremy", but *you* don't define what "is" and "is NOT" spam. The charters of the individual newsgroups define that -- something you're obviously clueless about. MLM and pyramid schemes are intended for suckers. Please go suck someWHERE and someTHING *else*! --donArticle: 10738
I think that Jeremy would appreciate hearing from each of us. Why not send him an email telling him just what you think of his offer? Don Yuniskis wrote: > > In article <6m1ssl$fsf$1@news-1.news.gte.net>, > Keith Christensen <radiopro@gte.net> wrote: > >Yeah right! Make 6 other suckers sign up 6 each more suckers ad infinitum. > >How many friends and family members are gonna fall for this one?? So Mr > >Klukan has to resort to newsgroup sales to get Admax off his back. > > > >~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > >From: beaver@usa.net (J Klukan) > >Newsgroups: comp.arch.embedded,comp.arch.fpga,comp.arch.storage > >Subject: Free Computer (Read--Easy, No money down) > >Date: Fri, 12 Jun 1998 06:07:41 GMT > >X-Newsreader: Forte Free Agent 1.0.82 > >NNTP-Posting-Host: 208.132.56.50 > >Message-ID: <3580c820.0@news.bigsky.net> > > [snip] > > [I won't do him the "service" of spreading his "nonsense" by > including a copy of it here...] > > >-Jeremy > > > >PS: This is not spam. I have posted it to newsgroups that I have > >found computer-related material in. Please do not criticize me for > >that. > > Sorry, "Jeremy", but *you* don't define what "is" and "is NOT" spam. > The charters of the individual newsgroups define that -- something > you're obviously clueless about. > > MLM and pyramid schemes are intended for suckers. > > Please go suck someWHERE and someTHING *else*! > > --don -- Rick CollinsArticle: 10739
Rene Kellenbach wrote: > > Anybody over here with hands-on experience with the > Lattice ispLSI series? > A lot of "us" do. > After many years of designing with simple PLD's, > I am considering to move to something better. > In-system programmability is an important factor, > so the Lattice stuff seems pretty interesting. > Xilinx CPLD's, and Cypress have ISP too. > What is the best software package to use this > stuff? I have fooled around with the Lattice starters > kit for I while, but I am not impressed. What I would > like is a relatively inexpensive package that allows > mixed HDL and schematic entry. > Once I started using HDL, I quit using schematics for FPGA's and CPLD's. Too bulky, and harder to document. I > How about the Lattice ispVHDL/Viewlogic package? > Or the Synario/ABEL software. Which is best and why? > (I have some hands-on experience with ABEL, but not > VHDL. How difficult is this to learn?). > Depends on your mind-set. Some take to it like ducks to water. Some never grasp it. > What about the performance of the chips? The timing > model seems much simpler than FPGA's. True. Lattice has some quirks, but they all do. > Do I need a timing simulator or will a simple calculation > by hand suffice? By hand (for CPLD's) will be more accurate than the low-end timing simulators. They really can be treated like a lot of 22V10's in one box. > What kind of system speed are we talking about? Most > companies talk about flipflop toggle rates only, but > what can be expected in real life? > > Thanks. > > Rene Kellenbach > The Netherlands Rene, The best VALUE I've seen is the Cypress WARP package. US$ 100 gets you a decent introductory text book, and a full on VHDL compiler. The only restrictions are it only supports their parts, and it only does a functional simulation of a fully compiled part. For US$ 175, you get the book, compiler, sample parts and a programming probe. Gary.Article: 10740
Gary Helbig <ghelbig@slip.net> wrote in article <357F2750.2B3F@slip.net>... > I won't get into the VHDL vs/ Verilog argument. But, AHDL is good > for Altera-made chips only, which limits its usefulness. > > AHDL also has poor documentation, and a few bugs. > > In other words, Verilog, VHDL; pick one. Or both. AHDL, stay away. AHDL is one of the easiest to use HDL's and has excellent documentation and on-line help. The only disadvantage is that it is vendor specific. Daniel Lang dbl@hydra0.caltech.eduArticle: 10741
Gary, >> What is the best software package to use this >> stuff? I have fooled around with the Lattice starters >> kit for I while, but I am not impressed. What I would >> like is a relatively inexpensive package that allows >> mixed HDL and schematic entry. >> > > Once I started using HDL, I quit using schematics > for FPGA's and CPLD's. After my first posting, lots of people told me to forget about schematic entry - most s/w packages seem a real PITA when it comes to mixed entry. >> Do I need a timing simulator or will a simple calculation >> by hand suffice? > > By hand (for CPLD's) will be more accurate than > the low-end timing simulators. They really can > be treated like a lot of 22V10's in one box. Agreed, the timing model of CPLD's is pretty straightforward. > The best VALUE I've seen is the Cypress WARP package. > > US$ 100 gets you a decent introductory text book, and > a full on VHDL compiler. The only restrictions are > it only supports their parts, and it only does a > functional simulation of a fully compiled part. > > For US$ 175, you get the book, compiler, sample parts > and a programming probe. Hmm...I have already got the Cypress WARP package, but mine is over 3 years old. I wasn't too impressed by then, but I will take another look at what Cypress has to offer these days. Thanks, Gary! Rene Kellenbach The Netherlands.Article: 10742
rkoblish@my-dejanews.com wrote:
>
>I am tasked with understanding an old design that used the Altera EP1210,
>which is equivalent to the Intel 5C121. Both of these PLDs are long since
>discontinued. I have the Jedec files but no logic equations.
>
>I have PLDShell versions 4 and 5, both of which appear to be too new to
>understand the EP1210/5C121. Altera's tech support had a datasheet for the
>part, but no old software available.
>
>Can anyone point me to, or send me, a version of PLDShell old enough to cover
>this part, or another means of disassembling the Jedec file to recover the
>logic equations?
I've got a copy of V3.0 of "PLDShell Plus/PLDasm" (March 1993). The
manual says this includes a utility program ("disassembler") which will
process a Jedec file into PDShell (*.pds) source. As has been pointed
out, there are other programs out there which will convert Jedec to
equations, and it isn't that difficult to do by hand (although the
macrocell configuration fusing can be quite fun, particularly when the
manufacturer doesn't state anywhere what the macrocell fusing is!).
The "1210/5C121" isn't listed as supported by PLDShell V3.0. Just the
usual 300/600/900/1800 types plus 22V10, 5C220 etc. According to one of
my textbooks, the 40 pin EP1200 was introduced in 1984, had 12 inputs,
24 output cells, 4 buried registers, dual clocks and variable product
term distribution. Output cell configurations were: combinational or
registered output with local enable, pin feedback and selectable
polarity. I strongly suspect that the 1200/1210 were superseded by the
900/910, but without having upwards Jedec compatibility.
With the manufacturer's data sheet, you should be able to translate
manually the dependencies of outputs upon inputs, then set up a test
regime to determine things like clock dependencies, polarities and the
like. Have you checked the Jedec to see if it includes Jedec-format
test vectors? If so, then you can inspect to see which pins are
input-only, which output-only, whether any are I/O, whether any are
unused. This all helps to limit the amount of work in unscrambling the
Jedec fusing.
Hope this helps, but suspect it doesn't - sorry. I've checked some
other obsolete PLD software packages without success: PLPL, OPAL Jr, a
1991 version of ABEL and a 1987 evaluation version of ALTERANS. The
last named actually refers to the 1210, but only in the negative sense
that the software (presumably when upgraded from evaluation-only to
full-function) can't support the programmable clock feature.
--
Tim Forcer tmf@ecs.soton.ac.uk
Department of Electronics & Computer Science
The University of Southampton, UK
The University is not responsible for my opinions
Article: 10743I wrote: > However, it's very easy to pipeline this function. Registers are essentially > free. A 2-deep 64-bit pipelined comparator with input and output > registers would take 9 PFU (Programmable Funcion Units) which is about > 2% of the 3T80. (A single PFU can be an 8-bit comparator with 8-bit register > at its input and 1-bit register at its output) > My guess is that this could easily run at 100MHz with their -5 speed grade. After further consideration, this is incorrect. It's not so easy to do a pipelined arithmetic comparator. I think it will be possible to do the entire 64-bits in a single 15 ns cycle. The data sheet doesn't give the register-to-carry timing, so you must verify this using the timing tools. Maybe a Lucent salesperson can do that for you. In the worst case, it would take 2 cycles, so you would need to ping-pong between two identical circuits. This would still only take 16 PFU or 3.3% of a 3T80. -- Don Husby <husby@fnal.gov> Phone: 630-840-3668 Fermi National Accelerator Lab Fax: 630-840-5406 Batavia, IL 60510Article: 10744
Kenneth Johanssson <Kenneth.Johansson@ebc.ericsson.se> wrote in article
<358507c9.861736371@news.ericsson.se>...
> But is there some standard whay to write code so the
> compilers(analyser) know what I really mean. I ask as I have problem
> to get my code understood by two different compilers.
>
> What iam trying to do is a shiftregister thats 8 bit wide and 4 step
> deep. And map this into an altera flex10k device.
>
> This device is made of a 4bit lookup and a flipflop with
> set/reset/enable. This shiftreg would take 32 of these lcell as they
> are called.
>
> My first try was
> ---------
> ENTITY pipe IS
> PORT(
> clock : IN BIT;
> enable : IN BIT;
> data : IN BIT_VECTOR(7 DOWNTO 0);
> head3 : OUT BIT_VECTOR(7 DOWNTO 0);
> head2 : OUT BIT_VECTOR(7 DOWNTO 0);
> head1 : OUT BIT_VECTOR(7 DOWNTO 0);
> ouput : OUT BIT_VECTOR(7 DOWNTO 0));
> END pipe;
>
> ARCHITECTURE synt OF pipe IS
>
> BEGIN
> PROCESS(clock)
> VARIABLE h1,h2,h3 : BIT_VECTOR(7 DOWNTO 0);
> BEGIN
> if clock'EVENT and clock='1' AND enable ='1' then
> ouput <= h1;
> head1 <= h2;
> head2 <= h3;
> head3 <= data;
> h1:=h2;
> h2:=h3;
> h3:=data;
> END IF;
> END PROCESS;
> END synt;
> -----------
> SYNPLIFY: Makes exaktly what I want but I get 7 of the following
> warnings.
>
> Feedback mux created for signal ouput[7:0]. Did you forget the
> set/reset assignment for this signal?
>
> Well what exactly dose they mean with that. I expected a mux but how
> do I write to get this warning to disapear. I dont want to leave code
> that create compile time warnings.
>
>
> Maxplus:
> Gets totally confused and refuses to compile.Complaining of no clock
> edge.
> I change "if clock'EVENT and clock='1' AND enable ='1' then" to
> "if clock='1' AND enable ='1' then" Then I get thru the compiler and
> no warings. BUT this makes only combinatorial logic. and uses 24
> lcells more than I want. So maxplus could not find any clock in this
> type of construct. Synplify compile it but warns that is has created
> latches.
>
> so a
> process (clock)
> if clock='1' and <whateverer>
>
> seams to mean no clock. How this is i dont really now as I have clock
> in the sesitivity list and then check if it is '1'. This can only mean
> a clock edge (to me anyway).
>
> -------------
> As am more or less forced to use maxplus at this time I need to find
> something that works for maxplus but is generic enough to works on
> other compilers to. After 10-15 different ways (toke some time to
> discover that maxplus really dont handle variables any good) I have
> ended up with this.
>
> ARCHITECTURE synt OF pipe IS
> signal h1,h2,h3 : BIT_VECTOR(7 DOWNTO 0);
> BEGIN
>
> PROCESS(clock, enable)
> BEGIN
> if enable = '0' then
> null;
> elsif clock'event and clock='1' then
> ouput <= h1;
> h1 <= h2;
> h2 <= h3;
> h3 <= data;
> END IF;
> END PROCESS;
>
> head1<=h1;
> head2<=h2;
> head3<=h3;
> end synt;
>
> This will do what I want in maxplus and in synplify. The only thing is
> that synplify is complaining again on creation of mux and set/reset
> signal.
>
>
> OK now this is NOT my first try and need some whay to understand why
> this works and not all my other tries.(well this is actually not my
> idea got it from altera)
>
> Anyone care to explain to me how Iam suposed to think when Iam using
> vhdl. Now iam obviously doing something wrong. 10% of my time to think
> what i need to do and 90% to get the compiler to understand. Normally
> I use a development tool to decrease the time.
>
Kenneth, To answer your first question: no there is no "standard" way to do
what you want. A standard for synthesizable VHDL is in the works but until
then the code is somewhat open to interpretation. There usually is a "common"
way to get most constructs which most synthesizers support. The common way to
do what you want (i.e. registers with clock enable) is this: (using your code)
PROCESS(clock, enable)
BEGIN
if clock'event and clock='1' then
if (enable = '1') then
ouput <= h1;
h1 <= h2;
h2 <= h3;
h3 <= data;
end if;
end if;
END PROCESS;
This works for Synplify, Synopsys and many other synthesizers. When used with
Altera or Xilinx parts, this code acutally uses the clock enable input of the
DFFE in the Lcell which is what you want for minimal logic and best
performance. The problem is that Altera's synthesizer uses this "uncommon"
(can't really say non-standard) way of specifying registers with clock enable:
(the way you found)
PROCESS(clock, enable)
BEGIN
if enable = '0' then
null;
elsif clock'event and clock='1' then
ouput <= h1;
h1 <= h2;
h2 <= h3;
h3 <= data;
END IF;
END PROCESS;
It will not recognize the first process as a clock enable and thus will not use
the clock enable pin in the DFFE. It builds a wasteful and slower mux-type
structure instead. At least this was the case when I was using Maxplus2
several versions ago. And Synopsys or Synplify do not really do the right
thing for this second process (i.e. they don't recognize the clock enable) and
you get an incication of the wasteful construct they are trying to build by the
warning message you describe. So, if nothing has changed with the software
since I used it, then you are stuck with two incompatible ways of specifying
clock enabled logic. I'm guessing that the reason you need your code to
complile for both Maxplus2 and Synplify is because you want to evalutate
Synplify vs. Maxplus2? This is why I had this exact problem. What I had to do
was take a snapshot of the Altera code and then hand convert all the clock
enable constructs to my first process so that I could fairly evaluate Synplify
and Synopsys. It was a pain. I told Altera at the time that I thought they
should really support the first construct since that is by far how it is
commonly done, so try that first on the remote chance that Maxplus2 recognizes
it now. Hope this helps.
--
Rich Iachetta
IBM Corporation
iachetta@us.ibm.com
Article: 10745Lars wrote: > Hi, > What are the fastest and biggest FPGA available in samples within next > > few months? > > The reason for me asking is that we have a large design that has to > run > fast, 66MHz. I know this does not sound too hard, but within these > 15ns > a 64 bit magnitude comparing (data greater or less than a register > value) and 180 bit equality comparing has to be done. This plus alot > of > other logic adds up to over 100K ASIC gates. So the FPGA has to be > big. > We can accept pipelineing to some extent, but this requires also more > resources in registers to hold data. > > The alternative is of cource ASIC, but our vloumes are low, so FPGA > would be great. > > Has anyone done 64 bit magnitude comparator in an FPGA before? > Does anyone have a feel about if this is feasable or not in an FPGA? > Any input from you FPGA experts would be nice The fastest Xilinx parts are the XC4000XL devices, and their fastest members are the -08 speed grade, which is just being announced. ( 08 sytands fro something like 0.8 ns delay through a look-up table, so these devices are FAST)The moment you allow pipelining, speed is no longer an issue. It makes a big difference whether you compare against a constant ( i.e. a value that will not change for several seconds or more), or whether you must compare against a variable, which can change every clock cycle. That doubles the complexity, at least in look-up-table based FPGAs. With pipelining, I am sure that your design can be implemented in an XC4000XL device. Peter Alfke, Xilinx Applications.Article: 10746
Is there anybody who can send me ( or tell me where to find ) the programming algorithms for PALCE22v10 / GAL22v10 devices ? Thanks. Vito VenezianiArticle: 10747
Call me I can source any board level component. New or obsolete. RAZ SEMICONDUCTORS 6525 VANDEN ABEELE ST.LAURENT QUEBEC H4S 1S1 CANADA 1-514-334-2447 TEL 1-514-334-7794 FAX dackman@razsemi.comArticle: 10748
Hi! I'm working on multiplier architectures and i'd like to know if it possible to generate the Wallace tree structure using only VHDL code, or a Wallace tree generator (written perhaps in C) has to be used? Does anyone know if there any Wallace tree VHDL models available ? Any Wallace tree generators ? Any related literature? If anyone has any information I wouLd appreciate it. ThanksArticle: 10749
Mario Porrmann <porrmann@hni.uni-paderborn.de> wrote:
>Hello,
>
>I want to subscribe the E-mail Synopsys Users Group
>
>Mario Porrmann
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