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*** Prefixed Primal Scream: AAAAAAAAggghhh!!
Not the GATE COUNT QUESTION!
Mr. Yadav,
Yes, Gate Count is pretty much vendor and technology specific.
Use it only as a #rough# measure of a devices' capacity. It certainly
does not address I/O pin requirements or other needs. It
Usable Gate Count is a better measure, but still not entirely accurate.
If you can, use this instead of the Gate Count figure.
The best measure is still post-facto: will it fit MY design.
Once you have a little more experience in working with a technology, you
will get a better feel for predicting which device(s) you need for a new
design.
And design styles make a big difference in what you can stuff into
a device. e.g. One-Hot is usually better for Fine-grained versus
Grey-coded for Coarse-grained. Or correct use of Hard-macros versus
making your own unoptimized logic. etc.
--Richard Vireday
(not speaking for Intel)
yadav@cse.iitb.ernet.in (Navneet S Yadav) wrote:
>hi,
> sorry if this has been asked before.
>
> most of the fpga databooks (xilinx, altera, actel etc)
>mention their chip densities in terms of gate count. exactly what is the
>definition of gate in this ? does it refer to a basic gate such as a nand
>or something more complicated ? i have heard somewhere that the basic
>notion of gate is vendor specific. in this case how do make a true
>comparision of chips from two different vendors ?
>
> also some vendors mention usable gate count and some of them
>don't. how important is the usable gate count figure ?
>
> email replies will be appreciated. i will post a followup
>containing summary of the replies.
>
>thanks,
>navneet yadav
>
>email:yadav@cse.iitb.ernet.in
Article: 4101We are looking for designers with 2+ years experience in FPGA, VLSI or ASIC development. Cadence, Menor and Viewlogic experience would be helpful! Salary in the High Five Figures, Location is Washington D.C. area. Must be U.S. Citizen. Reply to: Alex Simmons at hdhunter@usaor.netArticle: 4102
If anyone else is interested (seeing as Honest Earnest here forgot his email address), this came from firstnations.ca. I don't know Earnest's email but I do know that fnia@firstnations.ca is the contact for this site. I can't guarantee he actually has an account there, but that appears to be the origination of the posting. Chris Ernest, Aleixandre wrote: > [Much spam removed] > * 5. Ernest Aleixandre > * 108 Cedar Meadow Drive > * Regina, Saskatchewan, Canada, S4X 3J6 > * > *********************************************************************** > This works, I did it and have already received $682.00 in the past week. > ************************************************************************Article: 4103
Andrew Phillips wrote: > > Greetings all, > > I am interested to hear some responses from other designers about which > FPGA design tools they use. > > I am currently using the following tools for Xilinx FPGA design: > > design entry - MGC Design Architect (schematics) > > functional simulation - MGC QHPro (mixed VHDL/schematics simulation) - > I use Mentor's gen_arch utility to generate an entity and architecture > for the top-level schematic I am simulating and then use VHDL testbench > files to provide stimulus. > > map/place/route - Neocad foundry v7 > > timing simulation - MGC QHPro - I create an EDIF file from my placed > and routed Neocad <design>.ncd file, create a design viewpoint using > Mentor's ENREAD utility and then create a schematic of the post-layout > design using Mentor's SG schematic generator utility. Then I need to use > gen_arch to create an entity and architecture for the entire device and > use VHDL testbench files to do post-layout simulation. we're using its qsim 2 and its pc-based cousin (mti v-system). we had a qvhdl-pro loaner which semed to work well when we had it. very nice for mixed schematic/hdl designs and verification in the absence of vendor-supplied vital libraries (which continues to be the case for xilinx). > I have not tried using recent XACT map/place & route software as my > vendor suggested that its performance was not as good as the Neocad > tools that we had already purchased - I am still waiting for the > integrated XACT/Neocad tools. (Anyone know when they will be available - > are they already available?) > > I am planning to use Mentor's Autologic 2 to handle VHDL design entry > rather than using schematics. What pitfalls have others that have done > this found?? if you're doing a high performance design, you should consider the use of the B.2 release of Al2 which i'm told will be shipping in the US on september 24. this release will support timing-based optimization. surprisingly, prior releases of the xilinx AL2 libraries, including the current version, do not support the ability to specify timing constraints. you'll probably need to download the synthesis library for B.2 off of mentor's ftp-supportnet site (that's what i did for the A.4 libraries). so far, we've been synthesizing state machines using only area optimization under A.4. this has been satisfactory since we're working on a low-speed design. one issue i have not been able to resolve yet is whether xilinx will "offically" support the B.2 release when it comes out, and whether the xilinx kit will work with B.2 at all. this is difficult for me to assess because i don't know if the mentor tools used by the xilinx wrapper programs have changed significantly. definitely contact your reps on this one. there are *two* autologic-based synthesis flows to be aware of. one is a path which passes a synthesized xnf netlist to the downstream xilinx tools. the other is a path which uses SG to create an EDDM database (schematics!) which is then passed to xilinx (in particular, "men2xnf"). according to my mentor rep last spring, only the latter flow is officially suported by xilinx. this is not to say the former flow won't work (i haven't tried), its just that xilinx chose to support synopsys-based synthesis first and has not quite gotten its mentor-based synthesis support going full speed. another issue related to high performance designs is the use of the "xact performance" timing constraints for PPR, the xilinx partition, place, route engine (i don't know if PPR is a part of the neocad tools). xact performance constraints are traditionally implemented as schematic properties (or "attributes") placed on nets and/or instances. this may be problematic in a 100% HDL-based design where net/istance names are constantly changing (but fortunately, top-level ports are not). i believe the xilinx synthesis guide describes a utility targeted to synopsys users to support the use of xact performance constraints with HDL-based designs. i believe such a utility does not exist for autologic users (but you'll need to follow up on this if its relevant to neocad). i might add that the documentation for xilinx/mentor synthesis is a bit sparse. roberta fulton at xilinx has been working on a xilinx autologic 2 synthesis guide (i have a prelim copy supplied by my mentor rep) but as far as i know, it hasn't been published yet. the synthesis guide provided by xilinx has a definite synopsys design compiler bias (but still useful to read). much of my support in this area has come from our excellent local mentor rep. having said all of this, autologic may not be the *perfect* environment for designing a xilinx fpga, but we have managed to get it to work so far. > Does anyone know whether it is possible to take a post-layout Neocad > design and directly generate a VHDL model from it for simulation > purposes (rather than having to generate schematics as I currently am). i believe there is a (structural) vhdl model generator that takes xnf as an input. try looking at http://WWW.ERC.MsState.Edu/mpl/vhdl. good luck! regards, -- _______________________________________________________________________ Lance Gin "off the keyboard Delco Systems - GM Hughes Electronics over the bridge, OFC: 805.961.7567 FAX: 805.961.7739 through the gateway, C43LYG@dso.hac.com nothing but NET!" _______________________________________________________________________Article: 4104
Andrew Phillips wrote: > ...you would probably be better off > choosing a fairly simple digital design to start with (if this is your > first FPGA design). I recommended the CORDIC calculator because it *is* a simple design, well within the abilities of a neophyte to execute. It is also unusual enough to have a really decent 'gee-wiz' factor. As I stated before, it will fit in the smallest FPGAs. I feel the design is a good learning tool for the following reasons: 1. Bit serial design by nature does not often encounter the routing congestion and speed problems associated with FPGAs: This design will route using the APR tools. I will guarantee that. 2. The design is not speed sensitive, so even poor execution will result in a functional design. If time permits, the student can do a timing analysis on the design to know its limits. 3. The amount of logic design is small. The calculator core I described in the problem statement consists of three serial adder/ subtractors (one clb each), six shift registers, about a dozen multiplexers, a small lookup table (16 entries per function gives better than 12 bit accuracy...for all functions, better than 30 bits for sin and cosine), and a pretty simple state machine. Add input and output shift registers for a parallel interface and you got the whole thing! 4. The student is introduced to alternative ways to solve a problem. You aptly pointed that out in your statement about creating the CRAY in an FPGA. The CORDIC algorithms very elegantly avoid the hardware intensive solutions most people associate with transcendantal functions. The bit serial arithmetic reduces the hardware to practically nothing, offering a huge payback in systems that are not time critical (like a calculator). 5. The design forces the student to deal with the real world situation of translating a problem statement into a working design. He is not likely to find the design solution in a book or on the internet, but with a little thought can easily translate the algorithm into hardware that will work. I specifically like the serial design because it exposes the student to a degree of state machine design and functional timing that would be glossed over in many other systems. 6. Depending on the implementation, this design *can* touch all of the aspects of very high performance FPGA design, including high speed statemachine design, LUT Ram memories, level compression, pipelining, etc... All in a benign environment. > There is more than enough to learn going through the exercise of > designing a digital circuit rigorously (eg synchronous design issues > such as set-up and hold time calculations, metastability)... Precisely why I like this small design. It provides a small dose of all these issues without being so big that any one of them overwhelms. > It is easy to start off wanting to have the sexiest final year design > project but remember its September now and you need to finish by May > (dont forget you'll need 3-4 weeks to write up > the design report plus all those pesky final year subjects to consider > as well). And I figured this could easily be completed in a semester! > Maybe you would be interested in implementing an FIR filter (Xilinx has > app notes on this to get > you started). This is quite simple to start with and can be expanded > later on. You can change the filter coefficients to implement different > types of filters and check out tradeoffs in filter length, sampling... ...and you can download the design from Xilinx, paraphrase the app-note and be done, right? -Ray Andraka, P.E. Chairman, the Andraka Consulting Group 401/884-7930 FAX 401/884-7950 mailto:randraka@ids.net http://www.ids.net/~randraka/ The Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs. Services include complete design, development, simulation, and integration of these devices and the surrounding circuits. We also evaluate,troubleshoot, and improve existing designs. Please call or write for a free brochure or visit our web site.Article: 4105
Chris Humphres (chumphre@ee.duke.edu) wrote: : If anyone else is interested (seeing as Honest Earnest here forgot : his email address), this came from firstnations.ca. I don't know : Earnest's email but I do know that fnia@firstnations.ca is the contact : for this site. I can't guarantee he actually has an account there, but : that appears to be the origination of the posting. : Chris : Ernest, Aleixandre wrote: : > : [Much spam removed] : > * 5. Ernest Aleixandre : > * 108 Cedar Meadow Drive : > * Regina, Saskatchewan, Canada, S4X 3J6 : > * : > *********************************************************************** : > This works, I did it and have already received $682.00 in the past week. : > ************************************************************************ And did he tell Revenue Canada? :) -- Michael A. Covington http://www.ai.uga.edu/faculty/covington/ Artificial Intelligence Center <>< The University of Georgia Unless specifically indicated, I am Athens, GA 30602-7415 U.S.A. not speaking for the University.Article: 4106
Brad Wallace wrote: > < I am a senior EE student, and I need to do a senior design project by > May. I want to use a FPGA to do something useful, and I have a few < ideas. Does anyone have any good ideas or suggestions? Let me know, > please. < > Brad < bwalla@unf.eduBrad, Get yourself a few of those 5x7 LED matrix modules and drive both the column and row lines from the fpga directly. No other components needed. Minimum hardware and maximum fun. Add a few bottons, and you can build yourself a simple game machine. Forget about it being useful; too much and it will stunt the growth of your imagination.Article: 4107
Does anybody know how to get the Unix (serial port) XChecker cable with the MSDOS program XChecker working under NT or OS/2? E-regards --------------------------- Rainer Scharnow (amigo@bintec.de) BinTec Commmunications GmbH ---------------------------Article: 4108
> Peter Alfke, Xilinx Applications wrote .snip. > > There has been a thread about the (non)compatibility and the (non) > avilability of certain Atmel EEPROMs a few weeks back in this > newsgroup. > I don't want to start another flame with my dear friends at Atmel. > > Presently I would suggest using the Xilinx download cable during > development, then use the Xilinx SPROM. > In the future, there will be FLASH. > Presently *I* would suggest using the Atmel's In-System-(re)Programmable EEPROM AT17CXXX devices. If you would like us to send you a couple to try out or just want more info. - check out our *FREE* SAMPLE page at http://www.atmel.com/atmel/config.html. Martin. ------------------------------------------------------------------------- | Martin Mason | Snr FPGA/17Cxxx Applications Engineer | | Atmel Corp. | (email - me) martin@atmel.com | | 2325, Orchard Parkway | (email - help) fpga@atmel.com | | San Jose | configurator@atmel.com | | CA 95131 USA | (Tele) + (408) 436 4178 | | | (Fax) + (408) 436 4300 | -------------------------------------------------------------------------Article: 4109
Hi, everyone: I am a graduate student in ISU. I will design control circuits using FPGA. I have no experience of utilizing any programmable IC. Can you give me any advice? Thank you. Xiangdong LiArticle: 4110
Philip, >See above: no magic numbers in XNF. Disassembling PDS2XNF, XNFOPT, >or other 3rd party netlist generator isnt going to help you. Yes, sorry, you are right. >Plus it is a violation of the software license. :-) Is it? Not on the part of the *user* of Viewlogic, surely? I pay for a piece of software so I can do what I like with it, provided I remain a single user of it. Some license agreements (try to) prohibit patching the program, but any hypothetical magic number tweak would be operating on the data files only. >You will need to know both netlist formats to do this, and AWK type >substitutions may not quite be enough. SED/GREP etc might not, but AWK probably can, and of course any normal programming language can. My ASIC vendor worked out the .XTF netlist format, and wrote a converter for it, all within a day or two. In another day or so he wrote another converter which takes the test vector output from Viewwave (done with File, WriteTo, Generic) and converts it to his in-house format. Peter.Article: 4111
On Tue, 10 Sep 1996 05:44:42 GMT, fliptron@netcom.com (Philip Freidin) wrote: -- SNIP >As an example, Altera has XNF input capability in their MAX+II software >and I seriously doubt that Xilinx told them how to parse it. :-) > I've just received an eval copy of MAX+II in order to compare its results against a completed XC5210 design. If I could just read in the XNF file that would save me a lot of time in converting all the schematics over to Altera libraries. Where is the conversion utility I'm probably blind but I can't see it. -- AlanArticle: 4112
In article <32373621.3856186@news.wwa.com> aweir@spherecom.com (Alan Weir) writes: >On Tue, 10 Sep 1996 05:44:42 GMT, fliptron@netcom.com (Philip Freidin) >wrote: >>As an example, Altera has XNF input capability in their MAX+II software >>and I seriously doubt that Xilinx told them how to parse it. :-) >I've just received an eval copy of MAX+II in order to compare its >results against a completed XC5210 design. If I could just read in the >XNF file that would save me a lot of time in converting all the >schematics over to Altera libraries. Where is the conversion utility >I'm probably blind but I can't see it. > >-- Alan Create a new project, and for input (on the file menu) select a text file, and on the menu pulldown, select XNF. When you select the compiler, one of the menu items includes an XNF reader options.Article: 4113
> Mark Smotherman (mark@hubcap.clemson.edu) wrote:on the 4th Sept > : I would like to get pointers to any work on custom computing > : machines that transform selected C (or Fortran) routines into > : FPGA netlists. I have found papers and links to PRISM-II, being > : done at the Lab for Engineering Man/Machine Systems at Brown > : University. Are there other configuration compilers available, > : either at universities or from vendors? Parsys are building an awesome reconfigurable computer. We have the same issue, the best contender for a C compiler for this machine looks to be the work from Oxford University. Have a look at http://www.comlab.ox.ac.uk/oucl/hwcompArticle: 4114
Quy Dinh <dinh@mass-usr.com> wrote in article <322EE3D3.4F29@mass-usr.com>... > Which FPGA vendor out there did you select for your last PCI bus > interface designs. > or Which following FPGA vendors: I've taken a look at a few and personally chose Xilinx for a few reasons. I'm using the core that they sell and adding my own back-end logic. I can comment on a few things that I've discovered on the others. > > Altera Have looked at FLEX8000A and FLEX10K. The FLEX8000A has a fairly substatial hold time, which rules it out IMHO. The FLEX10K looks promising but seems to be a bit too slow currently. > Actel Haven't used it but there is an application note in Data I/O's magazine called something like "App Review." I noticed that Actel claims 100% burst but then they mention that they assume that the other end of the transaction never inserts a wait state. I'm not sure that you can make such an assumption in a general PCI system. > AT&T (ORCA) Haven't used it but have seen the protocol checklist provided by Logic Innovations. It appears to be a VHDL solution but I've heard that you have to instantiate portions of the design to guarantee timing. I've seen it on some PCI boards. > QuickLogic Haven't used it but have read the app. note available from their web site. It appears that it will work. It's done in VHDL but has fairly basic functionality. I've seen it on some PCI boards. > Xilinx I've used the currently available PCI Target design that Xilinx sells. It's a set of VIEWlogic schematics and some simulation files. I've also seen a pre-release of their PCI Initiator. I think that they use schematics instead of VHDL or Verilog so that they can guarantee timing (which will be a problem in any programmable solution, PCI timing is tough in FPGA/EPLDs). In the Initiator design, they've also added a "guide" file which is a portion of a full design. The "guide" file helps to guarantee timing on some critical paths. I'm assuming that the next release of the Target will include some of these new features. I have to admit a full design was more challenging than I expected, especially if you are doing a 33 MHz design with burst support. I don't think this is a limitation of Xilinx so much as it's just a difficult design problem. Consequently, if you are only doing small volumes or don't really need the integration, you might also look at using one of the PCI interface chip-sets out there like AMCC or PLX. You will still need a small amount of programmable logic connected to the chip-set to finish your design. > > who you believe is providing the best FPGA based PCI technology > PCI core (initiator/target) source code available, There is a lot of companies selling VHDL or Verilog source code. The thing is a BIG difference between the source code and a successful implementation in an FPGA or EPLD. The Xilinx design comes with the full set of VIEWlogic schematics. They don't have a synthesizable VHDL or Verilog solution but you can probably instantiate the netlist (though I've never tried this). > PCI 2.1 compliance For this one, I'd recommend asking the vendors if the they have the PCI-SIG compliance checklist completed. Many FPGA vendors have the electrical checklist filled out. The protocol checklist was the one that I found important. Again, be careful about companies that sell a VHDL/Verilog synthesizable core. The core may be fully compliant, but the implementation of the core in an FPGA may not be. > Zero wait state for Read/Write burst mode Watch out on this one, too. Be skeptical of any FPGA vendor that claims to have 100% burst. They are probably making some trade-off from complete compliance to the spec. (which is legitimate for some applications like embedded PCI). The Xilinx design supports 100% burst for Target Write and Initiator Read and 50% burst for Target Read and Initiator Write, but it does seem to follow the protocol rules to the letter. > Design tools (industry supports) Each of the FPGA vendors has a separate set of tools. I used various systems and each has its set of problems. I've mostly been using the Xilinx system for my designs. While I can't say that I love it, it does get the job done. > Your opinion/suggestion means a lot to me and are much appreciated Hopefully this info was useful. -- Raymond Gaita OptiMagic Logic Design StudiosArticle: 4115
hi,
I am a graduate doing Masters in Microelectronics. I am reqired to
implement a suitable architecture for a Speech Synthesizer (by Dennis
Klatt). This synthesizer consists mainly FIR realization and real-time
parameter updation. Generally speaking I have to realise a DSP kind of
architecture. I have access to the following resources:
* Viewlogic's Workview Plus along with FPGA synthesis tools.
* Synopsys's synthesis tools.
* Model Tech's VHDL tools.
* Tanner Tools for SPICE, Layout and S-Edit.
* XILINX FPGA programmer.
* Full access to the WEB.
I have the full software implementation of the synthesizer and I want to
do architecture extraction of it.
I will be glad if some one can help me in telling in how to go about
doing things with the above resources and information about literature
and Web sites where I can get help on related architectures (eg. DSP,
etc) .
Thanx in advance.
regards,
Saroj
___________________________________________________________
| |
| SAROJ ROUT Phone: 91-01596-42126 |
_______| EEE Department Fax: 91-01596-44183 |_______
\ | BITS,Pilani-333031 (INDIA) e-mail: saroj@bits.soft.net | /
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Article: 4116Are there anybody having experiences on writing VHDL code for FPGA multiplier? I would like to get a suggestion or openion which multiplication arichitecture is appropriate for FPGA. If you have sample VHDL source code, it will be wonderful! orachat@asu.eduArticle: 4117
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"High Level Design Using Verilog" is a fast paced, 5-day hands-on,
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Advanced Techniques Using Verilog
Course Overview
Copyright (c) 1996 Qualis Design Corporation
"Advanced Techniques Using Verilog" is a fast paced, 3-day hands-on,
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After a review of the more advanced behavioral constructs and
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Each day of class includes interactive lecture sessions with
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Sparcstations and the Verilog simulation environment of their
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Student Questions
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Prior to the first day of the course, registered students are
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Course Prerequisites
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students attending, all registrants must have prior experience with
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------------------------------
A full course syllabus listing all topics covered in this course is available.
Contact us for more information.
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8705 SW Nimbus Avenue, Suite 118
Beaverton, Oregon 97008 USA
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Article: 4118
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introduction to VHDL and shows the student how to approach complex
design tasks using High Level Design methods. The "Elite Class" course
"Advanced Techniques Using VHDL" leverages off the student's foundation
in VHDL to teach advanced design and verification methods. Both courses
provide high leverage knowledge for board, ASIC and FPGA designers.
For additional information about the material covered in these leading-edge
courses, see the course descriptions below.
These courses can also be held at your facilities in a private, one-on-one
setting -- contact us for more information.
Good News!
----------
Due to high demand, we have opened an additional session of our course
"High Level Design Using VHDL" during the week of September 30 through
October 4. See below for more information.
Schedule
--------
The Portland course schedule through December follows:
Course Title Course Dates Status
-------------------------------------------------------------------
High Level Design Using VHDL: Sep 23 - Sep 27 full
*** New Date! *** Sep 30 - Oct 04 open
Nov 04 - Nov 08 filling fast!
Advanced Techniques Using VHDL: Sep 30 - Oct 02 full
Nov 13 - Nov 15 open
For information about the material covered in these leading-edge courses,
see the course descriptions below.
The Qualis Difference
---------------------
We know what it's like to work under the pressure of aggressive schedules and
immense technical challenges. We believe that High Level Design methods
and technology, such as HDL-based verification and synthesis, are the key
to tackling those challenges and conquering today's design problems.
Our courses can really make a difference in your day-to-day work life
by showing you the high leverage points of VHDL and High Level Design.
Here's how we do it:
-- The Qualis "Best In Class" Instructor Team draws upon the absolute best
VHDL and Verilog consulting and training talent available. Our
instructors, top-notch Engineers with cutting-edge design experience,
know how to relate the course material to your real-world design problems.
-- Our courses are intense, hands-on events using the latest EDA tools
and hardware. Everything you need to learn quickly and efficiently is
provided -- you supply the brain, we'll supply everything else.
-- Our courses are like no other in the EDA industry. Engineers and
Managers who attend our courses will learn what's important and why, and
where to focus their time and resources for maximum leverage from HDLs
and design tools. And, unlike other vendor courses, our courses are
*dynamic* -- we constantly update our material with the latest in
High Level Design techniques and information, so you're assured of
learning the latest in the field.
-- Our courses are respected in the industry. We have taught our
High Level Design courses to dozens of companies and hundreds of
Engineers and Managers. Our student references attest to the
outstanding quality and real-world usefulness of our classes.
About Qualis Design Corporation
-------------------------------
Founded in 1992, Qualis Design Corporation has quickly become the
leading independent provider of High Level Design consulting and
training services. The company provides services to leading-edge
high technology firms worldwide, including Intel, Hewlett-Packard,
Tektronix, Xerox, TRW, and Northern Telecom. Qualis' corporate
headquarters are located in Beaverton, Oregon.
Don't miss this opportunity to learn the latest in High Level Design from
the best in the industry. For course syllabi and registration information,
contact us at:
Linda Boyd, Training Registrar
Qualis Design Corporation
8705 SW Nimbus Avenue, Suite 118
Beaverton, Oregon 97008 USA
Phone: +1-503-644-9700
FAX: +1-503-644-1583
E-mail: training@qualis.com
World Wide Web: coming soon!
Brief Course Descriptions
--------------------------
High Level Design Using VHDL
Course Overview
Copyright (c) 1995, 1996 Qualis Design Corporation
"High Level Design Using VHDL" is a fast paced, 5-day hands-on,
multimedia course designed not only to teach High Level Design
techniques and the VHDL language, but to make class participants
immediately productive in a system design environment using
state-of-the-art simulation and synthesis tools.
After an introduction to VHDL, the course deviates from the
traditional bottom-up, gates-to-behavioral modeling presentation of
other VHDL courses and reverses the flow, teaching top-down
design practices, with early special emphasis on coding for synthesis,
efficient testbench generation and advanced design verification
techniques. These skills are reinforced throughout the week while
teaching VHDL from a High Level Design perspective.
The course labs are designed to accommodate the learning aptitudes of
a wide range of students with diverse design experiences. Each lab is
structured into three parts:
1. Fundamental Concepts Review and Experience
2. Recognition of Common Mistakes and Correcting Problems
3. Additional Material for Advanced Students
All students complete parts one and two of each lab. Part three is
for students who finish early and want to learn additional material.
This lab structure caters to all student skill levels and provides
excellent opportunities to expand one's knowledge of VHDL simulation
and synthesis techniques.
Each day of class is divided into multiple interactive lecture and
lab sessions. Students have access to individual Sun Sparcstations,
the VHDL simulation environment of their choice, and the Synopsys
DC Expert synthesis environment for use during the lab sessions.
The course material is presented using a projection system that allows
30% more material to be presented in a given amount of time with vivid,
interest-grabbing color slides.
Full Course Syllabus Available
------------------------------
A full course syllabus listing all topics covered in this course is available.
Contact us for more information.
------------------------------------------------------------------------------
Advanced Techniques Using VHDL
Course Overview
Copyright (c) 1996 Qualis Design Corporation
"Advanced Techniques Using VHDL" is a fast paced, 3-day hands-on,
multimedia course designed to bring Engineers with experience in
using VHDL to an unparalleled level of efficiency.
After a review of the more advanced behavioral constructs and
features of VHDL, the course immediately illustrates how these
constructs can turn an ordinary-looking environment into a design
simulation and verification powerhouse through the use of
bus-functional models, test harnesses, abstract regressionable
testbenches and behavioral models.
Each day of class includes interactive lecture sessions with
8 challenging labs. Students will have access to individual Sun
Sparcstations and the VHDL simulation environment of their
choice. The course material is presented using a projection
system that allows 30% more material to be presented in a given amount
of time with vivid, interest-grabbing color slides.
Student Questions
-----------------
Prior to the first day of the course, registered students are
encouraged to submit questions related to their current usage
of VHDL to the instructor. Questions or topics that illustrate
modeling techniques or features of the language will be included
in the course presentation.
Course Prerequisites
--------------------
Due to the fast-paced nature of this class and the caliber of the
students attending, all registrants must have prior experience with
the VHDL language, or previously attended the Qualis course
"High Level Design Using VHDL". Knowledge of a structured
programming language, such as C or Pascal, is recommended.
Full Course Syllabus Available
------------------------------
A full course syllabus listing all topics covered in this course is available.
Contact us for more information.
------------------------------------------------------------------------------
Qualis Design Corporation
8705 SW Nimbus Avenue, Suite 118
Beaverton, Oregon 97008 USA
Phone: +1-503-644-9700
FAX: +1-503-643-1583
E-mail: training@qualis.com
World Wide Web: coming soon!
"DC Expert" is a trademark of Synopsys, Inc.
"Verilog" is a registered trademark of Cadence Design Systems, Inc.
Copyright (c) 1995, 1996, Qualis Design Corporation. All Rights Reserved.
Article: 4119
David E. Wallace <wallace@netcom.com> wrote:
>Ok, I didn't realize the number of EDA users responding was so
>big, and the number of Cadence employees responding was so small.
>Given that, yeah, if you can count on the responses being representative
>of their respective populations, you do have statistical evidence
>of a difference between the two groups. At least that's what the
>formula for the difference of the means of two binomial distributions
>from my old stat text seems to tell me. (The differences in the
>proportions are 4.5 and 3.2 standard deviations away from the expected mean
>if the populations were identically distributed.)
>
>I'm still concerned about the self-selection bias, though. I'm
>concerned that the group of EDA vendors who would respond to such
>a survey may not be representative of EDA vendors in general in the same
>way as the group of EDA users responding is representative of EDA users
>in general. That's because the question is closer to home for the
>EDA vendors, and may affect some types of vendors more closely than others.
>Given the small number of EDA vendor responses, even a small self-selection
>bias might have large effects on the overall results.
Dave, again, I ain't no statistics wizard, but from my old college sophmore
class in the topic I remember how the proff said that self selection isn't
as flawed as it's commonly believed. The reason why is that you test on
non-self selecting parameters. For example, if you had people self-select
for if they liked the color "blue" as their favorite, it's perfectly
legit to break the "blue" lovers into male and female groups and then
use it to compare how men & women like of dislike eating spinach. The
reason why is that their color preference has no correlation to what foods
they may or may not like.
My contention is that EDA makers and EDA users are far, far, far more
alike not only in training, but also in work environments, education,
-- even race, gender, and pay scale distributions that it's fair to
test both samples from the Cadence/Avant! lawsuit survey to find
real diffences between these two groups as far as how they view lawsuits
in their industry.
- John Cooley
Part Time EDA Consumer Advocate
Full Time ASIC, FPGA & EDA Design Consultant
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 4599 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 4120Raymond Gaita <optmagic@ix.netcom.com> wrote in article <01bba0c1$a2146b00$cd81b6c7@#optmagic>... > > > Actel > Haven't used it but there is an application note in Data I/O's magazine called > something like "App Review." I noticed that Actel claims 100% burst but then they > mention that they assume that the other end of the transaction never inserts a > wait state. I'm not sure that you can make such an assumption in a general PCI > system. > I've had a few inquiries on the above reference. I finally found it. It's in a publication called "app REVIEW" which is an advertising supplement with contributed application notes from various vendors. The specific issue is dated September 9, 1996. On page 23, Actel seems to be talking about Target Read burst mode and states, "Burst Transfer mode assumes the master will not deassert IRDYn during the transfer." -- Raymond Gaita OptiMagic Logic Design StudiosArticle: 4121
On Sept 12, <orachat@asu.edu > wrote: > Are there anybody having experiences on writing VHDL code for FPGA > multiplier? I would like to get a suggestion or openion which > multiplication arichitecture is appropriate for FPGA. If you have sample > VHDL source code, it will be wonderful! Exemplar had module generation that automatically produces multiplier modules optimized for FPGA architectures. The modules themselves are written in VHDL. I was impressed by the example I saw for Altera FLEX devices. benArticle: 4122
I would also like to know what people think about Warp 4.0. How good is the simulator package? Does the timing simulator run VHDL behavioral simulations only, or does it run gate-level simulations also? Finally, where can I get Warp 4.0 with the text for $61 CDN? RobArticle: 4123
In CMOS designs, a NAND gate takes four transistors, and so the usual definition of gates is transistors/4. But this only works for CMOS. But the goal of Xilinx is to be able to load logic that could become CMOS, so they should use a similar metric. It may be as useful as Dhrystone benchmark is at telling how fast a CPU will run your application. If averaged over typical designs, it may be approximately right. -- glenArticle: 4124
Xiangdong Li (lxd@cpre1.ee.iastate.edu) wrote: : Hi, everyone: : I am a graduate student in ISU. I will design control circuits using : FPGA. I have no experience of utilizing any programmable IC. Can you : give me any advice? Thank you. You may want to start with simple PLD's and Abel before getting into FPGA's and their associated tools because the formers are a lot simpler to learn and use.
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