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In article <50nllv$2a1a@service.polymtl.ca>, Patrick Jarry <wolf@step.polymtl.ca> wrote: >Hi everyone, > >In many engineering and design publication, I've heard of Warp2, which is >a VHDL behavioral synthesis for Cypress programmable logic. They claim >that their software offers better synthesis than 20 000.00$ packages, with >IEEE standards synthesis, simulation output, auto fitting and >plac-and-route, etc. all this for 99.00$. > >Being a student, I can't afford very expensive FPGA's or PLD's >development system, but I'd like to know if anyone of you tried this >software, and what was the performance like. Because even at 99.00$ I >want to make sure that it's worth the money. > >Thanks a lot, > >Patrick Jarry, >computer and electronics engineering student I haven't tried it yet and don't know how good it is, but I there is a new textbook on VHDL which includes the Warp 2 ver. 4.0 (latest ver. which includes a timing simulator) CD, and the whole package is only $61 (Canadian $) . If you don't mind using a non-standard HDL, Lattice will give you synario (uses ABEL-HDL and also has a schematic compiler) for free. It's set up so that you can only use lattice parts, but many of them are programmable through a 4-wire JTAG interface, and the programmer is <$100 ... I've been using synario for just a couple of days, and I'm finding it's not quite flawless, but for the price, it's a good place to start. -robArticle: 4051
Hi there, I have just finished a research PhD investigating an FPGA based image coprocessor. It is based on the Xilinx XC6200 device. The project also looked at the programming model for such a coprocessor and has developed a novel application oriented high level programming language interface in C++. (something I personally believe is vital for FPGAs to be accepted by the wide computing community). If anyone is interested, a copy is available at http://www.cs.qub.ac.uk/~P.Donachy/thesis/ Any comments / follow-ups or even job-offers!, much appreciated! Paul Donachy p.donachy@qub.ac.ukArticle: 4052
I'm looking at moving from using Xilinx to ORCA FPGAs. On paper ORCA looks more suited to my real-time video processing applications. Initially I plan to stick with schematic entry to check out the ORCA architecture, then perhaps invest in HDL tools if justified. The only PC based schematic entry system supported appears to be the Viewlogic PRO Series running under Windoze 3.1/3.11. I've briefly used this for Xilinx design entry and found it to be truely awful. It's the worst schematic entry package I've ever had the misfortune to use. I don't get it - has it been designed to make drawing as slow as possible? Is the idea to persuade you it's worth moving to HDL? I've been supplied with a 90 day license with which to evaluate the ORCA tools. Whilst this includes the ORCA Viewlogic libraries, it does not include a Viewlogic licenese with which to run them! It would probably be breaking my Xilinx license agreement to try to access them from my Xilinx setup - honesty aside, it also doesn't work! So, it looks like I'm faced with paying out for another Viewlogic license, on a package I hate, for the sake of evaluating the ORCA tools and architecture. I don't mind investing in tools if they are going to do what I need, but it's very difficult to decide this until you've been through a real design, hence the need for an evaluation period. So, has anybody got any advice for me? Is it worth attempting to move to ORCA, bearing in mind that a lot of my designs require signal processing at 13.5 and 27 MHz? What are your views on the Viewlogic PRO Series? Would Workview Office (or whatever it's called) be better under Windoze '95? -- Richard Jozefowski Millipede Electronic GraphicsArticle: 4053
Xilinx Users Mailing List Digest 15 9/05/96 1. Subject: ViewSynthesis and Xilinx ====================================================================== From: [Anonymous] Subject: ViewSynthesis and Xilinx. We have started using Viewsynthesis which is part of the ViewOffice suite from Viewlogic. We use VHDL and target X4000 devices. ViewSynthesis does not generate an xnf file that you can merge into the overall design, it generates a wir file and a schematic. It does not use FMAPs or HMAPs, and hence does a very poor job in allocating CLB resources. Even XABEL uses FMAPs and HMAPs. So after each synthesis run, we have to edit the schematic to add the FMAPs and it's a real pain since the slightest change in the VHDL source generates a new schematic. As our fiscal year starts in october, we have the opportunity to purchase another VHDL synthesis tool if its included in our capital budget, and I would like to do so as an educated consumer. I would like to ask the list their opinion first on Viewsynthesis and then on any other synthesis tool they might be using to design Xilinx devices. My questions: 1. Has anyone used ViewSynthesis? Likes, dislikes 2. Is there a workaround to the FMAP? Obviously Viewlogic tech support is completely useless on that subject. 3. Has anyone used other synthesis products: Synopsys FPGA Compiler, Synplicity Synplify, Xilinx Foundation (Metamore), Synopsys FPGA Express, Data IO Synario, Minc, any other? 4. What do you like about the above products? What do you dislike? Limitations, bugs? State machine support On what basis did you select it. cost, functionality, availability, tech support, platform, other? 5. What size devices have you implemented in VHDL? 6. Do you use schematic and VHDL or only VHDL? Thanks for your help. ============================================================================== XUMA is an independent mailing list for users of Xilinx devices and tools. To subscribe send an email to xuma_request@ecla.com Would you like to contribute an article? Share an experience, good or bad, with xilinx parts or tools, Describe a bug, or need some help, have a question or just a comment: then, post an article, send an email to xuma@ecla.com The digests are archived at http://www.ecla.comArticle: 4054
try www.xilinx.comArticle: 4055
Quy Dinh (dinh@mass-usr.com) wrote: : Hi All, : I'm currently in a process of evaluating to select a FPGA : vendor for my next coming task (FPGA based PCI bus interafce design) : If you have any experiences related to FPGA based PCI designs : and want to share the experiences then I would like to hear from you. : Which FPGA vendor out there did you select for your last PCI bus : interface designs. : or Which following FPGA vendors: : : Altera : Actel : AT&T (ORCA) : QuickLogic : Xilinx : ... and more : who you believe is providing the best FPGA based PCI technology : PCI core (initiator/target) source code available, : PCI 2.1 compliance : Zero wait state for Read/Write burst mode : Design tools (industry supports) : Engineering supports : to customers regarding to cost/performance. : Your opinion/suggestion means a lot to me and are much appreciated : Thanks, : -quy dinh I just finished implementing a home-made PCI target interface in a XC4010E-PQFP160. It worked fine (with a 2 layer PCB :) ), zero wait state is also implemented. If you're gone use a xilinx FPGA, I'dc suggest using a larger one instead of the XC4010E-PQFP160 kindly regards, Kim -- ============================================================================== ************************************ * Hofmans Kim * * * * tw38966@vub.ac.be * * khofmans@info.vub.ac.be * * * * Brouwerijstraat 62 * * 1630 Linkebeek * * Belgium * * * * 32-2-3771012 * * * ************************************Article: 4056
We are currently using EPROM 254k Bit from Xilinx to store our XE4000 configuration. They are bloody expensive. Do you know any second source or even better a compatible EEPROM ?Article: 4057
Constantin Jean-Claude wrote: > > We are currently using EPROM 254k Bit from Xilinx to store our XE4000 > configuration. They are bloody expensive. > Do you know any second source or even better a compatible EEPROM ? Try ATMEL (www.atmel.com) They have Xilinx compatible EEPROMs.Article: 4058
The PARALLEL Processing Connection is an entrepreneurial association; we mean to assist our members in spawning very successful new businesses involving parallel processing. Our meetings take place on the second Monday of each month at 7:30 PM at Sun Microsystems at 901 South San Antonio Road in Palo Alto, California. Southbound travelers exit 101 at San Antonio ; northbound attendees also exit at San Antonio and take the overpass to the other side of 101. There is a $12 visitor fee for non-members and members ($65 per year) are admitted free. Our phone number is (408) 732-9869 for a recorded message about upcoming meetings; recordings are available for those who can't attend - please inquire. Since the PPC was formed in late 1989 many people have sampled it, found it to be very valuable, and even understand what we're up to. Nonetheless, certain questions persist. Now, in our seventh year of operation, perhaps we can and should clarify some of the issues. For example: Q. What is PPC's raison d'etre? A. The PARALLEL Processing Connection is an entrepreneurial organization intent on facilitating the emergence of new businesses. PPC does not become an active member of any such new entities, ie: is not itself a profit center. Q. The issue of 'why' is perhaps the most perplexing. After all, a $65 annual membership fee is essentially free and how can anything be free in 1996? What's the payoff? For whom? A. That's actually the easiest question of all. Those of us who are active members hope to be a part of new companies that get spun off; the payoff is for all of us -- this is an easy win-win! Since nothing else exists to facilitate hands-on entrepreneurship, we decided to put it together ourselves. Q. How can PPC assist its members? A. PPC is a large technically credible organization. We have close to 100 paid members and a large group of less regular visitors; we mail to approximately 400 engineers and scientists (primarily in Silicon Valley). Major companies need to maintain visibility in the community and connection with it; that makes us an important conduit. PPC's strategy is to trade on that value by collaborating with important companies for the benefit of its members. Thus, as an organization, we have been able to obtain donated hardware, software, and training and we've put together a small development lab for hands-on use of members at our Sunnyvale office. Further, we've been able to negotiate discounts on seminars and hardware/software purchases by members. Most important, alliances such as we described give us an inside opportunity to JOINT VENTURE SITUATIONS. Q. As an attendee, what should I do to enhance my opportunities? A. Participate, participate, participate. Many important industry principals and capital people are in our audience looking for the 'movers'! For further information contact: -- B. Mitchell Loebel parallel@netcom.com Director - Strategic Alliances and Partnering 408 732-9869 PARALLEL Processing Connection Mktg. Director Minute-Tape International CorporationArticle: 4059
Sptember 9, 1996 EDA - Opportunities for Parallel Processing, Part II Our August's presentation clearly indicated that the EDA (ECAD) industry represents some very significant parallel processing application opportunities; simulation, synthesis, place and route, verification, etc. are all very compute intensive but parallelism has not yet been extensively used. This month we invited Henry Verheyen, Vice President of Engineering at Aptix Corporation to take the discussion to a deeper level. Henry has spent 12 years working on both the vendor and customer side; his experience with Cadence, Quickturn, Xilinx, and Aptix have made him an industry expert. He plans to explain todays EDA design flows and show us the structure of the various algorithms that are used. He'll size up the marketplace by showing us who the players are and why they haven't yet moved much into parallelism. This looks like virgin territory!! PPC would like to create a start-up team out of its member base to port EDA tools to various parallel machines including a Distributed Shared Memory cluster of PC's. Please inquire if you are interested in this $$$ opportunity; if you are not yet a memberoof PPC, perhaps you would like to become one. The main meeting starts promptly at 7:30PM at Sun Microsystems at 901 San Antonio Road in Palo Alto. This is just off the southbound San Antonio exit of 101. Northbound travelers also exit at San Antonio and take the overpass to the other side of 101. A discussion of member projects currently underway and other issues of interest to entrepreneurs follows immediately thereafter at 9PM. Please be prompt; as usual, we expect a large attendance; donŐt be left out or left standing. There is a $12 fee for non-members and members will be admitted free. Yearly membership fee is $65. -- B. Mitchell Loebel parallel@netcom.com Director - Strategic Alliances and Partnering 408 732-9869 PARALLEL Processing Connection Mktg. Director Minute-Tape International CorporationArticle: 4060
September 9, 1996 EDA - Opportunities for Parallel Processing, Part II Our August's presentation clearly indicated that the EDA (ECAD) industry represents some very significant parallel processing application opportunities; simulation, synthesis, place and route, verification, etc. are all very compute intensive but parallelism has not yet been extensively used. This month we invited Henry Verheyen, Vice President of Engineering at Aptix Corporation to take the discussion to a deeper level. Henry has spent 12 years working on both the vendor and customer side; his experience with Cadence, Quickturn, Xilinx, and Aptix have made him an industry expert. He plans to explain todays EDA design flows and show us the structure of the various algorithms that are used. He'll size up the marketplace by showing us who the players are and why they haven't yet moved much into parallelism. This looks like virgin territory!! PPC would like to create a start-up team out of its member base to port EDA tools to various parallel machines including a Distributed Shared Memory cluster of PC's. Please inquire if you are interested in this $$$ opportunity; if you are not yet a memberoof PPC, perhaps you would like to become one. The main meeting starts promptly at 7:30PM at Sun Microsystems at 901 San Antonio Road in Palo Alto. This is just off the southbound San Antonio exit of 101. Northbound travelers also exit at San Antonio and take the overpass to the other side of 101. A discussion of member projects currently underway and other issues of interest to entrepreneurs follows immediately thereafter at 9PM. Please be prompt; as usual, we expect a large attendance; donŐt be left out or left standing. There is a $12 fee for non-members and members will be admitted free. Yearly membership fee is $65. -- B. Mitchell Loebel parallel@netcom.com Director - Strategic Alliances and Partnering 408 732-9869 PARALLEL Processing Connection Mktg. Director Minute-Tape International CorporationArticle: 4061
ANNOUNCEMENT: Immediate Release Model of the Month ==================== This month's FREE model is: Carry Look Ahead Blocks You can find it at http://www.doulos.co.uk. You can also access previous FREE Models and Tips of the Month from the same site. ____________________________________________________________________ Also *** NEW *** for this month are: TIP of the MONTH: Synthesisable 'always' blocks for sequential circuits (Verilog) Excerpts from the Verilog Golden Reference Guide Additions to our 'Hardware Engineers Guide to VHDL' series ____________________________________________________________________ Also visit the Doulos site for: VHDL Quick Reference Card VHDL 93 Update Reference Card _____________________________________________________________________ Also details how to get a FREE online VHDL tutorial. DOULOS Church Hatch Tel: +44 1425 471 223 22 Market Place Fax: +44 1425 471 573 Ringwood BH24 1AW Email: info@doulos.co.uk UK _____________________________________________________________________ __________________________________________________________________Article: 4062
ANNOUNCEMENT: Immediate Release Tip of the Month ================== This month's 'Tip' is: Synthesisable 'always' blocks for sequential circuits (Verilog) You can find it at http://www.doulos.co.uk. You can also access previous FREE Models and Tips of the Month from the same site. ____________________________________________________________________ Also *** NEW *** for this month are: FREE MODEL of the MONTH: Carry Look Ahead Blocks Excerpts from The Verilog Golden Reference Guide Additions to our Hardware Engineers Guide to VHDL series ____________________________________________________________________ Also visit the Doulos site for: VHDL Quick Reference Card VHDL 93 Update Reference Card _____________________________________________________________________ Also details of how to get a FREE online VHDL tutorial. DOULOS Church Hatch Tel: +44 1425 471 223 22 Market Place Fax: +44 1425 471 573 Ringwood BH24 1AW Email: info@doulos.co.uk UK URL: http://www.doulos.co.uk _____________________________________________________________________Article: 4063
I have done several designs with Xilinx FPGAs... I am tired of NRE charges and quantity requirements needed to go to hardwire. I am considering alternative vendors like Cypress, Altera, Atmel and Actel. Please give me guidance (positive or negative) on design tools, pricing, availability of these alternative vendors.Article: 4064
Brad Wallace wrote: > > I am a senior EE student, and I need to do a senior design project by > May. I want to use a FPGA to do something useful, and I have a few > ideas. Does anyone have any good ideas or suggestions? Let me know, > please. > > Brad > bwalla@unf.eduBrad, A real good project that would be impressive to your prof, and would give you a great deal of extra knowledge would be a scientific calculator that can do the basic four fucntions plus all the trig, inverse trig, hyperbolic trig and thier inverses, logs, exponents, squares and square roots, and rectangular-polar conversions. It sounds complex, but don't panic. It really is pretty simple to implement and should fit easily into even a small Xilinx 5200 series part. The key is a set of neat shift-add algorithms called CORDIC that takes care of all these transcedental functions. The algorithms can be realized with a very small amount of hardware if they are done iteratively with bit serial hardware. I've done quite a bit of work both with CORDIC and bit serial hardware. Not many people are very familiar with either. You can check out papers I have on the web concerning bit serial hardware. The Supercon paper describes the construction of a pipelined CORDIC processor for finding vector magnitudes. If you decide to pursue this as your project, let me know. I can point you to more info on the CORDIC algorithms.Article: 4065
When I run Viewlogics Prosim under Windows 3.11 the program states that I have only about 1 Meg of memory available (which is not enough to load anything even moderately big). When I run any of the other Pro Series tools (i.e. Procapture or Prowave) they report I have 75Meg of memory available. MSD also says I have plenty of memory. Anyone ever seen this problem and have any hints???Article: 4066
In article <50oggr$ed0@vanbc.wimsey.com>, Rob Semenoff <rob@wimsey.com> wrote: >In article <50nllv$2a1a@service.polymtl.ca>, >Patrick Jarry <wolf@step.polymtl.ca> wrote: >>development system, but I'd like to know if anyone of you tried this >> >>Patrick Jarry, > >but I there is a new textbook on VHDL which includes >the Warp 2 ver. 4.0 (latest ver. which includes a timing simulator) >CD, and the whole package is only $61 (Canadian $) . $61 was the price I saw for the book at the University bookstore, with the CD included. Cypress will include the book for free if you buy the software for $99 (?!) All the information is on the cypress website under "what's hot". -rob -Article: 4067
Richard Jozefowski richard@milliped.demon.co.uk wrote: > So, has anybody got any advice for me? Is it worth attempting to move to > ORCA, bearing in mind that a lot of my designs require signal processing at > 13.5 and 27 MHz? What are your views on the Viewlogic PRO Series? Would > Workview Office (or whatever it's called) be better under Windoze '95? I made this move about a year ago and I haven't regretted it yet. The ORCA architecture is better than Xilinx for a lot of things, but the software is a bit more primitive. I have several 2c12 and 2c15 designs routed at 50MHz. All of them required extensive hand placement and routing which is not easy with the ORCA software. I use Workview-Office which is even worse than workview-pro. Unfortunately wv-office won't work with the current ORCA version unless you throw a fit and demand a proper license. Lucent claims to have its 9.0 release out soon. If at all possible, I'd try to avoid buying in to viewlogic.Article: 4068
You are invited to check out a special report about Intellectual Property -- reusable cores and macros. View it at www.pldsite.com. The report is from a first-of-its kind Web-based Roundtable of experts held in late August and discusses engineering, device and software issues. I would like to get your user inputs about what these experts discussed. So drop a note when you read it. Thanks, Stan Baker Editor, Programming SiliconArticle: 4069
Richard, >The only PC based schematic entry system supported appears to be the >Viewlogic PRO Series running under Windoze 3.1/3.11. I've briefly used this >for Xilinx design entry and found it to be truely awful. This is what I found too. I continue to use the DOS Viewlogic, v4.1, for FPGA design. (I use DOS Orcad SDT for other schematic designl it is far superior). Also, Proview is a win3.x-only program which cannot run under 95 or NT, and so it is not a good idea to spend money on it, given the obvious drift towards NT in the EDA business. > It's the worst >schematic entry package I've ever had the misfortune to use. I have seen worse! >I've been supplied with a 90 day license with which to evaluate the ORCA >tools. Whilst this includes the ORCA Viewlogic libraries, it does not >include a Viewlogic licenese with which to run them! It would probably be >breaking my Xilinx license agreement to try to access them from my Xilinx >setup - honesty aside, it also doesn't work! This is deliberate. This is Viewlogic's licensing policy. I questioned AT&T about this a while ago, but they have no choice in the matter. There is a program around which "fixes-up" things so you can do what you presently cannot, but I don't have it, and I believe it is also Viewlogic-version-dependent. >What are your views on the Viewlogic PRO Series? Personally, I would not spend any serious money on EDA software today unless it is an NT version, for reasons above. >Would Workview Office (or whatever it's called) be better under Windoze '95? I have no experience of this and others will doubtless have things to say. But this is a new and substantially re-written major program, and you know what that means! Also, I understand that Xilinx do not yet sell the Xilinx-only-crippled (and thus cheaper) Office version; they still sell Proview only. But this may be old info. You could also look at Orcad Capture and Protel Schematic. Both can be used to draw Xilinx etc FPGA schematics, and I think both are better than Proview. (Both are still poor IMO). But Protel don't AFAIK offer a simulator of any sort. Viewsim is hard to beat. Peter.Article: 4070
DTHIBAUL (DTHIBAUL@mailgw.sanders.lockheed.com) wrote: : When I run Viewlogics Prosim under Windows 3.11 the program states : that I have only about 1 Meg of memory available (which is not enough to : load anything even moderately big). When I run any of the other Pro : Series tools (i.e. Procapture or Prowave) they report I have 75Meg of : memory available. MSD also says I have plenty of memory. Anyone ever : seen this problem and have any hints??? What's your total physical memory? And the amount of virtual memory under Win3.11? Do you start Prosim using the proflow or 'link to prosim' under the procapture ? Are there any other applications running in background ? -- ============================================================================== ************************************ * Hofmans Kim * * * * tw38966@vub.ac.be * * khofmans@info.vub.ac.be * * * * Brouwerijstraat 62 * * 1630 Linkebeek * * Belgium * * * * 32-2-3771012 * * * ************************************Article: 4071
What's your definition of "bloody expensive"? EEPROM chip size tends to be bigger, and I don't know of any compatible 256k EEPROM. There has been a thread about the (non)compatibility and the (non) avilability of certain Atmel EEPROMs a few weeks back in this newsgroup. I don't want to start another flame with my dear friends at Atmel. Presently I would suggest using the Xilinx download cable during development, then use the Xilinx SPROM. In the future, there will be FLASH. Peter Alfke, Xilinx ApplicationsArticle: 4072
In article <50q5jk$2d0@fnnews.fnal.gov>, Don Husby <mailto:husby@fnal.gov> wrote: > > Richard Jozefowski richard@milliped.demon.co.uk wrote: > > So, has anybody got any advice for me? Is it worth attempting to move to > > ORCA, bearing in mind that a lot of my designs require signal processing at > > 13.5 and 27 MHz? What are your views on the Viewlogic PRO Series? Would > > Workview Office (or whatever it's called) be better under Windoze '95? > > I made this move about a year ago and I haven't regretted it yet. > The ORCA architecture is better than Xilinx for a lot of things, but > the software is a bit more primitive. I have several 2c12 and 2c15 > designs routed at 50MHz. All of them required extensive hand placement > and routing which is not easy with the ORCA software. Aren't the ORCA back-end place and route tools written by NeoCAD? If these are worse than the Xilinx tools (eg ARP/PPR), then I wonder why Xilinx acquired NeoCAD and why Xilinx's much delayed next release will be based on the NeoCAD tools. Apparently Lucent (ex AT&T) had rights to the NeoCAD source code so, when they were acquired by Xilinx, they took the code and (they claim) some of the key NeoCAD development personnel and set up shop across the road in Boulder. I wonder how much of this is sales bluster. > I use Workview-Office which is even worse than workview-pro. Unfortunately > wv-office won't work with the current ORCA version unless you throw a fit > and demand a proper license. Lucent claims to have its 9.0 release out soon. > If at all possible, I'd try to avoid buying in to viewlogic. My ORCA Foundry evaluation kit is version 7.1. Sounds like I'm a bit out of date. Are you suggesting there will be another, hopefully better, schematic entry system available with the 9.0 release? Come to think of it, it is hard to imagine one worse. -- Richard Jozefowski Millipede Electronic GraphicsArticle: 4073
I've been using Actel FPGA's for a couple of years and love them. The achitecture is much like a gate array, and your designs are secure. The antifuse types are great for small to medium size runs, and they are about 3 times cheaper than sram based for the same useable gatecount. The tools are pretty good too. And you can be sure they are routeable - I once did an A1010 design using 99.7% logic blocks. It routed without problems. Actel has a wide range of devices covering 1200 to 20000 REAL gates, and some really fast ones. They dont have hardwire like xilinx, but companies like Orbit is offering gate array conversion pretty cheap. Another antifuse vendor is quicklogic/cypress, but I consider Actel the best antifuse vendor. Actel is at http://www.actel.com Quicklogic is at http://www.quicklogic.com Orbit is at http://www.orbitsemi.com regards sorenArticle: 4074
In article <Dx8B4o.KBo@world.std.com>, John Cooley <jcooley@world.std.com> wrote: >disjoint difference. It's not like comparing EDA users to, say... >left-handed, Laplander lesbians. Oh, yeah? What makes you think we can't be compared.... Arnim "Lefty Lulu" Littek, lefty Lapland Lesbian from Lithgow, Lithuania. -- Arnim Littek arnim@actrix.gen.nz Actrix Networks Ltd. fax +64-4-499-1130 uucp/PPP/SLIP/BBS accounts tel +64-4-499-1122
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