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*** FREE INTERNET! *** Forever! NEVER EVER pay for Internet Access AGAIN!!! E-V-E-R! Amazing Course on Audio Tape describes STEP by STEP what your Internet Service Provider doesn't want you to know! * How to get FREE LOCAL DIAL-UP PPP Internet Access! * How to Surf the Web,Newsgroups,and EMAIL 100% Anonymously/Untraceable! * How to Make VOICE Phone Calls ANYWHERE in the World UNTRACEABLE! * Where you can get FREE Email Remailing * Where you can get FREE Email Accounts * Where you can get FREE Access to News Servers * How to get FREE Internet Tools for Email, News, WWW, Etc. * How to get free accounts on BBS's * MUCH MUCH More!!! All will work ANYWHERE in the world and Forever! Reply to this message with your Name, Address, and Phone Number and we will send your order out immediatly by COD - Cash on Delivery. REPLY TO: Freenet1@ez1.com Act NOW! Limited Supply! Only $14.95 + 3.50 Shipping FAST SERVICE!!!Article: 4001
In article <ZOLTAN.96Sep1142913@vackor.bendor.com.au> zoltan@bendor.com.au (Zoltan Kocsi) writes: >There was an article here about a month ago which said the the bitstream >format for the 6200 is publicly available, together with all info you need >to do synthesis and P&R for the chip. >I asked the local Xilinx reps, they heard nothing about it. >Is there any truth in it ? > >Zoltan Yes, it's all true, the bitstream format, and how it controls routing and logic is all publicly available. Go to www.xilinx.com, and under products, you can find the data sheet for the XC6200 devices, in .pdf format. Get the file and print it, and you will have all the info. Now you only have to write your own synthesis or other design entry system and place and route software, and you are ready to go. I have spoken to at least one researcher who has already done this. All the best, Philip FreidinArticle: 4002
I have a Pentium 166 with 64Mb RAM, 2.1G disk and Win95. Foundation won't install correctly (crashes). Even the coretools install program crashes... I believe it is my system, not the tools, but I can't find anything extraordinary with my system. Anyone else had problems in this area? I'd certainly appreciate some help! -Andrew MetcalfeArticle: 4003
The following very good question was sent to us via email, so I thought I would enlighten the "masses" about the difference between PeakVHDL Training Edition and Cypress Warp 2: >You ought to convince us why your package at $499 is better than Cypress' >Warp 2 at $99... Cypress Warp is an outstanding bargain, and a great training tool for learning the basics of VHDL synthesis. (It is also very useful for real PLD designs.) It is not, however, a VHDL simulator. It is a PLD compiler that accepts a limited subset of VHDL: RTL only as appropriate for Cypress devices. Although it does include a simple gate-level simulator, you cannot model general-purpose behavioral logic (a CPU, say, or a RAM) or write test benches using Warp. Accolade's PeakVHDL is a complete VHDL simulator allowing you to enter and simulate an essentially unlimited number of different designs. You are not constrained to a synthesizable subset of the language, and you can write comprehensive VHDL test benches. Test bench development typically makes the most use of a VHDL designer's skills, so it is important to have access to a real VHDL simulator when learning the language. PeakVHDL Training Edition at $499 and Warp at $99 are actually a very good combination for learning VHDL. (In fact, one of our standard examples shows how to write a test bench for one of the synthesizable examples provided with Warp.) But Warp itself cannot really be considered enough for learning the complete VHDL language and its broader applications. For this you need a VHDL simulator. Hope this helps, -- DaveP -- David Pellerin (pellerin@seanet.com) -- Accolade Design Automation, Inc. -- 26331 NE Valley, Suite 5-120, Duvall, WA 98019 -- (800) 470-2686, (206) 788-1802, FAX (206) 788-3768 -- Visit http://www.acc-eda.com for a free PeakVHDL/PeakFPGA demo CD-ROM!!Article: 4004
Hi, I want to know the address, FAX and e-mail
address of ALTERA, XILINX HQ in the States.
Please send reply to 103
103350.1222@compuserve.com
Thank youvery much in advance for your help.
Regards
MULIANI
--
Article: 4005Alan, The NOVA simulator that came with your Warp 2 software will generate (type and add) test vectors to your Jed file. I've done it a few times and it's been easy and worked well. I don't think it will let you do any fancy test vectors ( Force vectors and the like) but it will help you to create simple functional test vectors.Article: 4006
Hi, I saw your reply on the speed increase in going from and FPGA to an ASIC. You said your experience indicated a 10 to 20 times increase. I havn't gotten to work on ASICs yet but I have done a few FPGAs. Why or what do you think causes such a dramatic speed increase. My only guess is that it might be caused by the ram type devices used in some FPGAs or maybe the "increased granularity" of the ASIC.Article: 4007
hi, sorry if this has been asked before. most of the fpga databooks (xilinx, altera, actel etc) mention their chip densities in terms of gate count. exactly what is the definition of gate in this ? does it refer to a basic gate such as a nand or something more complicated ? i have heard somewhere that the basic notion of gate is vendor specific. in this case how do make a true comparision of chips from two different vendors ? also some vendors mention usable gate count and some of them don't. how important is the usable gate count figure ? email replies will be appreciated. i will post a followup containing summary of the replies. thanks, navneet yadav email:yadav@cse.iitb.ernet.inArticle: 4008
I would like to get pointers to any work on custom computing machines that transform selected C (or Fortran) routines into FPGA netlists. I have found papers and links to PRISM-II, being done at the Lab for Engineering Man/Machine Systems at Brown University. Are there other configuration compilers available, either at universities or from vendors? What is the state-of-the-art in taking a C function that uses floating-point and compiling it to FPGAs? Is there any kind of automated scaling for changing floating-point (w/ ranges on the input variables) into integer-only replacements, and thus easily into FPGAs? (I've seen Dan McCracken's 1957 textbook that shows how to do this by hand, but I wonder if it has been automated and integrated into a configuration compiler. PRISM-II doesn't do flt-pt.) Thanks. -- Mark Smotherman, Computer Science Dept., Clemson University, Clemson, SC http://www.cs.clemson.edu/~mark/homepage.htmlArticle: 4009
David Pellerin (pellerin@seanet.com) wrote: : The following very good question was sent to us via email, so I thought I : would enlighten the "masses" about the difference between PeakVHDL Training : Edition and Cypress Warp 2: : accepts a limited subset of VHDL: RTL only as appropriate for Cypress : devices. Although it does include a simple gate-level simulator, you cannot : model general-purpose behavioral logic (a CPU, say, or a RAM) or write test : benches using Warp. : Accolade's PeakVHDL is a complete VHDL simulator allowing you to enter and : simulate an essentially unlimited number of different designs. You are not Do note that Cypress Warp2 release 4 support FPGA's too ....and will generate post synthesis VHDL models for a range of VHDL simulators (including Model Tech, Synopsys etc etc) and Viewlogic viewsim. This is for the PLDs, CPLDs, and FPGAs. (Warp2 has the FPGA place and route, timing analyzer, and viewer included.) The included NOVA simulator actually a JEDEC simulator. -Rich AulettaArticle: 4010
Alan Weir wrote: > > Does anyone know of a software package to generate test vectors for > simple PALS (22V10 etc). I'm using Warp 2 for the design and I don't > want to have to hand code the vectors into the Jedec file. > > -- Alan Dear old PLPL generates test vectors and runs simulation. The collection of batch files provided with the (free) s/w contained a utility to concatenate a Jedec fuse file and a Jedec vector file. Unfortunately, it didn't do the important job of stripping off any old vectors before adding the new ones! PLPL simulator has various quirks, eg vector with clock pin '0' followed by one with it '1' DOESN'T generate a clock transistion. If you can't find a copy of PLPL anywhere, let me know and I can email you a zip, which includes models of 22V10, most other 20 & 24 pin PLDs and some others. PLPL has been the standard PLD design tool for undergraduate teaching in the Department of Electronics and Computer Science at the University of Southampton for many years. We freely acknowledge the assistance of AMD who provided PLPL source allowing us to provide PLPL on a wide variety of platforms. Hand coding of vectors is not too bad, the problem is providing the proper checksums - if you get these wrong many IC programmers won't accept the file. On the subject of programmers, note that many programmers report vector test failures in fault-free PLDs exercised with entirely valid vector sets. I have found the latest Windows s/w for Data I/O Chiplab to be very good in this respect. At one time Stag (programmer manufacturer) sold a program called "PLDTEST" (or some such) which generated test vector patterns for maximum coverage of fuse patterns (ie comprehensive check that all fuses were in their correct state after programming). Tim Forcer tmf@ecs.soton.ac.uk PS - What do Cypress say? Have a look around in http://www.cypress.com/Article: 4011
AP wrote: > > *** FREE INTERNET! *** Forever! > ...lots more... and then asked you to PAY! So it aint free. Tim Forcer tmf@ecs.soton.ac.ukArticle: 4012
MarkCondit wrote: > .... Why or > what do you think causes such a dramatic speed increase. My only guess is > that it might be caused by the ram type devices used in some FPGAs or > maybe the "increased granularity" of the ASIC. The speed increase comes from the fact that the cells used in the gate array design have been optimized to perform the particular function they are designed for. FPGAs are necessarily general purpose circuits that consist of a logic array (be it a look up or fixed logic with muxes) that is capable of being configured for a large number of possible circuits. Even more important are the interconnects between logic elements in the FPGA vs the ASIC. In the ASIC, all connections are made in metal connected solely to the source and destinations for each signal. In the FPGA, the metal interconnects are segmented and connected in a network of connections controlled by transistors or one of many forms of fuses. All of these have considerable on-resistances, which combined with a higher capacitance (due to the many possible connections) slows the propagation time over the interconnect drastically. All this is the price paid to avoid the foundry, and in many cases well worth it. -Ray Andraka, P.E. Chairman, the Andraka Consulting Group 401/884-7930 FAX 401/884-7950 mailto:randraka@ids.net http://www.ids.net/~randraka/ The Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs. Services include complete design, development, simulation, and integration of these devices and the surrounding circuits. We also evaluate,troubleshoot, and improve existing designs. Please call or write for a free brochure or visit our web site.Article: 4013
Hi is anyone else using the Beta release of XACT step fpr the xilinx 6200 series? I need to trade a few opinions on placement strategies.Article: 4014
Hi, I had the same problem and in my case the reason was a poor electronic design. The done signal connected to the processor was equipped with a resistor with higher impedance than the internal pull-up resistor on the done signal. This meant that the done signal actually did go high but the signal never reached the processor. I discovered this by simply measuring the voltage on the xilinx chip and on the processor. /PerArticle: 4015
Mark Smotherman mark@hubcap.clemson.edu wrote: >I would like to get pointers to any work on custom computing >machines that transform selected C (or Fortran) routines into >FPGA netlists. Try: http://www-mp.informatik.uni-mannheim.de/groups/mass_par_1/projects/ede.html This is a project for a high energy physics experiment but probably has more general applications. Their SpC compiler is a "High-level Language Compiler, which converts a C-Dialect into vhdl code for the SYNOPSYS vhdl compiler"Article: 4016
Mark Smotherman (mark@hubcap.clemson.edu) wrote:
: I would like to get pointers to any work on custom computing
: machines that transform selected C (or Fortran) routines into
: FPGA netlists. I have found papers and links to PRISM-II, being
: done at the Lab for Engineering Man/Machine Systems at Brown
: University. Are there other configuration compilers available,
: either at universities or from vendors?
: What is the state-of-the-art in taking a C function that uses
: floating-point and compiling it to FPGAs? Is there any kind of
: automated scaling for changing floating-point (w/ ranges on the
: input variables) into integer-only replacements, and thus easily
: into FPGAs? (I've seen Dan McCracken's 1957 textbook that shows
: how to do this by hand, but I wonder if it has been automated
: and integrated into a configuration compiler. PRISM-II doesn't
: do flt-pt.)
: Thanks.
Erm, there is such a system in development, but I can't remember the name.
However, the following URL will get you pretty close to where you want to
go:
http://HTTP.CS.Berkeley.EDU/Research/Projects/brass
It has a pointer to a site about the compiler used.
Cheerio,
Ray
--
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Article: 4017Hello I have problem using XACT STEP 6.0.1. I cannot install win32S software. Installation software says "successfully installed." But FREE CELL game soft causes MS-DOS error 21. And the setup soft does not go on. The O.S. of my PC is DOS6.2 and windows3.1. And any other versions of XACT or Windows have not been installed in my PC. I tryed this setup with Compac Prolinea 5133 and Fujitsu FMV 5133ED4. In both case, I have same result. Does anyone know a good solution? Any help is greatly appreciated. Thanks in advance, - YuichiArticle: 4018
1997 ACM/SIGDA Fifth International Symposium on
Field-Programmable Gate Arrays
Sponsored by ACM SIGDA, with support from Altera, Xilinx, and Actel
Monterey Beach Hotel, Monterey, California
February 9-11, 1997
(Web page: http://www.ece.nwu.edu/~hauck/fpga97)
The annual ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
is the premier conference for presentation of advances in all areas
related to the FPGA technology. The topics of interest of this symposium
include, but are not limited to:
o Advances in FPGA architectures, including design of programmable logic blocks,
programmable interconnects, programmable I/Os, and development of new
FPGAs and field-configurable memories.
o New CAD algorithms and tools for FPGAs, including new algorithms for
sequential and combinational logic optimization, technology mapping,
partitioning, placement, routing, and development of new FPGA synthesis or
layout systems.
o Novel applications of FPGAs, including rapid prototyping, logic emulation,
reconfigurable custom computing, and dynamically reconfigurable
applications.
o Advances in field-programmable technology, including new process
and fabrication technologies, and field-programmable analog arrays.
Authors should submit 20 copies of their original work by September 27, 1996.
Each submission should include an 100-250 words abstract, and is limited
in length to 12 pages (including figures and tables, minimum point size 10).
Notification of acceptance will be sent by November 18, 1996.
A proceedings of accepted paper will be published by ACM.
Authors must assign copyright of their accepted papers to ACM as a condition
of publication. Final versions of accepted papers will be limited
to seven pages, and must be submitted by December 6, 1996.
All submissions should include the e.mail addresses of the authors, as all
correspondence with authors will be done via e.mail.
Submissions should be sent to:
Prof. Jason Cong
FPGA'97 Program Chair
UCLA Computer Science Department
4711 Boelter Hall
Los Angeles, CA 90095
Phone: (310) 206-2775, Fax: (310) 825-2273, E.mail: fpga97@cs.ucla.edu
Organizing Committee:
General Chair: Carl Ebeling, University of Washington
Program Chair: Jason Cong, UCLA
Publicity Chair: Scott Hauck, Northwestern University
Finance Chair: Jonathan Rose, University of Toronto
Local Chair: Pak Chan, UC Santa Cruz
Program Committee:
Michael Butts Quickturn
Pak Chan UCSC
Jason Cong UCLA
Carl Ebeling U. Washington
Masahiro Fujita Fujitsu Labs
Scott Hauck Northwestern Univ.
Dwight Hill Synopsys
Brad Hutchings BYU
Sinan Kaptanoglu Actel
David Lewis U. Toronto
Jonathan Rose U. Toronto
Richard Rudell Synopsys
Rob Rutenbar CMU
Gabriele Saucier Imag
Martine Schlag UCSC
Tim Southgate Altera
Steve Trimberger Xilinx
Martin Wong UT Austin
Nam-Sung Woo Lucent Technologies
+-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
| Scott A. Hauck, Assistant Professor |
| Dept. of ECE Voice: (847) 467-1849 |
| Northwestern University FAX: (847) 467-4144 |
| 2145 Sheridan Road Email: hauck@ece.nwu.edu |
| Evanston, IL 60208 WWW: http://www.ece.nwu.edu/~hauck |
+-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
Article: 4019After optimizing save the top level design in a DB file. Then run the following command, from Design Compiler: replace_fpga Then finally save it as an EDIF file. Best regards, Michael Vincze vincze@ti.com In article 314D@iti.mu-luebeck.de, Andreas Doering <doering@iti.mu-luebeck.de> () writes: >Hello >I have problems using MAXPLUS2 6.2 (solaris) >together with the synopsys interface when compiling for >FLEX8000 or FLEX10k families. >When reading the EDIF netlists generated by FPGA compiler >with target/link library flex8000_fpga.db / flex10k_fpga.db >I get the error "Can't find Design file 'LUT'". >I have no problems when compiling for CPLD devices. >So I think my pathes are setup right. >Thanks for any help > >-- >--------------------------------------------------------------- > Andreas Doering > Medizinische Universitaet zu Luebeck > Institut fuer Technische Informatik > Email: doering@iti.mu-luebeck.de >----------------------------------------------------------------Article: 4020
In article <50cets$rgd@news71.supernews.com>, freenet1@ez1.com (AP) wrote: > Amazing Course on Audio Tape describes STEP by STEP what your Internet Service > Act NOW! Limited Supply! Only $14.95 + 3.50 Shipping > "LIMITED SUPPLY of an audio tape." That must be the high point of marketing bullshit. Peter AArticle: 4021
In article <322593d1.7813905@news.alt.net>, Peter <ft63@dial.pipex.com> wrote: > >You would need a sizeable FPGA for this, especially as the S-boxes >have 6 inputs, and the CLBs have only 5 (how inconvenient!). > >You will need a means of converting the S-boxes into logic or boolean >equations, which is a pain because they don't minimise (it would be a >pretty weak algorithm if they did minimise). Else you can possibly >implement them using XC4k RAM, and load them from the Host CPU's >firmware. Warp 2 from Cypress does well for converting to logic equations, it will report all the terms even if they won't fit in the target device. You write a VHDL table lookup (or otherwise, Warp 2 minimizes to identical results) version of the S Boxes. I've written C programs to generate the VHDL. The best way I have come accross of putting S Boxes into too narrow CLBs: For each row and each output bit of an S Box, you can specify which column addresses yield ones (or zeros). In four input CLBs this yields 16 CLBs, in dual four input lookup CLBs, you can implement one level of row multiplexers in the same CLB, yielding 8 CLBs. The remaining row bit is used in 2:1 muxes for each of the 4 S Box outputs. (4 more CLBs). This is a constant width solution, requiring no minimization, (you can write a C program to express it in VHDL). You may be able to hide the XOR with L here too. > >I have never actually done this, but when I looked at this problem a >few years ago I concluded that the best way to do the S-boxes was >using an external EPROM. The rest of the algorithm then becomes quite >easy. > Try Lucent Technologies FPGAs, which have CLBs that can be organized as 6 input.Article: 4022
In article <DwtJ51.7BJ@world.std.com>, John Cooley <jcooley@world.std.com> wrote: >John Cooley <jcooley@world.std.com> wrote: >>The biggest surprise came when I later compiled the 36 additional responses >>from EDA employees. This group was three times as likely (42 percent versus >>the EDA users' 13 percent) to grant Cadence's injunction. And EDA makers >>were twice as likely (53 percent vs. 27 percent) to see the courts as >>competent -- which helps explain why the EDA industry is so litigious! >This result from the survey still kind of stumps me. Why are EDA vendors >significantly more legalistic than their customers? I can't seem to figure >this one out. Any insights anyone? Uh, yeah. Can you say "small sample size"? For a sample of 36 EDA employees, the difference between the expected and actual percentages is about 9-10 responses. Throw in the fact that it's a self-selected sample, and things get even worse. So if EDA employees in general hold exactly the same opinions as EDA users, but you also got responses from a dozen or so Cadence/ex-Cadence employees who followed the company line, you would get the kind of results you report here. I think the sample size is too small to draw any meaningful conclusions about whether or not EDA vendors really do hold different views from EDA users on this issue. That doesn't keep people from spouting off about it, of course. And there might be some real differences - we just don't have enough info to be sure. -- Dave Wallace (wallace@netcom.com) It is quite humbling to realize that the storage occupied by the longest line from a typical Usenet posting is sufficient to provide a state space so vast that all the computation power in the world can not conquer it.Article: 4023
fuseda wrote: > > Hello > I have problem using XACT STEP 6.0.1. > I cannot install win32S software. > Installation software says "successfully installed." > But FREE CELL game soft causes MS-DOS error 21. > And the setup soft does not go on. > > The O.S. of my PC is DOS6.2 and windows3.1. > And any other versions of XACT or Windows > have not been installed in my PC. > > I tryed this setup with Compac Prolinea 5133 > and Fujitsu FMV 5133ED4. > In both case, I have same result. > > Does anyone know a good solution? > Any help is greatly appreciated. > > Thanks in advance, > > - Yuichi Been there, done that The version of WIN32S on the CD is not the latest. You caa download the latest version from Microsoft, www.microsoft.com - I believe. This will cure the DOS Error 21.Article: 4024
Maya Reuveni wrote: > > hi everybody, > I designed a board with 5 xilinx devices > 2 xc4013E & 3 xc4005H > I daisy chained all the parts and connected to the xchecker connector. > I made a xxx.mcs (xxx.exo too) into a 128K bytes prom > and the done signal did not go high ..... > any ideas why ? > what should I check ? > thanks > -- > > Maya Reuveni Tel: 972-9-986976 > Manager of Hardware Department Fax: 972-9-986980 > HaTaasiya 9, Raanana 43100, Israel. E-mail: maya@asp.co.il First thing to check is that the preample is coming out of each chip at the start of program. It should be present with 1 CCLK delay for each chip in the daisy chain. Xilinx has an app note with many hint on thier web site - it's worth downloading.
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Compare FPGA features and resources
Threads starting:
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