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bxa8@po.CWRU.Edu (Bassam Al-Kharashi) wrote:
>Does the security fuse protect the fpga from beeing able to read
>it?
>--
>Bassam A. Al-Kharashi
>email bxa8@po.cwru.edu
Yep. On the ACT 1 series it also stops you reading the Silicon
Signature.
BFN
Julian.
--
---------------------------------------------------------------------
CoxJA@augustsl.demon.co.uk error: smartass.sig not found
---------------------------------------------------------------------
Article: 3876Rafiki Kim Hofmans (tw38966@vub.ac.be) wrote: : Hi, : can someone help me figure out wath the following error means : : error 301 : delay 7.9 on Pin I0 of AND XSYM524 is not annotated. : The pin is connected to the signal $6I32/M2OUT8. : This error appears while the flow engine is running the timing. : Thanks in advance ! : Kim I solved the problem, I upgraded form 32megs to 64megs and everything runs fine now ! -- ============================================================================== ************************************ * Hofmans Kim * * * * tw38966@vub.ac.be * * khofmans@info.vub.ac.be * * * * Brouwerijstraat 62 * * 1630 Linkebeek * * Belgium * * * * 32-2-3771012 * * * ************************************Article: 3877
Hi, Thanks for your information. FAEs here didn't know how to solve my problem. In fact, one of tehm met the same problem. After trial-n-error, I found it's the incompatibility of Windows W32s and MAXPLUS2. It's not concerned about hardware environment as I thought previously. Thus it worked after I re-installing Windows. ( Here I deleted Windows before re-installation since I didn't know hoe to uninstall W32s) :) Tony Clark wrote: > > I had the local Altera FAE around yesterday and he did mention that there > were some bugs in 6.2O that effected the 10k family. He did say there > was a fix available. >Article: 3878
-After the security fuse is programmed, the device is unreadable. The interior of the device cannot be read or probed by anyone. - JEFF WETCH wetch@actel.com Actel Field Application EngineerArticle: 3879
I just finished reading the Xilinx 1996 Annual Report on http://www.xilinx.com/finance/annual96/home.htm. The shareholders' letter mentioned that Xilinx now has four primary product focusses, namely the XC9500 family, high-density FPGAs, the HardWire products, and CAD tools. What about the much-advertised 1995 reconfigurable FPGAs, and particularly the XC6200 family? Is the latter going to follow the same path as the antifuse XC8100 FPGA i.e. will it also be dropped? Jean-Michel VuillamyArticle: 3880
Do it with a counter, followed by a latch. >Hi , > >I need to implement a mono-stable MVB inside an Altera PLD. Could anyone >help ?? > >LEEArticle: 3881
>If you are gating clocks you are not synchronous! My understanding of "synchronous" is that everything changes together on a common clock edge. Is it perfectly permissible to gate a clock to a particular D-type, with an AND gate, provided the gate signal is setup and held with proper margins around the point where the clock will change. A theoretical problem occurs when the AND gate is in fact a lookup table, as it will be in all Xilinx chips. Generating gates using a lookup table is dangerous because of decoding glitches. However, it is quite obvious that this restriction would make using Xilinx parts extremely hard to use, if not downright impossible, and I have checked with Xilinx that the design of their CLB logic block guarantees glitchless decoding. So it is OK to gate a clock even in an FPGA. Peter.Article: 3882
Peter wrote: > > >If you are gating clocks you are not synchronous! > > My understanding of "synchronous" is that everything changes together > on a common clock edge. > > Is it perfectly permissible to gate a clock to a particular D-type, > with an AND gate, provided the gate signal is setup and held with > proper margins around the point where the clock will change. > > A theoretical problem occurs when the AND gate is in fact a lookup > table, as it will be in all Xilinx chips. Generating gates using a > lookup table is dangerous because of decoding glitches. However, it is > quite obvious that this restriction would make using Xilinx parts > extremely hard to use, if not downright impossible, and I have checked > with Xilinx that the design of their CLB logic block guarantees > glitchless decoding. So it is OK to gate a clock even in an FPGA. It's not this easy. By gating the clock to a FF with an AND gate, you have delayed the clock by a CLB and wiring delay and probably placed the clock on local interconnect. If you pass the output of this FF to the input of another FF driven by the same logical clock, the place and route tools must connect the gated clock to the 2nd flip-flop again using local interconnect. If the wiring delay is sufficient you will have setup/hold problems. If the gated-clock FF drives another FF which does not have it's clock gated (or is gated diffently), you will also risk setup/hold problems. This can be made to work if you contrain placement to guarantee that clock skew travels backwards on the FF chain (last FF clocks first), but you still lose significant system speed and gain a documentation and design headache. You must also maintain tight control over the clock gate. What happens if it causes the generation of a 0.5ns wide clock? The CE input to the CLB will be subject to the FF's metastability (which Xilinx attempts to reduce to insignificance by design) while runt clocks will certainly raise havoc in your design. Regards, ScottArticle: 3883
thomas wrote: > > HI, I WOULD LIKE TO KNOW HOW TO MODIFY THE MONOSTABLE VIBRATOR 74HC123 > IN TO THE TTL CIRCUIT, ESPECIALLY IN ALTERA MAX 7000 ISP DESIGN OR > ORCAD SOFTWARE. CAN ANYONE HELP ME ? > REGARDS > -LEE, MALAYSIA. Hi, best idea: forget it! If you need a function like this you should take a counter and decode appropriate values. Relying on a input threshold that evaluates the slow slope of an R-C network does not work as you would expect. AlfredArticle: 3884
Dear readers of the AI-Neural Nets and FPGA newsgroups, I would be very interested in knowing how mature current hardware designs of Neural Nets are by using FPGA architectures. My request to fill out the questionnaire below goes to anyone who has attempted or is attempting to design NN hardware by FPGA. Both success cases and failures are welcome. Perhaps you know of someone who is involved in designing NN HW on FPGA. Please send them a copy of this mail. Your assistance is much appreciated. The results of this inquiry will be posted on both newsgroups. But for now, the follow-up has been set to the AI-Neural Nets newsgroup. If you wish to contribute to the questionnaire, send your reply by e-mail to the undersigned, and feel free with any additional comments. After approximately 14 days I will summarize your responses and post the results. Perhaps we could delay a possible discussion until the final outcome is posted. Of course, if more entries come in later, I will rewrite the summary and post it again after some reasonable time. Thank you very much in advance, Aryan Saed (saed@engn.uwindsor.ca) Univ. of Windsor, Dept. of Electrical Engineering, Windsor ON, Canada QUESTIONNAIRE------------------------------------------------------------- Please copy this section in your reply and include each answer right after the question. There are 18 Questions, brief answers are sufficient, long ones are welcome. ---- About the FPGA devices What type of FPGA did you use (manufacturer, type)? e.g. Xilinx 4002 How many FPGA's did you cluster? e.g. 10 together or just one What throughputrate did you achieve (bit parallel, bit serial) ? e.g. 20Mbits/s serial , 1.1Mbyte (16bits parallel) What percentage of utilization did you achieve or how many blocks were available, how many used (switching blocks, logic blocks, input/output blocks)? e.g. 24 of 98 CLB's per device What type of functional block would you consider usefull for a NN tailored FPGA? Your additional comments: ---- About the Neural Network What type of Neural Network did you implement? e.g. feed forward network Precisely which part of the NN did you implement? e.g. only weight multiplication or complete 4:6:2 Network How much on-device learning did you include? e.g. gradient descents included Which word size did you use, which number representation? e.g. 8bit unsigned x 8bit signed = 16 bit binary How did you realize the activation function? e.g look-up table Did you implement a pipe line? What concessions did you make, what limitations were made on the NN in order to make it suitable for FPGA implementations? e.g. hard limiting activation What type of NN would you consider distinctively suitable for FPGA implementation? Your additional comments: ---- About your publications Have you published or presented your design and results (where, when)? e.g. Encyclopedia Britannica 1994 (just kidding) ---- - OPTIONAL - About your experience in this matter (the following answers, if provided, will NOT be linked to your name/organization in the outcome ) Were you satisfied with the overall design, in particular with respect to the performance speed, circuit complexity, interconnectibility of neurons, etc? Were you limited in the choice of FPGA's? Would you prefer to use a different device in future? Why? Do you have experience with other forms of NN implementations (Software, hardware: accelerator cards, analog/digital implementation)? Your additional comments: ---- About yourself ( so that I can thank you and give you credit) Your Name: Your Organization: Your E-mail (please include): Shall I include your name and/or organization in the credits? How about your e-mail? Thank you very much for your time and effort! ------------------------------------------------------------------------------Article: 3885
Hello, I am doing a design which 70% fills a XC3090. I am using the latest XACT6 place/route software (front end is Viewlogic, DOS version) and this version of XACT always completely routes the design. But it does not always appear to connect it up correctly. I can compile it once and everything but one part, e.g. just one 8-bit counter, works fine, and after another compilation of the same design that counter works fine but there is a fault elsewhere. The symptoms resemble a simple case of the software not being able to fully connect up the design, but there are no error messages. The design is fully synchronous, and the areas which have "failed" contain nothing which might be suspicious, as far as I know. Is it possible to get less-than-100% connections without error messages? Peter.Article: 3886
Mr. Lewis,
Otto's sorry that you object to seeing your associates get jobs. Otto
thinks everyone needs one; Otto can't sell them software if they don't
have money.
Otto's sorry that you object to seeing them save money on software.
Otto thinks most people pay too much!
Otto's sorry that you have to press the <down-arrow> key to skip a
post or two that you're not interested in. Otto thinks that most
people will just skip those messages.
Otto is an authorized reseller of most major CAD products available
today even though his WWW page focuses on AutoCAD.
Otto would love to save you money on your next software purchase; just
shoot him a note in what you're interested in!
Love,
Otto (otto@ottocad.com)
http://www.ottocad.com
"Jim Lewis, ASIC and HDL Consultant" <telejim@teleport.com> wrote:
>Recently, I have noticed that some of the Job (and ad) postings that have
>been posted to comp.lang.vhdl were not even for VHDL type jobs.
>I became a little concerned that some of the posters are missing
>the concept of what the news group was for, so I sent them email to
>see what was up and to ask that if they did not have something on topic
>not to post it here.
>What I learned was that this type of posting was intentional.
>The following is a direct quote:
>B> "No, there isn't anything specific to VHDL in the listings, but
>B> it has been my experience in the past that quite often individuals who do
>B> have VHDL knowledge have DSP in there background as well."
>So you might ask yourself, is this a fluke or will it continue.
>Here I will quote the entire contents of a follow up email.
>B> Wow, I can not believe that the only thing you got out of my note was that I
>B> was going to continue to post non-VHDL messages to the VHDL newsgroup. I
>B> guess people will read into things what they want to. I took my best shot at
>B> explaining things to you. But I will try one last time As I told you before,
>B> it has been my experience in the past and now I can tell you it is also my
>B> experience in the present (as I have received resumes from individuals who
>B> saw my posting guess where?) that individuals with VHDL experience in many
>B> instances have DSP in their background as well. I have just sent over more
>B> than 20 candidates for seven open positions to my client. EVERY single one
>B> of them responded to one of my postings on the technical news groups. Three
>B> of them in particular were from the VHDL user group. So again, I know none
>B> of this will make any difference to you but I do what I do because it works.
>B> I understand that you are not interested in my postings and I do respect
>B> that. However, there are obviously people out there who do care - please try
>B> to respect that as well.....
>In fact, the person with whom I corresponded also felt that very few
>people object to this type of posting. Going back to the first email,
>I quote:
>B> "My responses are about 100 to 1 favorable to unfavorable. I have so few
>B> negative responses that I do take the time to write a thoughtful answer to
>B> the issues at hand as I am doing with you
>I am do not have an extremist point of view reguarding posting jobs
>(or advertising). All I care is that if someone is going to post
>a job or advertise that they stay within the scope of the newsgroup
>(and hence only post VHDL jobs to the VHDL news group, ...).
>As I pointed out earlier, these people feel that they are getting an
>overwelmingly favorable response to what they are doing and do intend to
>continue. Perhaps they will set a precedence and others will join.
>If you disagree with them, a simple polite email would do.
>I have included the following as an example and a good way to
>get started (do include the postmaster of the site that the
>person emailed from):
>====================
>Mail To: BKOjobs@aol.com, postmaster@aol.com
>subject: Your off topic job postings to comp.lang.vhdl
>Dear Postmaster,
> Please disable, BKOjobs@aol.com, account, as they are not repecting
>our newsgroups charter.
>Dear Bridget,
> Please stop posting non-related job postings to comp.lang.vhdl.
>Thank You,
>A concerned newsgroupie
>======
>While you are at it, you might send email to otto@ottocad.com
>concerning his autocad advertisments in comp.cad.synthesis. He is
>also of the opinion that no one objects to him spamming the newsgroup.
>In fact postmaster@ottocad.com (probably otto himself) responded
>with the following:
>O> In checking the logs, I find that Otto has posted approximately once every
>O> two weeks to comp.cad.systhesis for a total of five posts.
>O> In looking at the postings (dating back to 10/95) in this group as provided
>O> by our newsfeed, I can find only one objection to Otto's postings.
>Feel free to let them know.
>=======
>I feel the personal, polite follow up will bring much faster and
>hopefully more conclusive results than posting in the newsgroup.
>Cheers,
>Jim Lewis
>telejim@teleport.com
Article: 3887Peter (ft63@dial.pipex.com) wrote: : Hello, : I am doing a design which 70% fills a XC3090. I am using the latest : XACT6 place/route software (front end is Viewlogic, DOS version) and : this version of XACT always completely routes the design. : But it does not always appear to connect it up correctly. I can : compile it once and everything but one part, e.g. just one 8-bit : counter, works fine, and after another compilation of the same design : that counter works fine but there is a fault elsewhere. : The symptoms resemble a simple case of the software not being able to : fully connect up the design, but there are no error messages. : The design is fully synchronous, and the areas which have "failed" : contain nothing which might be suspicious, as far as I know. : Is it possible to get less-than-100% connections without error : messages? : Peter. Did you verify the failure on more than one part? John EatonArticle: 3888
In article <3211c89b.9319399@news.alt.net> ft63@dial.pipex.com (Peter) writes: > >>If you are gating clocks you are not synchronous! > >My understanding of "synchronous" is that everything changes together >on a common clock edge. Yes, thats right. > >Is it perfectly permissible to gate a clock to a particular D-type, >with an AND gate, provided the gate signal is setup and held with >proper margins around the point where the clock will change. NO, NO, NO, NO, NO, (did I say NO?) When you gate the clock, it will have to go through a gate and routing to get to the clock pins of the flip-flops. This will add delay, and if you route to multiple FFs, then you will probably be using local routing resources, which means different delays to each FF's clock pin. All of these FFs on the gated clock will be clocked later than those FFs on the non gated clock. You will have race conditions or timing problems of at least the following forms: 1) from a gated clock FF to a non gated clock FF, the Q to D path will be less than a clock period, by anything from 0 nS to the max delay through the clock gate and its routing. 2) A CE of such a FF, from a Q of a FF not on the gated clock net may fail to meet hold time: intermittent behaviour or metastability. 3) A D of such a FF, from a Q of a FF not on the gated clock net may fail to meet hold time: intermittent behaviour or metastability. 4) A D of such a FF, from a Q of a FF on the gated clock net may fail to meet hold time because of less routing delay to the source FF: intermittent behaviour or metastability. 5) other variations. Xilinx puts global clock nets on chips for a good reason: Since they can't guarantee minimum transit time of signals through gates and routing (only maximum delays. Don't ask for minimums because that would require them to guarantee that they wont improve the product in the future, or sell you faster parts at a slower speed grade price), the global clock nets are specially designed, pre-routed nets that guarantee a worst case skew to ANY FF's clock pin to be less than the clock to out time of a FF. This guarantees that you never have hold time violations due to a path being too fast. Note: you can have setup time problems if a path is too slow, but that is a system design issue. Note: in fast systems, without well designed clock nets, the worstcase situation can be with a shift register. > >A theoretical problem occurs when the AND gate is in fact a lookup >table, as it will be in all Xilinx chips. Generating gates using a >lookup table is dangerous because of decoding glitches. As you say next, the LUTs are designed not to have this problem. >However, it is >quite obvious that this restriction would make using Xilinx parts >extremely hard to use, if not downright impossible, and I have checked >with Xilinx that the design of their CLB logic block guarantees >glitchless decoding. Almost true. If only a single input is changing, and the output is the same regardless of its value, the there are no glitches. If the output value is different, you are NOT guaranteed a monotonic transition, but I believe you will get one. If on the other hand you were changing two signals at the same time, and an intermediate state specified an opposite value, then you could get a glitch, but this would be your own fault, and would only effect your design if you had done something stupid with the output, like connecting it to an asynchronous input to a FF. (For reference, these asynchronous inputs are: Async-Set, Async-Reset, AND.... the CLOCK pin). A gate that glitches on its output while transitioning from one state to another, and feeds a D pin on a FF in a synchronous system is OK, providing it stable before the setup time starts. Thats why synchronous design works. >So it is OK to gate a clock even in an FPGA. Not according to me. > >Peter. Philip Synchronous FreidinArticle: 3889
In article <3211f084.17787296@news.alt.net> ft63@dial.pipex.com (Peter) writes: >Hello, > >I am doing a design which 70% fills a XC3090. I am using the latest >XACT6 place/route software (front end is Viewlogic, DOS version) and >this version of XACT always completely routes the design. > >But it does not always appear to connect it up correctly. I can >compile it once and everything but one part, e.g. just one 8-bit >counter, works fine, and after another compilation of the same design >that counter works fine but there is a fault elsewhere. Is this using one of your gated clocks? > >The symptoms resemble a simple case of the software not being able to >fully connect up the design, but there are no error messages. > >The design is fully synchronous, and the areas which have "failed" >contain nothing which might be suspicious, as far as I know. > >Is it possible to get less-than-100% connections without error >messages? I have never seen it fail to route, and not report it. As a check though, here are two other things you could do: 1) Create a post routed simulation, and run it with the same test vectors you used for the unit delay simulation you did before place and route. If they behave the same, the design must be routed, as the post routed simulation database is derived from the LCA file. 2) In XDE, run the DRC option. It will tell you if anything is incorrect with the design's routing, such as unrouted destination nodes. 3) (disgusting but might work under extreme duress) run the LCA file thru LCA2XNF, and the result thru XNF2WIR, and the result thru Viewgen to recreate the schematic. While this will show you what got built, viewgen's schematics are close to useless for anything more than a 100 gates, and your design sounds like about 4000 gates (70% of a 3090). > >Peter. Good luck Philip.Article: 3890
Hi, 1) If I want to simulate my routed design, all the signals connected immediately to an I/O pad are unknown. How can I assign values to the 'unknown signals' ? 2) when I want to simulate my original design, it seems that the startup symbol doesn't work properly. If I assign an attribute "init=s" to a flip-flop, the start value is always zero. Can someone help me out ? thanks in advance ! Kim -- ============================================================================== ************************************ * Hofmans Kim * * * * tw38966@vub.ac.be * * khofmans@info.vub.ac.be * * * * Brouwerijstraat 62 * * 1630 Linkebeek * * Belgium * * * * 32-2-3771012 * * * ************************************Article: 3891
Otto's CAD Auction wrote: > Otto's sorry that you object to seeing your associates get jobs. ... > Otto's sorry that you object to seeing them save money on software... > Otto thinks most people pay too much! > Otto's sorry that you have to press the <down-arrow> key to skip... > Otto is an authorized reseller of most major CAD products available ... > Otto would love to save you money on your next software purchase; just > shoot him a note in what you're interested in! Otto just lost a butt load of business.Article: 3892
Don Husby <husby@fnal.gov> wrote:
>Otto's CAD Auction wrote:
>> Otto's sorry that you object to seeing your associates get jobs. ...
>> Otto's sorry that you object to seeing them save money on software...
>> Otto thinks most people pay too much!
>> Otto's sorry that you have to press the <down-arrow> key to skip...
>> Otto is an authorized reseller of most major CAD products available ...
>> Otto would love to save you money on your next software purchase; just
>> shoot him a note in what you're interested in!
>
>Otto just lost a butt load of business.
Otto is clueless that the Cadence, Mentor, VHDL, Verilog and synthesis
newsgroups he spams have NOTHING to do with the type of CAD software he
peddles.
Otto has psychological problems when he refers to himself in the 3rd
person instead of 1st person form.
- John Cooley
Part Time EDA Consumer Advocate
Full Time ASIC, FPGA & EDA Design Consultant
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 4599 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 3893Philip, No, my other post about gated clocks was just hypothetical, and intended to say that there are cases where gating a clock is *not* unreliable. I would never gate clocks in any of the circumstances you describe. I will try your other suggestions if I cannot make it compile over the next few nights! Thanks. (It takes 6 hours on a P90). Peter.Article: 3894
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more standard busses (VME, PCI, Futurebus+); one or more micro-processors
(68XXX, XX86, i960, MIPS); and programmable logic (PALs, CPALs, FPGAs).
Experience in VHDL or Verilog a plus. Must be a self-starter with good
communication & interpersonal skills.
CCT offers competitive salaries, excellent benefits & long-term stability.
E-mail your ascii-text resume with salary history to cjohnson@c2t.com or via US. mail to:
Attn: Cindy Johnson
1555 So. Sinclair St.
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cjohnson@c2t.com
--
mankeny@netcom.com
Article: 3895In article 17787296@news.alt.net, ft63@dial.pipex.com (Peter) writes: ... > I can > compile it once and everything but one part, e.g. just one 8-bit > counter, works fine, and after another compilation of the same design > that counter works fine but there is a fault elsewhere. ... > Is it possible to get less-than-100% connections without error > messages? This sounds very familiar. I have struggled with similar problems repeatedly with XC3000 and XC4000 series parts. My usual strategy is to make sure clocks are placed onto clock nets and to increase timing constraints on the router. I will also target key nets that seem to be having problems between designs by giving them a little higher priority or frequency constraint. When all else fails, I'll redesign problematic areas to be functionally the same, but implemented slightly differently. Some day soon, I hope to evaluate FPGAs from other manufacturers to see if they suffer from the same problems. ---------------------------------------------------------------------- Jeff Hunsinger jeffh@oakhill-csic.sps.mot.comArticle: 3896
In article <3211f084.17787296@news.alt.net>, ft63@dial.pipex.com (Peter) writes: [snip] > But it does not always appear to connect it up correctly. I can > compile it once and everything but one part, e.g. just one 8-bit > counter, works fine, and after another compilation of the same design > that counter works fine but there is a fault elsewhere. > > The symptoms resemble a simple case of the software not being able to > fully connect up the design, but there are no error messages. [snip] I had one like that many years ago. It turned out to be a gross timing blunder. The problem was obvious after I looked in the right place. I had a signal that ran all the way across the chip. The worst case timing was way over the clock speed, but it worked at normal temperature and VCC. When I changed something unrelated, the routing for that signal got a bit longer and things stopped working. [This was using older tools that weren't very helpful about checking timings. The long path was in the timing report I had made, but it was burried in the middle of a mass of carry chains that had many cycles to settle so I skimmed over that area too fast.]Article: 3897
Hey Otto, if you can't sell us any Cadence Design Systems software,
Mentor Graphics, or any of the other groups you post to, then quit
posting there! That'd be even easier than making me hit the "next"
key!!!
Since this damn WWW thing started, advertising has gotten out of hand
on the USENET groups...
Otto's CAD Auction wrote:
>
> Mr. Lewis,
>
> Otto's sorry that you object to seeing your associates get jobs. Otto
> thinks everyone needs one; Otto can't sell them software if they don't
> have money.
>
> Otto's sorry that you object to seeing them save money on software.
> Otto thinks most people pay too much!
>
> Otto's sorry that you have to press the <down-arrow> key to skip a
> post or two that you're not interested in. Otto thinks that most
> people will just skip those messages.
>
> Otto is an authorized reseller of most major CAD products available
> today even though his WWW page focuses on AutoCAD.
>
> Otto would love to save you money on your next software purchase; just
> shoot him a note in what you're interested in!
>
> Love,
> Otto (otto@ottocad.com)
> http://www.ottocad.com
--
Dave Clark - Austin, Texas david.clark@analog.com
http://www.io.com/~dclark/ dclark@io.com
Nothing increases the size of a fish like fishing all by yourself
Article: 3898Tim Lindquist wrote: > > Create a top level entity and architecture with the bus oriented > signal eg counter(7 downto 0). Then instantiate the synthesised > version as a component under this top level and manually join > counter(x) => counter_x in your port map Yes, of course, it's OK for top-level signals... But when you want to look at internal busses, you can forget it !!! -- Michel EFTIMAKIS........................Internet : Michel.Eftimakis@vlsi.COM DECT Design Engineer....................Phone....: (33) 92 96 11 19 VLSI TECHNOLOGY France..................Fax......: (33) 92 96 11 01 505, Route des Lucioles.................CellularP: Sophia Antipolis - 06560 Valbonne FRANCEArticle: 3899
If anyone could be on any assistance, I would greatly appreciate it. I am trying to find an experienced digital electrical engineer with extensive knowledge of FPGA design and synopsis tools. I am not having any luck. If anyone would know of anyone who has these skills who might me interested in a 6 month+ contract position in Illinois or if anyone could direct me toward any professional organizations which might be able to help me, I would appreciate it. Please contact me via e-mail at cnielsen@notes.techni-source.com or call me at (800)330-9961, I would appreciate it.
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