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hi,all
i am facing a problem when obtaining port signals with chipscope in
edk.i creat an user ip connecting opb bus (based microblaze). I can get
only one right data from ports,but following samples(total
16384 samples) are in high status (High-impedance state)at all ports ,then
the signal data are 1,8,64,0(width=8 port)or 0,2,16,128,1024,8192
(width=16
port) and so on.then these data display with loop. what is the problem?
who can help me.
thanks in advance..
---------------------------------------
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Article: 144351Hi, how do you engineers evaluate your design performance for a specified FPGA? My opinion is that if you satisfy timing requirements, I think your performance is good. Because resource to a specified FPGA is fixed, I don't care about your resource usage. How do you think about this? Please comments. regards chen yongArticle: 144352
> I don't think anyone would force you to do something which you're > uncomfortable doing. Apart from the wife (and not in 'interesting' ways). > It's certainly easier to work with single > synchronous clock but it's possible to do with multiple generated ones > too. My only real experience of ripple & gated clocks was 8 years or so ago when a client brought me in to 'tweak' an FPGA that was 'almost working'. It had been created by a board designer who had approached the FPGA design as if he was designing a PCB. There were bits in VHDL, AHDL and schematics with ripple and gated clocks all over the place, far too many to analyse and constrain to get working. They were getting different performance and behaviour every build. The tools reported an fmax of ~20MHz, they were clocking it at 50MHz! I re-wrote it in about six weeks after which it just worked, every build. I know asynchronous design techniques can be used in FPGAs, but I'll avoid it where possible, this is the message I was trying to give the OP (who I think is a beginner). NialArticle: 144353
Hi,
I tried to synthesize a small example using xst 11.2 but the synthesis
takes more than 20 GB of memory and never completes,
So I have to kill the tool.
Please find the code Below
library ieee;
use ieee.std_logic_1164.all;
entity tmp is
port (
i1 : in std_ulogic;
o1 : out std_ulogic_vector(31 downto 0)
);
end tmp;
architecture rtl of tmp is
signal sig1 : std_ulogic_vector(31 downto 0);
signal sig2 : std_ulogic_vector(15 downto 0);
begin
tmp_process: process (sig2, sig1)
variable var1 : std_ulogic_vector(15 downto 0);
variable var2 : std_ulogic_vector(1 downto 0);
variable var3 : std_ulogic_vector(3 downto 0);
begin
var3 := (others => '0');
for i in 15 downto 0 loop
var2 := sig1((i*2+1) downto (i*2));
case var2 is
when "00" =>
var3(0) := var3(0) or var1(i);
when "01" =>
var3(1) := var3(1) or var1(i);
when "10" =>
var3(2) := var3(2) or var1(i);
when "11" =>
var3(3) := var3(3) or var1(i);
when others =>
null;
end case;
end loop;
end process;
end rtl ;
Your help is most appreciated.
regards,
subagha
---------------------------------------
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Article: 144354On Nov 30, 3:36=A0pm, "subagha" <suba...@gmail.com> wrote: > Hi, > > =A0I tried to synthesize a small example using xst 11.2 but the synthesis > takes more than 20 GB of memory and never completes, > > So I have to kill the tool. > > Please find the code Below > > library ieee; > =A0 =A0 use ieee.std_logic_1164.all; > > entity tmp is > =A0 =A0 port ( > =A0 =A0 =A0 =A0 i1 : in =A0 =A0 std_ulogic; > =A0 =A0 =A0 =A0 o1 : out =A0 =A0std_ulogic_vector(31 downto 0) > =A0 =A0 ); > end tmp; > > architecture rtl of tmp is > =A0 signal sig1 =A0 =A0 =A0 =A0 =A0 =A0: std_ulogic_vector(31 downto =A00= ); > =A0 signal sig2 =A0 =A0: std_ulogic_vector(15 downto =A00); > > begin > > =A0 =A0 =A0tmp_process: process (sig2, sig1) > > =A0 =A0 =A0 =A0variable var1 : std_ulogic_vector(15 downto 0); > =A0 =A0 =A0 =A0variable var2 =A0 : std_ulogic_vector(1 downto 0); > =A0 =A0 =A0 =A0variable var3 =A0 =A0 : std_ulogic_vector(3 downto 0); > > =A0 =A0 =A0begin > =A0 =A0 =A0 =A0 =A0 var3 =A0 =A0 =A0 =A0:=3D (others =3D> '0'); > =A0 =A0 =A0 =A0 =A0 for i in 15 downto 0 loop > =A0 =A0 =A0 =A0 =A0 =A0 =A0 var2 =A0 =A0 =A0:=3D sig1((i*2+1) downto (i*2= )); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 case var2 is > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when "00" =3D> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 var3(0) =A0:=3D var3(0) or va= r1(i); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when "01" =3D> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 var3(1) =A0:=3D var3(1) or va= r1(i); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when "10" =3D> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 var3(2) =A0:=3D var3(2) or va= r1(i); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when "11" =3D> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 var3(3) =A0:=3D var3(3) or va= r1(i); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when others =3D> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 null; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 end case; > =A0 =A0 =A0 =A0 =A0end loop; > =A0 =A0 =A0end process; > > end rtl ; Whatever is this supposed to do? The input is never used, the output is never driven, the signals are never assigned to... if I were a synthesis tool I would check the system clock to make sure it wasn't April 1st.Article: 144355
On Nov 30, 5:55=A0pm, ASPENLOGIC <use...@aspenlogic.com> wrote: > I've started a new ASIC Prototyping group on LinkedIn. To join, search > for "ASIC Prototyping" in the groups directory. 1 reason todo so is: <insert here why> ? AnttiArticle: 144356
Simon wrote:
> On Nov 20, 1:31 pm, Simon <goo...@gornall.net> wrote:
>> I'm trying to implement an SDRAM controller for the Altera EP2C8 on a
>> TS-7300 board (fromhttp://www.embeddedarm.com), and I found a
>> document from Altera (http://www.pldworld.net/_altera/html/_excalibur/
>> nios-sdram-tuning/SDRAM_PLL_Tuning.pdf) which looks helpful in
>> calculating how the PLL ought to be set up.
>>
>> The problem I'm facing is that the datasheet (http://www.altera.com/
>> literature/hb/cyc2/cyc2_cii5v1_01.pdf) for the EP2C8 doesn't seem to
>> have the information needed by the calculations in the tuning guide.
>> The tuning guide is referencing a table ("table 4:36. EP1C20 Column
>> pin global clock external i/o timing parameters) that shows t_su,
>> s_inh, and t_outco for a Cyclone 1, and the closest table I can find
>> in the datasheet for the cyclone 2 has t_cin, t_cout, t_pllcin, and
>> t_pllcout (table 5-23 : EP2C8/A Column pins global clock timing
>> parameters). These don't appear to be the same thing :)
>>
>> Can anyone point me in the right direction ? Much appreciated if you
>> do :)
>>
>> Cheers,
>> Simon
>
> No-one got any hints ?
Haven't done it with a Cyclone, but with a Stratix, you get these numbers
from the timing output after a build. Make your calculations and substitute
into the PLL and build again.
Mark
Article: 144357It depends on what your design's goals and usage are. Is it a demonstration project, or a for-production design? Is the design likely to be upgraded with new features, or ported to a different (smaller/slower/cheaper) FPGA in the future? Is it battery powered, or does it have to operate at high temperatures? Depending on the answers to these questions, and others I'm sure, your design's "performance" may need more or less design margin on timing. Resource utilization and/or power dissipation could be an indication of relative "performance". Beyond "satisfying timing requirements," system throughput and latency may also be indicators of design performance, depending on the nature of the system surrounding the FPGA. There are other potential measures of performance that have nothing to do with the implemented design in the FPGA, but with the maintainability of the code and the quality of the design documentation and testbenches (especially if it will be maintained/ modified in the future). Do not confuse "design performance" with "product performance". Depending on what the design is to be used for, there may be many performance indicators beyond just meeting timing. AndyArticle: 144358
hi,all
i have created an user ip connecting opb bus based microblaze.when i
watch the data from many ports ,there is a strange Phenomenon. i can obtain
only one right data from the ports.but,the following samples are in high
state from all the ports.i can not solve the problem all the time. who can
help me?
---------------------------------------
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Article: 144359Hi, Sorry for the confusion. The code along with the post is stripped form a big design. XST 11.2 does not synthesize my design so i stripped my code to the point where it produces the problem and it is produced in the post. So the input output and clocks none are driven. Can anyone please tell me a way to synthesize the piece of code. regards >On Nov 30, 3:36=A0pm, "subagha" <suba...@gmail.com> wrote: >> Hi, >> >> =A0I tried to synthesize a small example using xst 11.2 but the synthesis >> takes more than 20 GB of memory and never completes, >> >> So I have to kill the tool. >> >> Please find the code Below >> >> library ieee; >> =A0 =A0 use ieee.std_logic_1164.all; >> >> entity tmp is >> =A0 =A0 port ( >> =A0 =A0 =A0 =A0 i1 : in =A0 =A0 std_ulogic; >> =A0 =A0 =A0 =A0 o1 : out =A0 =A0std_ulogic_vector(31 downto 0) >> =A0 =A0 ); >> end tmp; >> >> architecture rtl of tmp is >> =A0 signal sig1 =A0 =A0 =A0 =A0 =A0 =A0: std_ulogic_vector(31 downto =A00= >); >> =A0 signal sig2 =A0 =A0: std_ulogic_vector(15 downto =A00); >> >> begin >> >> =A0 =A0 =A0tmp_process: process (sig2, sig1) >> >> =A0 =A0 =A0 =A0variable var1 : std_ulogic_vector(15 downto 0); >> =A0 =A0 =A0 =A0variable var2 =A0 : std_ulogic_vector(1 downto 0); >> =A0 =A0 =A0 =A0variable var3 =A0 =A0 : std_ulogic_vector(3 downto 0); >> >> =A0 =A0 =A0begin >> =A0 =A0 =A0 =A0 =A0 var3 =A0 =A0 =A0 =A0:=3D (others =3D> '0'); >> =A0 =A0 =A0 =A0 =A0 for i in 15 downto 0 loop >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 var2 =A0 =A0 =A0:=3D sig1((i*2+1) downto (i*2= >)); >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 case var2 is >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when "00" =3D> >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 var3(0) =A0:=3D var3(0) or va= >r1(i); >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when "01" =3D> >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 var3(1) =A0:=3D var3(1) or va= >r1(i); >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when "10" =3D> >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 var3(2) =A0:=3D var3(2) or va= >r1(i); >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when "11" =3D> >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 var3(3) =A0:=3D var3(3) or va= >r1(i); >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when others =3D> >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 null; >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 end case; >> =A0 =A0 =A0 =A0 =A0end loop; >> =A0 =A0 =A0end process; >> >> end rtl ; > >Whatever is this supposed to do? The input is never used, the output >is never driven, the signals are never assigned to... if I were a >synthesis tool I would check the system clock to make sure it wasn't >April 1st. > --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144360
On Nov 30, 11:43=A0pm, "subagha" <suba...@gmail.com> wrote: > Hi, > =A0 =A0Sorry for the confusion. The code along with the post is stripped = form a > big design. XST 11.2 does not synthesize my design so i stripped my code = to > the point where it produces the problem and it is produced in the post. > So the input output and clocks none are driven. > > Can anyone please tell me a way to synthesize the piece of code. > Ben already did tell you how to synthesize your code. - You have to actually *use* the inputs (i.e. they must be on the right hand side of an expression or used to evaluate some condition. - Assign something to the outputs that is a function of the inputs (either directly or indirectly). As posted, entity tmp reduces to 0 logic, 0 pins and apparently XST has a problem with such nonsense. Whether this is part of some bigger design or not doesn't matter, this entity will always completely disappear during synthesis But a better tactic would be... - Simulate your design and get it to actually work in simulation. If you did, you find that the output of entity tmp would always be 'U'. - After you get the simulation working properly, THEN try to synthesize it Kevin JenningsArticle: 144361
Hi, Sorry for the confusion. The code along with the post is stripped form a big design. XST 11.2 does not synthesize my design so i stripped my code to the point where it produces the problem and it is produced in the post. So the input output and clocks none are driven. Can anyone please tell me a way to synthesize the piece of code. regards >On Nov 30, 3:36=A0pm, "subagha" <suba...@gmail.com> wrote: >> Hi, >> >> =A0I tried to synthesize a small example using xst 11.2 but the synthesis >> takes more than 20 GB of memory and never completes, >> >> So I have to kill the tool. >> >> Please find the code Below >> >> library ieee; >> =A0 =A0 use ieee.std_logic_1164.all; >> >> entity tmp is >> =A0 =A0 port ( >> =A0 =A0 =A0 =A0 i1 : in =A0 =A0 std_ulogic; >> =A0 =A0 =A0 =A0 o1 : out =A0 =A0std_ulogic_vector(31 downto 0) >> =A0 =A0 ); >> end tmp; >> >> architecture rtl of tmp is >> =A0 signal sig1 =A0 =A0 =A0 =A0 =A0 =A0: std_ulogic_vector(31 downto =A00= >); >> =A0 signal sig2 =A0 =A0: std_ulogic_vector(15 downto =A00); >> >> begin >> >> =A0 =A0 =A0tmp_process: process (sig2, sig1) >> >> =A0 =A0 =A0 =A0variable var1 : std_ulogic_vector(15 downto 0); >> =A0 =A0 =A0 =A0variable var2 =A0 : std_ulogic_vector(1 downto 0); >> =A0 =A0 =A0 =A0variable var3 =A0 =A0 : std_ulogic_vector(3 downto 0); >> >> =A0 =A0 =A0begin >> =A0 =A0 =A0 =A0 =A0 var3 =A0 =A0 =A0 =A0:=3D (others =3D> '0'); >> =A0 =A0 =A0 =A0 =A0 for i in 15 downto 0 loop >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 var2 =A0 =A0 =A0:=3D sig1((i*2+1) downto (i*2= >)); >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 case var2 is >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when "00" =3D> >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 var3(0) =A0:=3D var3(0) or va= >r1(i); >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when "01" =3D> >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 var3(1) =A0:=3D var3(1) or va= >r1(i); >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when "10" =3D> >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 var3(2) =A0:=3D var3(2) or va= >r1(i); >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when "11" =3D> >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 var3(3) =A0:=3D var3(3) or va= >r1(i); >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 when others =3D> >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 null; >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 end case; >> =A0 =A0 =A0 =A0 =A0end loop; >> =A0 =A0 =A0end process; >> >> end rtl ; > >Whatever is this supposed to do? The input is never used, the output >is never driven, the signals are never assigned to... if I were a >synthesis tool I would check the system clock to make sure it wasn't >April 1st. > --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144362
On 1 Dez., 06:23, "subagha" <suba...@gmail.com> wrote: > Hi, > =A0 =A0Sorry for the confusion. The code along with the post is stripped = form a > big design. XST 11.2 does not synthesize my design so i stripped my code = to > the point where it produces the problem and it is produced in the post. > So the input output and clocks none are driven. > > Can anyone please tell me a way to synthesize the piece of code. > > regards > H subagha, you either stripped the code to much, to be meaningful, or it's just as weird as it looks. Have you tried to synthesize it using pen and paper? The first stage in the loop is quite simple but even the second and third stage become nasty stuff. Since you are using variables, which are assigned immediately, there's not even a chance to build latches for the synthesis tool. Depending on the input value it may be possibe that a var3-bit of the first iteration has to be used as input for the last iteration. So in hardware this code will grow like a combinational fungus over your chip. Some clocking might help here, so var3 can be stored over the iterations and you get a latency of 16 clocks. Also you have to restrict the new inputs (sig1) to be updated only after latency. (Pipelining would increase the hardware needs in a nasty way.) Others were complaining about not using any I/Os. This is correct, but when you say XST takes this code and still needs endless time to synthesize it makes me wonder. A clever synthesis tool would look at the entity, search for the I/Os, find everything unused and just quit with some messages. In ISE-PN (since 10.1i) we see, that entities are not shown in the source tree anymore, just architectures. Can it be possible, that XST just drops on this architectures and tries to synthesize some logic BEFORE it checks if this hardware is connected to anything at all? For ordinary code this might be ok and give some runtime advantages (hierarchies and black boxes may be an issue too), but for such crappy code it's doomed to fail. So, maybe you should reveal the algorithm you want to implement with this code, and then maybe someone can tell you how to do it with better success. Have a nice synthesis EilertArticle: 144363
On Dec 1, 4:43=A0am, "subagha" <suba...@gmail.com> wrote:
> Can anyone please tell me a way to synthesize the piece of code.
Kevin is right; as it stands this entity should synthesize to nothing
at all. (Although that's not really an excuse for XST to crash and
burn, I'll freely admit.)
However, I did a few mods to bring the inputs and outputs of the
process up to top-level ports, and ran the resulting well-formed code
through XST. It definitely seems to hit some sort of memory leak when
synthesizing this process.
To fix it, I removed the case statement and replaced it with an
equivalent if-else statement:
if var2 =3D "00" then
var3(0) :=3D var3(0) or var1(i);
elsif var2 =3D "01" then
var3(1) :=3D var3(1) or var1(i);
elsif var2 =3D "10" then
var3(2) :=3D var3(2) or var1(i);
elsif var2 =3D "11" then
var3(3) :=3D var3(3) or var1(i);
end if;
Then it goes through fine. It looks like there's a bug handling case
statements within loops. At first I thought it was probably because
the controlling variable was of std_logic-related type, meaning that
very many possible values fall into the "default" case. But I changed
var2 to be of type "integer range 0 to 3" and added code to convert
the bit-slice to integer, and it still failed badly in the same way.
So it must be more fundamental.
I'm going to file a CR on this right now.
HTH,
-Ben-
Article: 144364
Currently I am studying the "Circuit Design with VHDL" by Volnei A.
Pedroni. On page 207 the run a simulation but do not provide the test
bench. I would like to run the same simulation but I am not familiar with
how to write a testbench. If possible please provide a testbench to mimic
the simulation shown on page 207. If you are unfamiliar with this book or
the simulation run, I would also appreciate ANY KIND of testbench which
could simulate it's funcionality. Also if there are any errors with the
code, please let me know! Your help is much appreciated! thank you!
Here is the code we are trying to implement:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vending_machine is
Port ( clk, rst : IN STD_LOGIC;
nickel_in, dime_in, quarter_in : IN BOOLEAN;
candy_out, nickel_out, dime_out, quarter_out: OUT STD_LOGIC);
end vending_machine;
architecture fsm of vending_machine IS
TYPE state IS (st0, st5, st10, st15, st20, st25, st30, st35, st40, st45);
SIGNAL present_state, next_state: STATE;
begin
PROCESS(rst, clk)
BEGIN
IF(rst='1') THEN
present_state <=st0;
ELSIF(clk' EVENT AND clk ='1') THEN
present_state <= next_state;
END IF;
END PROCESS;
PROCESS(present_state, nickel_in, dime_in, quarter_in)
BEGIN
CASE present_state IS
WHEN st0 =>
candy_out <= '0';
nickel_out <='0';
dime_out <= '0';
IF (nickel_in) THEN next_state <= st5;
ELSIF (dime_in) THEN next_state <= st10;
ELSIF (quarter_in) THEN next_state <= st25;
ELSE next_state <=st0;
END IF;
WHEN st5 =>
candy_out <= '0';
nickel_out <='0';
dime_out <= '0';
IF (nickel_in) THEN next_state <= st10;
ELSIF (dime_in) THEN next_state <= st15;
ELSIF (quarter_in) THEN next_state <= st30;
ELSE next_state <=st5;
END IF;
WHEN st10 =>
candy_out <= '0';
nickel_out <='0';
dime_out <= '0';
IF (nickel_in) THEN next_state <= st15;
ELSIF (dime_in) THEN next_state <= st20;
ELSIF (quarter_in) THEN next_state <= st35;
ELSE next_state <=st10;
END IF;
WHEN st15 =>
candy_out <= '0';
nickel_out <='0';
dime_out <= '0';
IF (nickel_in) THEN next_state <= st20;
ELSIF (dime_in) THEN next_state <= st25;
ELSIF (quarter_in) THEN next_state <= st40;
ELSE next_state <=st15;
END IF;
WHEN st20 =>
candy_out <= '0';
nickel_out <='0';
dime_out <= '0';
IF (nickel_in) THEN next_state <= st25;
ELSIF (dime_in) THEN next_state <= st30;
ELSIF (quarter_in) THEN next_state <= st45;
ELSE next_state <=st20;
END IF;
WHEN st25 =>
candy_out <= '1';
nickel_out <='0';
dime_out <= '0';
next_state <= st0;
WHEN st30 =>
candy_out <= '1';
nickel_out <='1';
dime_out <= '0';
next_state <= st0;
WHEN st35 =>
candy_out <= '1';
nickel_out <='0';
dime_out <= '1';
next_state <= st35;
WHEN st45 =>
candy_out <= '0';
nickel_out <='0';
dime_out <= '1';
next_state <= st35;
END CASE;
END PROCESS;
END fsm;
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Article: 144365On Nov 23, 10:17=A0am, "jack.gassett" <jack.gass...@gadgetfactory.net> wrote: > Hello, > > We are working on a project to create a low cost Open Source Logic > Analyzer. We are making great progress but would greatly appreciate > any input from members of the comp.arch.fpga group. > > The design is based on the following resources: > -Sump Logic Analyzer VHDL design. (http://www.sump.org/projects/ > analyzer/) > -Butterfly Light Hardware implementation. The goal is to streamline > the Butterfly Light hardware to reduce costs. (http://www.gadgetfactory.n= et/gf/project/lax/) > > If you have some time please take a look and give us you thoughts > about the project. The design pages are:http://www.gadgetfactory.net/gf/p= roject/butterflylogic/ > > All discussions about the project are located at:http://whereisian.com/fo= rum/index.php?board=3D23.0 > > Thank you, > Jack. Looks pretty nice. Simple little system is usable for many types of designs and the price is fairly reasonable (cheaper dev-boards are available from mfgs/distros with more features however). It's pretty bare-bones though: no signal conditioning, no cables / connectors. Very DIY. I'd say that for cost reduction and ergonomics you'd want to do the following at a minimum: * combine the USB & power conditioning with the FPGA onto one small board. * Eliminate unused I/O * Add input signal conditioning to prevent damage to FPGA from external sources * Add some sort of standard connectors for multi-bit cables. * Consider a board profile that would fit in a standard enclosure. Newer Spartan 3A parts in the VQ100 package are now available from the usual suspects and are a few $$ cheaper than the S3E you're currently using. I'm guessing you could get the whole thing in for under $60 BOM. At that price though I'm wondering how well it competes with low- end USB logic analyzers that are already out there. EricArticle: 144366
Hi, On a project requiring intensive processing based on VXS boards we are looking at ways of increasing the processing power by using a mezzanine board hosting a large FPGA with fast access memory resources. The mezzanine would preferably be an XMC type and PMC as a last resort. We are looking for an Altera based mezzanine as we already have other developments based on Altera FPGAs. Up to now, we could not find a mezzanine based on Altera parts except for one at GE fanuc which is not enough for our need and does not seem to be the way for new designs. Would any one know of an Altera based mezzanine with a Stratix II GX or Stratix IV GX ? Best regards, JFArticle: 144367
"Philip Pemberton" <usenet09@philpem.me.uk> wrote in message
news:00428082$0$2310$c3e8da3@news.astraweb.com...
> Hi guys,
> I'm trying to generate a clock signal that can be switched between
> 16MHz, 8MHz and 4MHz, and have a 50% duty cycle (for a data separator/
> slicer). Just to make this difficult, I only have a 40MHz master clock to
> work from... which only has an even integer factor for 4MHz (divide-by-
> ten). Divide-by-five gets 8MHz, but doesn't give a 50:50 ratio. 16MHz
> isn't even possible (nearest I can get is 20MHz with a divide-by-two).
>
> This is on an Altera Cyclone II 2C20, FBGA484 package, on a Terasic DE1
> (actually Altera Cyclone II Starter Board, but the Terasic board is
> essentially identical) development board. Software is Quartus 9.0.
>
> Originally, this seemed like a simple problem to solve -- create a PLL
> to generate a new set of clocks that were phase-locked to the original
> 40MHz master clock. Problem is, while I can get the PLL to generate a
> 16MHz clock, it won't go any lower -- 8MHz and 4MHz produce an alert to
> the effect of "division ratio not possible."
>
> So I figured I'd go about this a different way -- generate a 16MHz
> clock with the PLL, then divide it down to 8MHz and 4MHz with a pair of
> DQ flip-flops wired to toggle (or a binary counter, whatever worked).
> This worked fine when I tied the outputs of the clock divider straight to
> the clock input on the data separator.
>
> This is what I have now:
>
> // Instantiate a PLL to convert from 40MHz to 32MHz
> wire CLK_PLL16MHZ;
> DatasepClockGen dscg(CLK40MHZ, CLK_PLL16MHZ);
>
> // Divide down the 16MHz reference to get 8MHz and 4MHz
> reg CLK_PLL8MHZ;
> always @(posedge CLK_PLL16MHZ) CLK_PLL8MHZ = ~CLK_PLL8MHZ;
> reg CLK_PLL4MHZ;
> always @(posedge CLK_PLL8MHZ) CLK_PLL4MHZ = ~CLK_PLL4MHZ;
>
> wire DATASEP_MASTER_CLK;
> assign DATASEP_MASTER_CLK = CLK_PLL4MHZ;
>
> // Data separator
> wire SHAPED_DATA, DWIN;
> DataSeparator _datasep(DATASEP_MASTER_CLK, FD_RDDATA_IN,
> SHAPED_DATA, DWIN);
>
> // For debugging -- REMOVEME!
> assign debug[3:0] = { DATASEP_MASTER_CLK, FD_RDDATA_IN,
> SHAPED_DATA, DWIN };
>
> debug[3:0] is a set of output pins, CLK40MHZ is the master clock,
> CLK_PLL16MHZ is the output from the PLL. I can post the data separator
> logic as well, but it's basically a Verilog implementation of the circuit
> shown here:
> <http://www.analog-innovations.com/SED/FloppyDataExtractor.pdf>
>
> And this works fine on its own. I'm aware that there are issues with
> glitches if I just use a straight multiplexer to switch between clock
> sources, so I'm using the parameterised "clock_mux" module from the
> Quartus manuals
> (<http://www.altera.com/literature/hb/qts/qts_qii51007.pdf>, chapter 6,
> page 48-50). I added it to my code like this (replacing the
> DATASEP_MASTER_CLK assignments in the code above):
>
> // Mux the clock
> wire DATASEP_MASTER_CLK;
>
> // Clock multiplexer
> wire [3:0] datasep_clock_selects = {
> (ACQCON_MFM_CLKSEL == 2'b00),
> (ACQCON_MFM_CLKSEL == 2'b01),
> (ACQCON_MFM_CLKSEL == 2'b10),
> (ACQCON_MFM_CLKSEL == 2'b11) };
> wire [3:0] datasep_clocks = {
> (CLK_PLL16MHZ), // 3.5in ED (1Mbps)
> (CLK_PLL8MHZ), // 3.5in HD (500kbps)
> (CLK_PLL4MHZ), // 3.5in DD (250kbps)
> (CLK_PLL4MHZ) }; // Dummy entry for SEL=0b11
>
> clock_mux #(.num_clocks(4)) _datasep_clock_mux(
> datasep_clocks,
> datasep_clock_selects,
> DATASEP_MASTER_CLK
> );
>
> This results in a ton of timing violation warnings from the timing
> analyser, the most notable being these two:
>
> Warning: Can't achieve minimum setup and hold requirement
> DatasepClockGen:dscg|altpll:altpll_component|_clk0 along 9 path(s). See
> Report window for details.
>
> Critical Warning: Timing requirements for slow timing model timing
> analysis were not met. See Report window for details.
>
> Obviously the setup/hold violation is not a "Good Thing (tm)" and it
> needs resolving ASAP (assuming the design works at all as it is). The
> question is, how should I go about doing this?
>
> I can replace the clock multiplexer with a straight AND/OR multiplexer,
> which seems to resolve the timing issue (or it did last time I tried it),
> but this risks causing glitching issues (although the Datasep should
> reset within about 64 clock cycles).
>
> Can anyone suggest a possible solution? This is driving me nuts...
> probably because the errors from Quartus are about as clear as a pool of
> mud, and it seems the Quartus "help" file is only serving to make the mud
> thicker...
>
> Thanks,
> --
> Phil.
> usenet09@philpem.me.uk
> http://www.philpem.me.uk/
> If mail bounces, replace "09" with the last two digits of the current
> year.
Are you sure that the circuit described in
<http://www.analog-innovations.com/SED/FloppyDataExtractor.pdf>
works as you hope?
I've run it through a couple of simulators including one that simulates
the old "family logic" and find that it breaks down and doesn't maintain
lock, or even approach a steady timing relationship with the input signal.
Of course, it does work if the input timing and driver clock are both in
sync, but if the MFM input is 10% out of phase, the thing seems never to
acquire. Further, if it's 5% fast or slow, relative the center frequency,
then it loses or never achieves lock.
Uli
Article: 144368Vaughn, where are you? Couple of updates since last time: 1. Our kit is indeed based on engineering sample. 2. QuartusII 9.1 appears to have exactly the same problems as 9.0 SP2 that we used before. [Whining on] BTW, do you know that PCIe core v. 9.1 is not 100% source code compatible with v.9.0? I though that the whole point of _minor_ version number that it's supposed to be backward compatible :( Next time you break backward compatibility, pleas increment the major version number then, at least, we would know that the trouble is coming. Plus, "soft" IP is not 100% source code compatible with the hard IP and the differences are more than just test inputs/output. It's pretty annoying. [Whining off] Regards, MichaelArticle: 144369
Thanks a lot the change fixed my problem in the original design regards --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144370
I have two CPUs (master and slave) and a Spartan II FPGA.
CPUs communicate using FPGA.
Inside the FPGA there is a READY flag which:
- master can reset to '0';
- slave can set to '1' or to the state of another flag;
- also, hardware RESET can reset it to '0', but that never happens;
So, READY should be implemented as a FDRSE.
At the time of first writing of VHDL code, I didn't think
*how* ISE will implement the READY flag, and I wrote this:
if rising_edge(CLK) then
if WR3/=WR2 or RESET='1' then READY <= '0'; -- master/reset
elsif ACTION='1' then -- slave
if ACTIONCODE="00" then READY <= '1';
elsif ACTIONCODE="01" then READY <= ACTIONBIT;
end if;
end if;
end if;
ISE implemented a FDRE and routed Q output
back to D input (not directly, of course).
In real world that didn't work.
I wrote a test prog that has failed after several seconds.
READY was set to '1' when it should have stayed '0'.
Later, I re-wrote it to look more like the FDRSE template:
READY_RES <= '1' when (WR3/=WR2 or RESET='1') else '0';
READY_SET <= '1' when (ACTION='1' and ACTIONCODE="00") else '0';
READY_CE <= '1' when (ACTION='1' and ACTIONCODE="01") else '0';
if rising_edge(CLK) then
if READY_RES='1' then READY <= '0';
elsif READY_SET='1' then READY <= '1';
elsif READY_CE='1' then READY <= ACTIONBIT;
end if;
end if;
And that worked. ISE has implemented a FDRSE and
that test prog never failed.
All signals are synchro to CLK, and the design is constrained.
Why did the first example fail?
BTW, just to be safe, I've later instantiated the FDRSE.
Master has its own clock and to cross clock domains, I do this:
if rising_edge(MASTERCLK) then
WR0 <= not WR0;
end if;
if rising_edge(CLK) then
WR3 <= WR2; WR2 <= WR1; WR1 <= WR0; -- right to left
end if;
CLK is 40 MHz.
Article: 144371nola94 pisze: > hi all, > thanx for your reply... > i finally figure out how to save the data in txt files..I used sjinn linux > application and xil_print to my c program in microblaze.. > however,i am not able to save all samples that adc outputs..my fsm make the > onboard adc to give 1 sample every 700ns... > Is microblaze fast enough to capture these data? > Do i need some external ram to save first data and transfer them > afterwards? > thanx in advance, > i really appreciate it.. > > > --------------------------------------- > This message was sent using the comp.arch.fpga web interface on > http://www.FPGARelated.com I don't the previous messages in your thread. Without your current hardware configuration it's hard to advise anything. If You want to use microblaze I presume you want to store adc output in the hardware. then sure you need additional storage ram. another thing is to send data via usb to pc and store it somewhere either in memory or hard disk regards robertArticle: 144372
How are you synchronizing action, actioncode and actionbit? AndyArticle: 144373
"Ben Jones" <benjjuk@gmail.com> wrote > It definitely seems to hit some sort of memory leak when synthesizing this > process. I have submitted a webcase with a design that fails synthesis on an XP machine reporting lack of memory: Portability:3 - This Xilinx application has run out of memory or has encountered a memory conflict. Current memory usage is 2082080 kb. According to the tech support person working on the case the same design synthesizes fine on a Linux machine and requires only 510 MB of memory. /MikhailArticle: 144374
Hi, After all the clock generation stories, now comes the time of time counting. So I want to implement a high-frequency (<=100MHz ?) counter/timer that gets incremented by an auxiliary input, and the problem comes from the clock domain crossing : the low-frequency "acquire" signal must latch the counter in another register but problems are likely to occur there. I have figured a "latch enable" logic that is synchronised with the incoming signal, plus a simple R/S toggle for handshaking but I presume that there are far better solutions. Can anybody hint me ? yg -- http://ygdes.com / http://yasep.org
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