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Petter Gustad <newsmailcomp6@gustad.com> wrote: > John Adair <g1@enterpoint.co.uk> writes: > > A number of parallel port based cables, like our Prog2 cable, will > > work for Chipscope/Impact tools. USB solutions are not readily > Is the ChipScope/Impact software interface documented? Is there a way > I can write a plug-in for my programmer so that it will work with my > own programmer? Petter Are you kidding ? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 144476
> I'm starting to wonder about how the PHY is reset. I don't have any > physical access to that signal, so I cannot view it on a scope. But > the PHY data sheet states it must be at least 10 ms long, and remain > active for at least 10 clock cycles. Could that be different? I believe I measured this at some point in the past and found that it was much much shorter and did not meet the spec of my PHY. However, the PHY I am using doesn't seem to care... On the other hand I remember having a problem similar to yours when TRST pin of the PHY wasn't grounded. /MikhailArticle: 144477
Andy Peters wrote: > On Dec 3, 10:36 pm, Antti <antti.luk...@googlemail.com> wrote: >> On Dec 4, 2:09 am, Andy Peters <goo...@latke.net> wrote: >> >>> On Dec 3, 3:01 pm, Vikram <vkr...@gmail.com> wrote: >>>> Announcing a Seminar on A New Approach - An FPGA and PCB System >>>> Development Platform, Santa Clara, CA, USA (By Altium) - Dec'10 >>>> #2 FPGA Design & Instant Prototyping >>>> Learn how to design complex FPGA's with an embedded processor utlizing >>>> block based IP and quickly debug your design in a NanoBoard with >>>> virtual instrumentation. >>> FPGA design using a PCB layout tool is a recipe for disaster. >>> -a >> Altium Designer is NOT a PCB layotool. > > Oh, then how is it possible that I'm doing a board-level schematic in > it right now, which will then be handed off to my layout guy so he can > do that task, also in AD? > > -a Perhaps Antti meant to say "Altium Designer is not *just* a PCB layout tool". It is also a tool for FPGA design (though I haven't tried that aspect of it myself). Whether or not you think it is a /good/ for FPGA design is another matter, of course.Article: 144478
On Dec 9, 7:40=A0am, "kendor" <jonas.re...@bfh.ch> wrote: > >I hope your comment on the declaration of WD is not what you really > >wanted... > > >Also, en=3D'0' disables the cnt increment, but not the prescaler (temp), > >which will lead to problems if en is disabled at the wrong time or for > >long enough. > > >Depending on how much latency you can tolerate (other posts regarding > >register retiming/rebalancing), you may want to register the output of > >the prescaler comparison, so that it's logic path does not add to the > >counter path. > > >Andy > > thank you all for your follow ups! > > In the comment I certainly mean prescaler - not divider ;) > > I am using timespecs for high and low time - ISE11 manages to do its job > (however I have to increase its effort, which leads to quite some > processing time (30'+)) > I believe to add a pipeline would be a good idea. I'm processing 4*1024 > multiplexed signals and for each signal I have 10 clock cycles for my > algorithm to pass (I always switch between single incoming signals and th= en > to the processing and wait again for the next time the same signal is > selected... around 100us). Since I use the countervalue right from the > beginning I would need to increase the countertime at the time I switch t= o > the new signal. At the moment the data path needs 8 out of those 10 clock > cycles. So there's not a lot of margin to add in another pipeline stage > without having to add those in the whole algorithm (which works with > feedbacks and loops of different delays) - so I'd prefer to have the easy > way :) > > I didn't think of the "from : to style timing constraint" since I was not > wanting to add 42 of those. But I'll give this a try. > Registering the prescaler comparison sounds good to. > > Thanks! > > --------------------------------------- =A0 =A0 =A0 =A0 > This message was sent using the comp.arch.fpga web interface onhttp://www= .FPGARelated.com No need to add 42 constraints. You make a timing group out of the counter bits. Then you have one constraint from that group to itself using the clock multiplied by the prescaler count as the delay. One good approach to this is as mentioned to register the prescaler to create a single cycle pulse at the prescale rate and write the counter logic such that it only changes when that signal is active (the "clock enable"). Then you can create the timing group based on the clock enable signal and perhaps catch some multicycle paths you didn't think of. Regards, GaborArticle: 144479
On Dec 9, 1:26=A0pm, "MM" <mb...@yahoo.com> wrote: > > I'm starting to wonder about how the PHY is reset. =A0I don't have any > > physical access to that signal, so I cannot view it on a scope. =A0But > > the PHY data sheet states it must be at least 10 ms long, and remain > > active for at least 10 clock cycles. =A0Could that be different? > > I believe I measured this at some point in the past and found that it was > much much shorter and did not meet the spec of my PHY. However, the PHY I= am > using doesn't seem to care... On the other hand I remember having a probl= em > similar to yours when TRST pin of the PHY wasn't grounded. > > /Mikhail After my last email, I decided to control the reset line myself, and unfortunately, no improvement. Then, on a tip, I tried V3.00.a (instead of V3.00.b) of the hard_temac IP, and the reading improved dramatically. At first, I thought it was fixed, but looking real close, I noticed there were still a few bit errors. However, it occurred to me that, because I only need to modify two registers after reset, and they are both well-defined, I didn't actually need to read them. Once I get past the reset, I have no need for any interaction with the PHY's registers. So, I modified my code thusly, and lo and behold, it works! So at this point, I am happy... Thanks for the insight, Mikhail! -BobArticle: 144480
Ok My hunt is finally over. I've aquire the Altera LP6 Programming card. So I now have a fully running Altera PL-ASAP2 Master programmer. http://d.yimg.com/kq/groups/21609865/hr/1272931197/name/DSC00617.jpg http://d.yimg.com/kq/groups/21609865/hr/896433905/name/DSC00380.jpg I'm keeping a lookout for more adapters and I'm going to try and do a few school projects using this old unit. Fun Stuff!! Later Folks, -Gerry P.S. My Altera group I opened up. :) http://groups.yahoo.com/group/AlteraMAX7000/ >I've actually done this already with the DATA I/O Labsite programmer and it >erases the Altera chips perfectly. > >But I have almost all of the components for the Altera MPU setup and now I >just want to finish the deal since I've been searching for so long, I >refuse to just quit. Plus it would be interesting to learn and use the >unit. I've done so much research on it, I really am aching to try it out. > >Like I said, more of a collector at this point. :) > > >-Gerry > >># So anyone that knows where to get an Altera LP6 Logic Programming >>card >># please let me know. I'm willing to purchase it if the price is >>reasonable. >> >>An alternative could be to look for a Universal Pgmr on EBAY, that >>supports >>EPM7128's ? >> >>Or ask Altera for the Algorithm, hoping that someone still works there >>from >>this era ;) >> >>-jg >> >> > --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144481
On Dec 9, 6:39=C2=A0am, "moonlight721" <245298...@qq.com> wrote: > Hi > > Thanks for the HELP in advance > > I use the EDK9.1i to make my design=EF=BC=8Cthen I come to the EDK10.1 to= update > my > design=EF=BC=8C that works half year ago=EF=BC=8Cbut for now=EF=BC=8Cit d= oes not work=EF=BC=81The > error is =E2=80=9C No license for component <plb_uart16550_v1_00_c> found= =E2=80=9D > =EF=BC=8Csince I made my design in EDK9.1i thus I used the > =E2=80=9Cplb_uart16550_v1_00_c=E2=80=9D=EF=BC=8Cbut it works before=EF=BC= =8Cbut now it doesn't=EF=BC=8C > could you help me find out the problem=EF=BC=81 Is it the plb_uart16550_v= 1_00_c > cann't use in EDK10.1 anymore=EF=BC=9F Or the other reason=EF=BC=9F > my board is Virtex II pro 30 > > Thanks again Looking at the error message =E2=80=9CNo license for component <plb_uart16550_v1_00_c> found=E2=80=9D my guess is that you don't have a license for that component. No license, you can't use it. You could either design it out, or get a license for it. My suspicion is that you're using an illicit copy of ISE/EDK. Good luck with that. ALArticle: 144482
Andy Peters <google@latke.net> wrote:
>On Dec 3, 10:36=A0pm, Antti <antti.luk...@googlemail.com> wrote:
>> On Dec 4, 2:09=A0am, Andy Peters <goo...@latke.net> wrote:
>>
>> > On Dec 3, 3:01=A0pm, Vikram <vkr...@gmail.com> wrote:
>>
>> > > Announcing a Seminar on A New Approach - An FPGA and PCB System
>> > > Development Platform, Santa Clara, CA, USA (By Altium) - Dec'10
>>
>> > > #2 FPGA Design & Instant Prototyping
>> > > Learn how to design complex FPGA's with an embedded processor utlizin=
>g
>> > > block based IP and quickly debug your design in a NanoBoard with
>> > > virtual instrumentation.
>>
>> > FPGA design using a PCB layout tool is a recipe for disaster.
>>
>> > -a
>>
>> Altium Designer is NOT a PCB layotool.
>
>Oh, then how is it possible that I'm doing a board-level schematic in
>it right now, which will then be handed off to my layout guy so he can
>do that task, also in AD?
Antti should have typed: Altium Designer is NOT *JUST* a PCB layotool.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 144483Is there some report ISE can produce that will tell me the locations of all the blockrams it has placed? The post-PAR static timing happens to tell me that memory/r[1].ram is RAMB16_X1Y17, because that one is in a critical path, but grep through all of the generated files for memory/r[ and RAMB16_X doesn't turn up any of the others. I'd like to let PAR choose the locations of the blockrams, but use a Python script to extract the locations from a report and generate a BMM file. Thanks, EricArticle: 144484
Hi Everyone, If your looking for an older Altera LP6 Logic programming card, Which is part of the PL-ASAP2 Master programming Unit, then check out this link Below. the Company is called Artisan Scientific and they have some in stock. Hope this can help some of you. http://www.artisan-scientific.com/67142.htm -Gerry --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144485
>On Dec 9, 6:39=C2=A0am, "moonlight721" <245298...@qq.com> wrote: >> Hi >> >> Thanks for the HELP in advance >> >> I use the EDK9.1i to make my design=EF=BC=8Cthen I come to the EDK10.1 to= > update >> my >> design=EF=BC=8C that works half year ago=EF=BC=8Cbut for now=EF=BC=8Cit d= >oes not work=EF=BC=81The >> error is =E2=80=9C No license for component <plb_uart16550_v1_00_c> found= >=E2=80=9D >> =EF=BC=8Csince I made my design in EDK9.1i thus I used the >> =E2=80=9Cplb_uart16550_v1_00_c=E2=80=9D=EF=BC=8Cbut it works before=EF=BC= >=8Cbut now it doesn't=EF=BC=8C >> could you help me find out the problem=EF=BC=81 Is it the plb_uart16550_v= >1_00_c >> cann't use in EDK10.1 anymore=EF=BC=9F Or the other reason=EF=BC=9F >> my board is Virtex II pro 30 >> >> Thanks again > >Looking at the error message =E2=80=9CNo license for component ><plb_uart16550_v1_00_c> found=E2=80=9D my guess is that you don't have a >license for that component. > >No license, you can't use it. You could either design it out, or get >a license for it. > >My suspicion is that you're using an illicit copy of ISE/EDK. Good >luck with that. > >AL >Thanks for your answer！ I find out the answer， I change the system time to 2009.3.10，then I can use it。 When I setup the EDK&ISE on my computer it comes up with “the licence setup failed” I think this is the problem， could you help me how can I solve this problem？（But The ISE&EDK software is applied from the Xilinx company！） Thanks again！ --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144486
On Dec 9, 2:41=A0pm, Eric Smith <space...@gmail.com> wrote: > Is there some report ISE can produce that will tell me the locations > of all the blockrams it has placed? =A0The post-PAR static timing > happens to tell me that memory/r[1].ram is RAMB16_X1Y17, because that > one is in a critical path, but grep through all of the generated files > for memory/r[ and RAMB16_X doesn't turn up any of the others. > > I'd like to let PAR choose the locations of the blockrams, but use a > Python script to extract the locations from a report and generate a > BMM file. > > Thanks, > Eric The data2mem tool doesn't require you to know the physical location of a particular BlockRAM, it just needs to know what the name is like a UCF file does. http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/data2mem.pd= f Ed McGettigan -- Xilinx Inc.Article: 144487
Hello to all
i have master Clock 40 Mhz and from master Clock want Generate 1.2 K
hz Suare wave pulses at output
(1) what is problm with my Code
(2) how Counter works and how to take decide the Counter values like
these designs
(3) without Counter can we use Shift ??
my code is as below
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Clk_divider is
port(
resetn : in std_logic; -- Reset
MHZ_clock : in std_logic;
Out_clock : out std_logic
);
end Clk_divider;
architecture Clk_divider_arch of Clk_divider is
signal clk_count : std_logic_vector(16 downto 0) :=
"00000000000000000"; -- 16 Bit Counter
begin
Clock : process(resetn, MHZ_clock) -- 0.025uSec
begin
if(resetn = '0') then
Out_clock <= '0';
elsif(MHZ_clock'event and MHZ_clock = '1') then
if(clk_count <= "01000001000101000") then --- want Generate
Delay (40M Hz /1.2K Hz = 3320)
clk_count <= clk_count + '1';
out_clock <= '1';
elsif(( clk_count > "01000001000101000") AND (clk_count <
"10000010001010000"))then
-- 0 to 3333 ON and 3333 to 6666 OFF
out_clock <= '0';
clk_count <= clk_count + '1';
if(clk_count = "10000010001010000") then
clk_count <= "00000000000000000" ;
end if;
end if ;
end if ;
end process Clock ;
end Clk_divider_arch ;
Waiting fr replies ..
with Advance Thanks
Joshi
Article: 144488Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> writes: > Are you kidding ? Not actually. I was hoping that Xilinx had specified some of the interface to allow for 3rd party development of debugging interfaces. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 144489
Petter Gustad <newsmailcomp6@gustad.com> wrote: > Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> writes: > > Are you kidding ? > Not actually. I was hoping that Xilinx had specified some of the > interface to allow for 3rd party development of debugging interfaces. I always bug Xilinx on fairs to document the interfaces, but while technical people at the booth understand the point, they mostly tell that higher levels in the company will strongly oppose. So the release of the DLC10 cable clone on the SP601 board came as a surprise, but it doesn't help with using other cables for Chipscope communication. One way for resolution could be that the Xilinx devellopers see the ease of using the FT2232H and supply a cable with it. As the FT2232H needs no firmware, other FT2232H cables would work too. The other way would be to intercept the USB communication with the DLC9/10 (at least on Linux in the libusb level) and translate the DLC9/10 (already reversed engineered) primitives to primitives for the target cable. Another project on my list... Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 144490
On Dec 9, 9:09=A0pm, Bob <rsg.ucli...@gmail.com> wrote: > On Dec 9, 1:26=A0pm, "MM" <mb...@yahoo.com> wrote: > > > > I'm starting to wonder about how the PHY is reset. =A0I don't have an= y > > > physical access to that signal, so I cannot view it on a scope. =A0Bu= t > > > the PHY data sheet states it must be at least 10 ms long, and remain > > > active for at least 10 clock cycles. =A0Could that be different? > > > I believe I measured this at some point in the past and found that it w= as > > much much shorter and did not meet the spec of my PHY. However, the PHY= I am > > using doesn't seem to care... On the other hand I remember having a pro= blem > > similar to yours when TRST pin of the PHY wasn't grounded. > > > /Mikhail > > After my last email, I decided to control the reset line myself, and > unfortunately, no improvement. > > Then, on a tip, I tried V3.00.a (instead of V3.00.b) of the hard_temac > IP, and the reading improved dramatically. =A0At first, I thought it was > fixed, but looking real close, I noticed there were still a few bit > errors. > > However, it occurred to me that, because I only need to modify two > registers after reset, and they are both well-defined, I didn't > actually need to read them. =A0Once I get past the reset, I have no need > for any interaction with the PHY's registers. =A0So, I modified my code > thusly, and lo and behold, it works! =A0So at this point, I am happy... > > Thanks for the insight, Mikhail! > > -Bob Hi Bob, a long time ago I inserted a FF between MDIO input and the HARD_TEMAC clocked with falling MDC. The 88E1111 is very fast changing the MDIO after the rising MDC and I don't know when the HARD_TEMAC samples the signal. Have fun FlorianArticle: 144491
On Dec 10, 8:20=A0am, "Joshi & Joshi" <joship...@gmail.com> wrote:
> Hello to all
>
> i have master Clock 40 Mhz and from master Clock want Generate 1.2 K
> hz Suare wave pulses at output
>
> (1) what is problm with my Code
> (2) how Counter works and how to take decide the Counter values like
> these designs
> (3) without Counter can we use Shift ??
>
> my code is as below
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_arith.all;
> use ieee.std_logic_unsigned.all;
>
> entity Clk_divider is
> =A0 port(
> =A0 =A0 resetn =A0 =A0 =A0 =A0 =A0 : in =A0std_logic; -- Reset
> =A0 =A0 MHZ_clock =A0 =A0 =A0: in =A0std_logic;
> =A0 =A0 Out_clock =A0 =A0 =A0 =A0: out std_logic
>
> =A0 =A0);
> =A0 end Clk_divider;
>
> architecture Clk_divider_arch of Clk_divider is
>
> signal =A0clk_count =A0: std_logic_vector(16 downto 0) :=3D
> "00000000000000000"; -- 16 Bit Counter
>
> begin
>
> Clock : process(resetn, MHZ_clock) -- 0.025uSec
> begin
> =A0 if(resetn =3D '0') then
> =A0 =A0 Out_clock <=3D '0';
>
> =A0 elsif(MHZ_clock'event and MHZ_clock =3D '1') then
> =A0 =A0 =A0 =A0 if(clk_count <=3D "01000001000101000") then --- =A0 =A0wa=
nt Generate
> Delay (40M Hz /1.2K Hz =3D 3320)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 clk_count <=3D clk_count + '1';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 out_clock <=3D '1';
>
> =A0 =A0 =A0 =A0 elsif(( clk_count > "01000001000101000") AND (clk_count <
> "10000010001010000"))then
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- 0 to 3333 ON and 3333 to =
=A06666 OFF
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 out_clock <=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0clk_count <=3D clk_count + '1'=
;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if(clk_count =3D "10000010=
001010000") then
> =A0 =A0 =A0 =A0 clk_count <=3D "00000000000000000" ;
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 =A0 =A0 end if ;
>
> =A0 end if ;
> =A0 =A0 =A0 =A0 end process Clock ;
> end Clk_divider_arch ;
>
> Waiting fr =A0replies ..
>
> with Advance Thanks
> Joshi
Several things are wrong, which you would be able to find quite easily
by running a simulation and debugging the output.
(a) you haven't included clk_count in your reset clause, so asserting
the reset signal might not do what you expect - and the synthesis tool
might have to insert a latch in your design in order to match exactly
the behaviour you've specified.
(b) your condition in 'if(clk_count =3D "10000010001010000")' will never
be true, because it's nested inside another if statement that already
determined that clk_count is less than that number. So your counter
will reach it, and just stop. You probably meant to write "elsif"
here, and lose one of the 'end if's.
(c) I think your clock maths is out by a factor of two (and maybe a
rounding error). To create a 1.2KHz square wave from a 40MHz counter,
you need about 16666 cycles high and 16666 cycles low.
Also you're using asynchronous reset, which isn't really the best
solution in FPGAs, and four comparison operations where really you
could get away with one (so the circuit will probably be quite
inefficient). Why not just count N cycles then flip the output bit (x
<=3D not x)?
I didn't really understand your other two questions.
-Ben-
Article: 144492On Dec 8, 11:29=A0am, Gabor <ga...@alacron.com> wrote: > On Dec 7, 7:19=A0pm, Danyao <danyao.w...@gmail.com> wrote: > > > > > Hi, > > > I'm trying to implement a 10-bit rotating priority encoder. The two > > inputs are a 10-bit valid vector and a 4-bit index indicating which > > input has the highest priority. The output is a 10-bit 1-hot vector > > where the position of the 1 corresponds to the highest priority input > > that is also valid; > > > For example, for in_valid =3D 10'b0000111101: > > priority =3D 1 =3D> out_select =3D 10'b0000000100 > > priority =3D 6 =3D> out_select =3D 10'b0000000001 > > > My implementation consists of two rotate shifters and a simple > > priority encoder. The Verilog code is attached at the end of this > > message. > > > My questions are related to the resource utilization of this design. > > I'm using ISE 10.1.03 and targeting an XC2VP30-6ff896 device. When > > synthesized independently, I got the following LUT counts for the > > modules: > > > 10-bit rotate_shift_left: 45 4LUTs > > 10-bit rotate_shift_right: 43 4LUTs > > 10-bit 1-in-11 priority encoder: 12 4LUTs > > > First question: I expect the overall cost of the rotating priority > > encoder to be 45 + 43 + 12 =3D 100 4LUTs because it is a simple cascade > > of the three sub-modules. But in reality XST reports 106 4LUTs. I > > can't figure out what the 6 extra LUTs are for. This result is > > obtained using the default XST settings, where KEEP_HIERARCHY is set > > to NO. Forcing KEEP_HIERARCHY to YES results in 99 total 4LUTs, which > > is more inline with my original estimate. Am I just missing something > > obvious? > > > The second question is related to the logic cost of the shifters. From > > the XST numbers it seems that they are probably not implemented using > > 10-bit 10-to-1 MUXes (which would use about 50 4LUTs) . How are they > > actually implemented and how should I estimate their area cost? > > > I appreciate any help. > > > Danyao > > [snip] > > I'm not sure why you need to know these details unless you're > either doing this as a research project or you need to use > a whole pile of these. > > In any case one of the best ways to answer your questions is > to take a look at the "Technology Schematic" after synthesis > to see what XST did with your logic. > > My best guess on question 1 is that when flattening the design, > XST tried to merge the shift and encode functions into fewer > logic levels and ended up using more LUT's as a result of that. > > Regards, > Gabor Thanks for the reply Gabor! I wanted to know the details just out of curiosity and see what is the minimum amount of resources I can use to implement the design. This is for a research project, and in the bigger system there will be many instances of this small component, so I'd like to be able to implement it as efficiently as possible. The Technology Schematic shows priority encoders and shifters as black boxes, so I don't know how many LUTs they used to implement them. Regards, DanyaoArticle: 144493
On Dec 4, 6:39=A0am, "Nial Stewart" <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > > FPGA design using a PCB layout tool is a recipe for disaster. > > Indeed, I think they're wasting their time down this path. > > What is good is the ability to pin/netlist swap when routing and pass > that back to the FPGA constraints. They should concentrate on this and ma= king it > as flexible as possible but forget the FPGA development side of things. > > Nial. Is the tool FPGA pin type aware? I have found some layout people don't like to swap pins on FPGAs because it can be very complex due to the many constraints on pin capability. If the tool is aware of these limitations, it could help with intelligent swapping. RickArticle: 144494
What Ben said, except the asynchronous reset part. If you need
asynchronous reset (e.g. reset will work even if clock is not
working), FPGA's handle it fine. If you keep it asyncrhonous, you
need to synchronoize the deasserting edge of it; if you make it
synchronous, you need to synchronize both edges.
You won't get a latch from the missing reset on clk_count, but you
will get a "clock enable" or feedback mux on the clk_count register
because even though the description does not reset the clk_count
contents while reset is active, it does not increment or change them
either.
Other hints:
Use numeric_std library data types and operators for arithmetic.
std_logic_arith and std_logic_unsigned may reside in the ieee library,
but they are NOT standard IEEE packages.
numeric_standard defines signed and unsigned data types, for which
operators and conversion functions are appropriately defined.
In your design, clk_count could be of type unsigned, then you can
compare or add it to integer literals rather than binary bit strings.
Alternatively, clk_count could be just an integer range (0 to 2**16 -
1). Just remember that integer math does not "roll over" like vector
based math.
You can use the language to calculate your counter range. If you want
to account for uneven half cycles that will add to a total period
closest to 1200 Hz, you can calculate:
constant input_f : integer := 40000000;
constant output_f : integer := 1200;
constant period : integer := (input_f + output_f / 2) / output_f; --
round up
constant high : integer := (period + 1) / 2; -- round up
constant low : integer := period - high;
variable clk_cnt : integer range 0 to high - 1;
...
if clk_cnt = 0 then
if out_clk = '1' then
clk_cnt := low - 1; -- load low half-period
else
clk_cnt := high - 1; -- load high half_period
end if;
out_clk <= not out_clk;
else
clk_cnt := clk_cnt - 1;
end if;
Use rising_edge() or falling_edge() functions to detect the edge of a
clock; it is safer and more readable.
Assign an SLV with the value (others => '0') when you just want to set
it to all zeroes.
Andy
Article: 144495On Dec 11, 6:41=A0am, rickman <arius....@gmail.com> wrote: > On Dec 4, 6:39=A0am, "Nial Stewart" > > <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > > > FPGA design using a PCB layout tool is a recipe for disaster. > > > Indeed, I think they're wasting their time down this path. > > > What is good is the ability to pin/netlist swap when routing and pass > > that back to the FPGA constraints. They should concentrate on this and = making it > > as flexible as possible but forget the FPGA development side of things. > Yes, it should be relatively easy to verify a pin mapping match. That needs little intelligence, or groundwork, on the PCB side. > > Is the tool FPGA pin type aware? =A0I have found some layout people > don't like to swap pins on FPGAs because it can be very complex due to > the many constraints on pin capability. =A0If the tool is aware of these > limitations, it could help with intelligent swapping. There are degrees of awareness, and effort : Pinswap is the simplest, and that requires a symbol definition that groups pins as swapable. Here, the bus stays on a Pin-group, but the bit-destinations swap to reduce vias. Hopefully, this should have minimal risk of not rerouting in the FPGA post-swap. Next step is possible bank/Pin swap, which is more work, and more risk (so is less commonly done) Here, you must define both pin swap and bank swap symbols (which may include VccIO caveats) Most companies would avoid this, by first looking at what banks 'make most sense' to choose, using that venerable tool : The MK-I eyeball :) Note that Actual FPGA place and route, is usually done by the Chip Vendors tools, so calling a PCB package a 'FPGA Development System', has much more to do with marketing, than engineering reality. -jgArticle: 144496
Uwe Bonnes wrote: > > I always bug Xilinx on fairs to document the interfaces, but while technical > people at the booth understand the point, they mostly tell that higher > levels in the company will strongly oppose. > No big surprise here: if they sell a cable worth about $10 in parts for $250 they think it's good busyness. Doesn't take into account the loss from bad PR this generates. In any case there are now compatible Xilinx cable clones that are always available on e-bay for around $70 or so. In addition my understanding is that Digilent has a compatibility library now that allows their very inexpensive USB cable to be used with Xilinx tools. Didn't try it myself as I have both a genuine Xilinx cable and a clone from China that works just as well just in case. -Alex.Article: 144497
On Dec 9, 3:27=A0pm, Gabor <ga...@alacron.com> wrote: > On Dec 9, 7:36=A0am, Symon <symon_bre...@hotmail.com> wrote: > > > > > > > fab. wrote: > > > > I have a Spartan 3 FPGA clocked at 50 MHz. I have two events (rising > > > edge) happening on two different pins, about 100 us ~ 300 us =A0apart= . > > > I'd like to perform a time measurement (using the FPGA clock) on that > > > time interval with an accuracy that is higher than 1/(50E6) s. Is it > > > possible? Can somebody please redirect me to some docs/examples about > > > it. > > > > Thank you in advance, > > > Fabrizio > > > Use a DCM to make a 60MHz clock. Then you can measure with a resolution > > of 1/(60E6) s. =A01/60e6 < 1/50e6. > > > HTH, Syms. > > Hope that was tongue-in-cheek. =A0Of course he didn't say > just how much faster he needs to measure. =A0Twice as fast > as the clock? Use DDR sampling with the existing 50 MHz > clock to get 100 megasamples per second. =A04 times as fast? > Generate 4 clock phases using the DCM and sample on all > four. =A0Much faster? =A0Take a look at some old Virtex E > appnotes for high-speed LVDS that use carry chain delays > to grab the same input on multiple clock phases. > > regards, > Gabor Thank you all for the good suggestions Regards, FabrizioArticle: 144498
On Dec 10, 7:08=A0pm, Andy <jonesa...@comcast.net> wrote:
> What Ben said, except the asynchronous reset part. If you need
> asynchronous reset (e.g. reset will work even if clock is not
> working), FPGA's handle it fine. =A0If you keep it asyncrhonous, =A0you
> need to synchronoize the deasserting edge of it; if you make it
> synchronous, =A0you need to synchronize both edges.
I still maintain that asynchronous reset "isn't the best solution",
but everything Andy says is certainly true. Sometimes, you have an
external requirement for it, and in most cases the FPGA silicon and
tools will cope with it. But note that in more complex designs and on
some devices, certain blocks (e.g. DSPs, BRAMs) contain registers that
are only resetable synchronously.
Usually asynchronous resets are only needed for registers that feed an
external signal (i.e. something that goes to another chip), to prevent
problems at the board level. Internally, your design will be much more
reliable if you use synchronous resets everywhere, because the
propagation time and skew of asynchronous resets usually isn't taken
into account by static timing analysis tools. So, you can end up with
some registers coming out of reset on a different cycle from other
registers elsewhere, without warning, even when you logically
deasserted the reset at the same time. Hence, Andy's very good advice
about synchronizing that trailing edge.
Cheers,
-Ben-
Article: 144499On Dec 11, 12:08=A0am, Andy <jonesa...@comcast.net> wrote: > What Ben said, except the asynchronous reset part. If you need > asynchronous reset (e.g. reset will work even if clock is not > working), FPGA's handle it fine. =A0If you keep it asyncrhonous, =A0you > need to synchronoize the deasserting edge of it; if you make it > synchronous, =A0you need to synchronize both edges. > > You won't get a latch from the missing reset on clk_count, but you > will get a "clock enable" or feedback mux on the clk_count register > because even though the description does not reset the clk_count > contents while reset is active, it does not increment or change them > either. > > Other hints: > > Use numeric_std library data types and operators for arithmetic. > std_logic_arith and std_logic_unsigned may reside in the ieee library, > but they are NOT standard IEEE packages. > > numeric_standard defines signed and unsigned data types, for which > operators and conversion functions are appropriately defined. > > In your design, clk_count could be of type unsigned, then you can > compare or add it to integer literals rather than binary bit strings. > > Alternatively, clk_count could be just an integer range (0 to 2**16 - > 1). Just remember that integer math does not "roll over" like vector > based math. > > You can use the language to calculate your counter range. If you want > to account for uneven half cycles that will add to a total period > closest to 1200 Hz, you can calculate: > > constant input_f : integer :=3D 40000000; > constant output_f : integer :=3D 1200; > constant period : integer :=3D (input_f + output_f / 2) / output_f; -- > round up > constant high : integer :=3D (period + 1) / 2; -- round up > constant low : integer :=3D period - high; > variable clk_cnt : integer range 0 to high - 1; > ... > if clk_cnt =3D 0 then > =A0 if out_clk =3D '1' then > =A0 =A0 =A0clk_cnt :=3D low - 1; -- load low half-period > =A0 else > =A0 =A0 =A0clk_cnt :=3D high - 1; -- load high half_period > =A0 end if; > =A0 out_clk <=3D not out_clk; > else > =A0 clk_cnt :=3D clk_cnt - 1; > end if; > > Use rising_edge() or falling_edge() functions to detect the edge of a > clock; it is safer and more readable. > > Assign an SLV with the value (others =3D> '0') when you just want to set > it to all zeroes. > > Andy thanks lot for all yur Inputs ... ya its asynchnous reset i synthsised already but problm in Simulaton ... pls Correct my Code it will make me Some Correction for future Designig
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