Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
still not programming.... --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144751
On Dec 30, 8:07=A0am, Chris Abele <ccab...@yahoo.com> wrote: > On 12/29/2009 6:38 PM, Frank Buss wrote: > > > > > > > Rick wrote: > > >> I want to get back into some 'trivial' design work. I'm thinking my > >> level of sophistication is still at the ~22v10 stage and using > >> schematic capture vs. programming languages or assembler. I have read > >> enough to know this is bad form but I still understand 74LSXX and > >> would like to ease into topics like Verilog. Nothing I do requires > >> more then a couple of 4 bit counters and maybe a six bit latch with a > >> bit of glue logic. > > > You can do such small logic with a small CPLD, e.g. the XC9572XL from > > Xilinx (I've managed to implement two 19 bit counters with it and a SPI > > interface for reading). Just download the free Web Edition of Xilinx IS= E > > and then you can write Verilog or VHDL designs and test it in the > > integrated simulator. > > > If you want a starter kit, maybe this one is a good idea: > > >http://www.xilinx.com/products/devkits/DO-CPLD-DK-G.htm > > > If you want to program it in your own boards later, I can recommend the > > Xilinx Platform Cable. > > > Altera has a free web edition of the development environment, too and s= ome > > nice CPLDs and starter kits, and some Lattice CPLDs are really inexpens= ive, > > but I don't know the development tools. > > Looks like the programming cable included in that kit is for a parallel > port. =A0Few recent PCs have parallel ports anymore, and I understand tha= t > USB-to-parallel converters generally don't work with JTAG cables (or > more accurately with the software). =A0And while the Xilinx platform cabl= e > is a great solution, its costs over $200. > > For playing around at home I've had good luck with stuff from Digilent:ww= w.digilentinc.com(in fact they made the board in your kit). =A0They > have USB JTAG cable that's compatible with Xilinx tools and only costs > $60. =A0They also have two types of USB JTAG cable that work with their > free programming software (called Adept) and are even less expensive. > These are all on the "Cables & connectors" page. > > For playing with very simple logic Digilent also has a small board with > a CoolRunner CPLD for $18 (look for "C-Mod"). =A0It's basically just a wa= y > to mount the PLCC and bring the connections to DIP pads for easy > experimenter access, but sometimes that's really handy. > > Of course the C-Mod is only 64 macrocells. Digilent also has fairly > inexpensive FPGA experimenter boards: the "Basys2" board has a Spartan > 3E with 100k gates for $80, and the "Nexys" board has a Spartan 3 with > 400k gates for $90. =A0Those boards have USB built in, and don't even > require an additional programming cable. > > Chris- Hide quoted text - > > - Show quoted text - Thsnkd, I did try Diligent for the 'rookie' board but they listed it as discontinued so I went to another supplier who still had them in stock. I am weighing my options and have room for at least one obsolete computer. Looks like my best choice for a development platform would be some ISA slots, USB, serial, and printer ports which puts me somewhere back about the year 2000 vintage computer. Not really a problem since I have stuff on either side of that time period. If need be I can always get a PCI printer port or serial card. There seems to be a couple of software packages for micros like the Pony programmer that I may get interested in. RickArticle: 144752
On Dec 30, 10:50=A0am, van...@sfu.ca (Peter Van Epp) wrote: > Rick <richardcort...@gmail.com> writes: > >On Dec 29, 4:44=3DA0pm, van...@sfu.ca (Peter Van Epp) wrote: > >> Rick <richardcort...@gmail.com> writes: > ><snip> > >Hehe! I was looking for software for my Needham PB-10 earlier. I > >actually found some that is supposed to run under XP but I have to put > >it in a computer with ISA slots. I should give up the ghost. > > =A0 =A0 =A0 =A0 I still have the XT clone that it originally ran in (and = several other > ISA machines :-)). I even still have an operating Z80 CPM machine (and am > building a nwe one :-)). I had mine in a Tandy 1000TX. Still have the Tandy and it boots but hard drive is dead and I can't find the keyboard.<sigh> I really have to move on so it is probably a good thing. > > >I went ahead and got the development board from Frank's link. It was > >only $39+ shipping so it will get me into the current decade. Checked > >with Digikey and they have the CPLD in 44 pin PLCC so at least I can > >buy a carrier for wire wrap. Price is right too at about $2 per chip. > > =A0 =A0 =A0 =A0 Horrors! Not an adapter ($$$$), a through hole PLCC socke= t and some > sip www sockets from Jameco (6100-1X30W-R) or Electronix Express (ssw30s) > (http://www.elexp.com/ics_sf10.htmand cheapest), All had some at $.50 som= e > months back but I cleaned them out :-). Cut to suitable lengths for the P= LCC > pins =A0the through hole plcc socket plugs in on .1 centers giving you a = wirewrap > =A0adapter for a couple of bucks (you may have to experiment with PLCC so= ckets > if the pins are too big, all those I've tried have worked though). This i= s how > my 84 PLCC Z80 chip is wire wrapped in. Thanks for the tip. I'm getting old to the point where SOIC and my vision have crossed. No big problems with .1 centers yet. > > >I will give the Lattice a look and see what I can find. I am trying to > >tell myself I am better off with a 44 pin CPLD then a 28 pin GAL. The > >CPLD still seems like a lot of club for the distance but prices are > >about even. > > =A0 =A0 =A0 =A0 True, and learning the new stuff is a good thing for sure= but if a PAL > will do the job, by the time you add in socket cost and board area the PA= Ls > may still be a better bet against a PLCC device (not to mention a lot of = the > CPLDs are going 3.3V only). Sometimes the old stuff is still best. > > Peter Van Epp I'm trying to focus on what I want vs. what I need. My son took my Super Elf with him to work and lost it. I was thinking I would like to get a simple 1802 or 65C02 benchtop system going. The smaller Xilinx CPLD would need its own 3.3V supply but they say 'it is 5v tolerant' so if I do go that route it won't be to bad. I really should be going with an AVR or PIC but hard head and soft heart get in the way. RickArticle: 144753
On Dec 30, 11:11=A0am, Rick <richardcort...@gmail.com> wrote: > I want to get back into some 'trivial' design work. I'm thinking my > level of sophistication is still at the ~22v10 stage and using > schematic capture vs. programming languages or assembler. I have read > enough to know this is bad form but I still understand 74LSXX and > would like to ease into topics like Verilog. Nothing I do requires > more then a couple of 4 bit counters and maybe a six bit latch with a > bit of glue logic. Atmel have WinCUPL free on their web site, and that works fine from 16V8 up to ATF1508RE devices. Their ATF15xx series are 5V, and ISP with a choice of parallel port or USB JTAG programming. For 16v8/22V10/ATF750 you will need a device programmer, but you can get those cheap - or just skip to the PLCC44 ISP devices. (32/64 Macrocells) With WinCUPL you can create test vectors, which allows a development HW verify step, and also allows Pgm/Vfy/Secure/VectorTest flows on the PLDs -jgArticle: 144754
Hello I wrote a vhdl code for implementing amplifer and ADC on sparan3E board, I am working with LTC1407A-1 Dual A/D on spartan3E(with SPI protocol),my problem is when I changed the analog voltage which is applied to this A/D,the eight most significant digital value on LEDs also changed accordingly,but it's not equal to what I calculated based on the formula D[13:0]=(Gain*(Vin-1.65)*8192)/1.25v provided in the data sheet.LED's follow specific pattern for each analog voltage ,I mean I tested different voltage and every time the result on LED's were same,so my program does understand different volages,but the problem is ,it is not equivalent to what I got from formula. can anyone help?please give me an idea what I can do.Article: 144755
>On May 15, 4:00=A0pm, John McCaskill <jhmccask...@gmail.com> wrote: > >> Xilinx has switched to using FlexLM for licensing as of ISE 11.1. =A0I >> have been using multiple other software packages that use FlexLM for >> years, so I have some experience with the issues that it can cause. >> FlexLM is more restrictive than just giving you an activation ID, and >> I expect that they will be getting a lot of calls from customers about >> this. =A0However, after evaluating how Xilinx has used FlexLM, I think >> that some of your issues above have been addressed in a reasonable >> fashion, and I think that some of their licensing terms have been made >> more favorable for the customer. > >I've dealt with FlexLm in the past, and I've learned to curse its very >existence when the license server, typically in an inaccessible >location, goes down. This always happened on a weekend with a looming >Monday-morning deadline. > >But all that aside, after all these years, Xilinx still doesn't get >it. We use their software to develop applications FOR THEIR CHIPS. >There is no other use for it. Locking it down and otherwise making it >difficult to install and use is at cross purposes with Xilinx' >objectives: selling chips. > >Now I understand that there is a real cost for technical support. What >Xilinx needs to do is to uncouple tech support from the cost of the >tools. To wit: > >a) If you are a hobbyist and you want to play with a starter kit or >whatever, use the tools and use the various WWW resources for support. >You don't get a tech-support account and Xilinx won't answer your >phone calls. > >b) The professional user should be able to choose between per-incident >and blanket yearly tech-support options. Perhaps two tiers of support >should be available -- initial WebCase, and direct-to-smart-people >telephone support. The point is that if we are paying directly for the >support, we expect REAL results and not the usual web-case runarounds. > >c) In either case, any user (from the hobbyist to the pro) should be >able to report bugs and get updates on their resolutions. Xilinx >should not cut off a source of bug reports simply because the users >aren't paying for support. > >As it is now, users who buy ISE/EDK etc spend a lot of money and don't >get any real support, and this latest licensing nonsense is a kick in >the teeth. > >-a > Amen to that. We use Xilinx at NASA and I am having so many problems using the new software 11.1 with the floating license. I am going to downgrade to 10.1. I liked Xilinx over Altera even more because of the node-locked licensing and the fact that they make money from their chips. Now, they are following the same route as Altera. Sell h/w...give s/w free. Support pay..bug fixes free. SalmanArticle: 144756
On Wed, 30 Dec 2009 14:36:19 -0600, "mlajevar" wrote: >I wrote a vhdl code for implementing amplifer and ADC on sparan3E board, I >am working with LTC1407A-1 Dual A/D on spartan3E(with SPI protocol),my >problem is when I changed the analog voltage which is applied to this >A/D,the eight most significant digital value on LEDs also changed >accordingly,but it's not equal to what I calculated based on the formula >D[13:0]=(Gain*(Vin-1.65)*8192)/1.25v provided in the data sheet.LED's >follow specific pattern for each analog voltage ,I mean I tested different >voltage and every time the result on LED's were same,so my program does >understand different volages,but the problem is ,it is not equivalent to >what I got from formula. can anyone help?please give me an idea what I can >do. First you can start to be a scientist :-) Sure it's not equivalent to the formula. Shit happens. But what IS it? Is it linear? Is it monotonic? Have you graphed it? You say it's repeatable, so surely you can do that. The formula you quote depends on the values of reference voltages; are they set correctly? Where do they come from? Have you used the correct filtering and grounding, as indicated in the device data sheet? Engage brain, and enlightenment often follows. -- Jonathan BromleyArticle: 144757
Rick <richardcortese@gmail.com> writes: <snip> >Looks like my best choice for a development platform would be some ISA >slots, USB, serial, and printer ports which puts me somewhere back >about the year 2000 vintage computer. Not really a problem since I >have stuff on either side of that time period. If need be I can always >get a PCI printer port or serial card. Not quite that bad, just a relatively more expensive server motherboard (well except for the ISA slots). I have a quad core AMD machine with an ASUS M2N-LR server mother board which has 2 serial and a parallel port (although come to think of it I haven't tried that with a parallel programming cable yet). Mostly I wanted the 2 PCIX slots (it also has a PCIE 16 lane) for doing gigabit ethernet work (with FPGAs in fact :-)). Cost around $1500 Canadian with 4 gigs of fast ram and dual quad core AMD processors case etc. Although at that point I think one of the USB progtamming cables may be a better bet even at a couple of hundred ... PeterArticle: 144758
Rick <richardcortese@gmail.com> writes: <snip> >I'm trying to focus on what I want vs. what I need. My son took my >Super Elf with him to work and lost it. I was thinking I would like to >get a simple 1802 or 65C02 benchtop system going. The smaller Xilinx >CPLD would need its own 3.3V supply but they say 'it is 5v tolerant' >so if I do go that route it won't be to bad. I really should be going >with an AVR or PIC but hard head and soft heart get in the way. >Rick But I want it all :-), affording it is the problem. I'm in to PICs as well, invaluable for some small jobs. Note that when they say the CPLD is 5V tolerant they mean the I/O pins will drive TTL and (more importantly) can be driven from 5V pulled up signals without latchup and self distuction (the old "stop and catch fire" unimlemented instruction in the 6502 :-)), you still need 3.3V as the CPLD power supply. There are 5V to 3.3 LDO regulators to get that from 5V however (which you may already know). The idea of the Z80 board is to have a board which will run CPM (now available open source) with I/O ports that can provide test signals to an FPGA without requiring a cycle of compile on PC move to Z80 run, repeat. Of course I learned programing in assembler on a Z80 40 years ago so it seems natural to me (these days you get looked at stangely when you mention assembler rather than C :-)). You may also be interested in the sdcc open source C compiler which supports Z80, 8251s and PICs. For expensive toys there is tech tools (www.tech-tools.com), I have one of their DV3400 200/400 meg logic analysers (just used it in fact to deterimine that a GPS board is running at 9100 baud not 9600 ...) which may be of interest to some of the other folks in here as well. PeterArticle: 144759
On Dec 30, 3:36=A0pm, "mlajevar" <mahsa_lajeva...@yahoo.com> wrote: > please give me an idea what I can do. 1. Use either an oscilloscope or a multi-meter to make a measurement of the analog input and reference voltages 2. If #1 checks out, run a simulation and verify correct operation of your SPI interface code. This basic process works to solve most any design problem. If you're stumped and have no hypothesis to explain the unwanted behavior, then you make measurements to give you additional insight (#1), or run additional simulation test cases (#2) until you finally can say 'Ah ha!'...then you fix whatever it was that caused you to say 'Ah ha!' Kevin JenningsArticle: 144760
Hello thanks for your idea, I did the simulation for amplifier part to check if SPI communication working properly or not,and it was right,after that I made a op level module from my amplifier combined with ADC behavior which I cannot simulate it ,because t needs analog voltage,so all I can do for the top level is to check it when it is programmd on the board. Moreover,the reference volatge generated via a voltage divider on the board,I just applied 3.3 volt from power supply to vcc og Header J7,so I suppose reference voltage should be right. the thing is what I got from LEDs is not even two's complement or invert form of what I expected from formula. with these information,does any one have new idea? thanks in advance --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144761
On Dec 30, 11:43=A0pm, "mlajevar" <mahsa_lajeva...@yahoo.com> wrote: > I did the simulation for amplifier part to check if SPI communication > working properly or not,and it was right,after that I made a op level > module from my amplifier combined with ADC behavior which I cannot simula= te > it ,because t needs analog voltage, VHDL has a data type 'real', analog voltages can be modelled quite nicely. The transfer function of your ADC can be implemeted quite easily. To simulate the ADC, make an entity with all of the I/O using type 'real' for any of the analog inputs. Next compute the ADC output and finally implement the SPI interface of the ADC. Do all of this by consulting the data sheet for the part. Now you have a simulation model for the ADC that will work with your design. Beef up your testbench for your FPGA to include the ADC model and some form of stimulus (even a constant voltage) for the ADC input. > so all I can do for the top level is to > check it when it is programmd on the board. > If the problem is actually in the VHDL code that you wrote, then checking it on the board is doing it the hard way. If the problem is in the analog portion of the board then a meter or scope is all you should need to find the problem. Looking at LED patterns is like looking at Christmas lights and provides little information about the problem unless it was something simple like the LED values represent 1/2 or 2x the correct value or some simple to spot thing like that. > Moreover,the reference volatge generated via a voltage divider on the > board,I just applied 3.3 volt from power supply to vcc og Header J7,so I > suppose reference voltage should be right. > Suppose all you want...I suggested to measure and verify so that you wouldn't have to speculate and guess. > the thing is what I got from LEDs is not even two's complement or invert > form of what I expected from formula. with these information,does any one > have new idea? thanks in advance =A0 =A0 =A0 =A0 =A0 > It's not at all clear just what you know is working and what is not. It sounds like you wrote some VHDL and the logic is being implemented in some board that has a Spartan 3E on it. Is the board design in question or is it the VHDL that controls the ADC? Or maybe the LED driver? If the board is in question then the meter on the analog signals will clear it all up. Once you've verified that the inputs to the ADC are correct, then guess what, the problem is in your VHDL code...and simulation will find it...IF you model the system correctly (i.e. the above mentioned ADC model has been verified to the data sheet for the part, the interconnect from ADC to Spartan is correct, the interconnect between Spartan and LEDs are modelled correctly) Kevin JenningsArticle: 144762
Hi all, I implemented a small statemachine with 2 states, State A triggers counter A, when counter A reaches 255 the state machine jumps to state B which triggers counter B, when counter B reaches 255 the state machine goes to state A again. This repeats forever. The counter is implemented as a component and the top module instantiates two of them. The code is in VHDL and I am using Xilinx ISE 11.4 When I viewed the RTL schematic, one counter is connected to the rest of the state machine and the counter is floating with no connections. However when i wrote a testbench and simulated it the result is correct. Can please someone give me an explanation? Thanks and Happy New Year, Regards, JosephArticle: 144763
For any of you that wanted one of our boards but didn't want to pay the shipping our shop is running a special offer of free worldwide shipping on purchases over GBP=A3 100. Offer is running until the end of January, or we run out of stock, whichever comes first. We would rather ship it than move it. More updates on our move in the coming few weeks. John Adair Enterpoint Ltd.Article: 144764
Chris Abele <ccabele@yahoo.com> writes: > parallel port. Few recent PCs have parallel ports anymore, and I > understand that USB-to-parallel converters generally don't work with You can still get a PCIe parallel port card for twenty something dollars. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 144765
>Hi all, > >I implemented a small statemachine with 2 states, State A triggers >counter A, when counter A reaches 255 the state machine jumps to state >B which triggers counter B, when counter B reaches 255 the state >machine goes to state A again. This repeats forever. > >The counter is implemented as a component and the top module >instantiates two of them. The code is in VHDL and I am using Xilinx >ISE 11.4 When I viewed the RTL schematic, one counter is connected to >the rest of the state machine and the counter is floating with no >connections. However when i wrote a testbench and simulated it the >result is correct. > >Can please someone give me an explanation? > >Thanks and Happy New Year, > >Regards, > >Joseph It probably determined that the two counters are never used at the same time and could use one to do both tasks. Try changing the time outs to non-matching values and see how that affects the outcome. > --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144766
On Dec 29, 6:42 pm, vcar <hi...@163.com> wrote: > On 12=D4=C229=C8=D5, =CF=C2=CE=E76=CA=B112=B7=D6, glen herrmannsfeldt <g.= ..@ugcs.caltech.edu> wrote: > > > > > > > Frank Buss <f...@frank-buss.de> wrote: > > > vcar wrote: > > >> For certainreasons, I could not use battery on my board, so the > > >> Virtex5 bitstream encryptioncould not be used. In this situation, wh= at > > >> could I do to protect my design on areasonable level? > > > Protecting against exact clones is difficult. In many cases, decoding > > the bits back to logic is hard enough not to worry about that. > > > > I don't know the answers to your questions, but I guess an attacker c= ould > > > at least just desolder the XCF16P and reading it like the FPGA does w= hen > > > booting, so even the read protection bit of the flash is useless. If = you > > > want to secure your device, I would use something like the DS2401. Th= is > > > provides a unique id. You could save this in the flash and compare it= from > > > the FPGA with the chip. The chip is available in packages which looks= like > > > a capacitor or diode: > > > As long as they don't read this newsgroup and know what to look for... > > > -- glen > > Hi, glen. > My point is to protect my board from cloning, so the attacker do not > need to decoding bit stream back to logic. Once they obtain the bit > stream, they can produce my board themselves. > I could not protect the PCB from cloning, so I have to do something on > my bit stream. Otherwise it is very easy to copy my board.- Hide quoted t= ext - > > - Show quoted text - If the bitstream is not using the AES encryption then there is very little that you can do to prevent the entire board from being cloned as anyone that has one of your original boards can easily extract the data from the PROM. There are some alternatives, but they aren't as secure. See Xilinx Whitepager WP266 and Application Note XAPP780 Ed McGettigan -- Xilinx Inc.Article: 144767
It's easier for me to manage keeping my definitions consistent, because I have direct control over that, than to deal with how multiple synthesis tools deal with records. If all the tools did a good job of dealing with records, I'd be happy to use them, but several of the tools have problems, and the tool vendors' answer when one runs into these problems is just like the doctor's reply to "it hurts when I do this".Article: 144768
I would like to create a generic multiplexer in Verilog were I can set the number of inputs and data bits. I can create something using 2 input multiplexers cascaded but this produces a priority structure which uses more logic resources. If anyone can give me a clue as to if it is possible that would be great. Jon --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144769
maxascent <maxascent@yahoo.co.uk> wrote: > I would like to create a generic multiplexer in Verilog were I can set the > number of inputs and data bits. I can create something using 2 input > multiplexers cascaded but this produces a priority structure which uses > more logic resources. If anyone can give me a clue as to if it is possible > that would be great. The synthesis tools that I know of will easily optimize out any difference that you might be thinging about, at least for FPGA targets. (You did post to comp.arch.fpga.) That is especially true for LUT4 architecture FPGAs. I believe the usual generated form is more like an N to 2**N decoder, followed by AND/OR logic. That is especially true if it is more than one bit wide, which requires only one decoder. -- glenArticle: 144770
I did a quick experiment using Synplify were I created 2 multiplexers of 4 inputs with 64-bit data, one using my cascaded 2 input mux and another using a case statement. The one with the case statement used less resorces. So either I have coded the first incorrectly or Synplify is interpreting the code differently. Jon --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144771
On Fri, 2010-01-01 at 06:16 -0600, maxascent wrote:=20 > I did a quick experiment using Synplify were I created 2 multiplexers of = 4 > inputs with 64-bit data, one using my cascaded 2 input mux and another > using a case statement. The one with the case statement used less resorce= s. > So either I have coded the first incorrectly or Synplify is interpreting > the code differently. I did the experience that is depends on the FPGA type (Lut type, ...) and vendor (maybe tools). So, I think it is a good practice to test it for the different factors. cheers benArticle: 144772
Nobody who can help me? >Hi, > >I want to send a video file from a pc to a FPGA (on a XUPV2P development >board) via the PCI interface. On the FPGA the video will be processed by an >algorithm. The result, after processing, will be send back to the pc. I >generated the VHDL-code of the algorithm in Simulink with Xilinx System >Generator (gateway_in and gateway_out are 8 bits wide). I also have the >VHDL-code of the PCI-core (from Xilinx). In Xilinx ISE I instantiated the >algorithm in the PCI-code. > >The resolution of the video is 320x240. The device driver on the pc (Linux) >gives an interrupt at the beginning of every frame. Can someone tell me how >I have to adapt the code of the user application delivered by Xilinx ( code >can be found here : http://www.mediafire.com/?kyygtdm0wlj ) to give the >FPGA a sign to start processing the data and send the result back to the pc >after a frame has been processed? Is there a manner to check how many >bits/bytes/pixels passed by? > >Thanks in advance. > > > > --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144773
On Jan 1, 4:51=A0am, "maxascent" <maxasc...@yahoo.co.uk> wrote: > I would like to create a generic multiplexer in Verilog were I can set th= e > number of inputs and data bits. I can create something using 2 input > multiplexers cascaded but this produces a priority structure which uses > more logic resources. If anyone can give me a clue as to if it is possibl= e > that would be great. > > Jon =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > This message was sent using the comp.arch.fpga web interface onhttp://www= .FPGARelated.com One of the simplest and most consistent multiplexers I've used is with arrays of registers or wires. wire [p:0] my_sel; wire [n:0] my_array [m:0]; // assign m+1 my_array values to the desired inputs reg [n:0] my_output; // always @(posedge clk) my_output <=3D my_array[my_sel];Article: 144774
On Dec 29 2009, 10:07=A0am, Selensky <selen...@gmail.com> wrote: > > Are native 3-port mode supported by which Xilinx devices? Without > duplicating memories? Is there any constraint about using this > operation mode combined with different aspect data ratio? I had heard > something about native support of 3-port (two read and one write port > with 3 different addresses) in Altera devices only. > > Selensky Any good synthesizer can take one memory array with one write and multiple reads and effectively replicate the memories without manual intervention from the user. As long as the memory inferences are written in a way which properly instantiates one memory, having multiple reads inferred in the same "structure" automatically replicates the memories delivering post-synthesis names for the memory elements that are slightly different.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z