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Schematics and UCF file are now available for our Spartan-6 board Drigmorn3. They can be found http://www.enterpoint.co.uk/drigmorn/drigmorn3.html. I'm hoping the manual will follow shortly in the next few days. John Adair Enterpoint Ltd.Article: 143901
Frank Buss <fb@frank-buss.de> wrote:
>MK wrote:
>
>> Tried to look at it but Acrobat says the file is damaged and can't be
>> repaired. I downloaded it a few times.
>
>Works for me. Maybe try right click and "save as", then open the PDF, not
>within the browser, sometimes Acrobat Reader has problems when loading it
>from within a web browser.
>
>BTW: the W7100 microcontroller sounds interesting: 64 kB flash, 64 kB SRAM,
>32 IO ports and TCP/IP for $6.40 ( http://tinyurl.com/yev4vzy ).
NXP's LPC1700 series (Cortex M3) is probably cheaper and has at least
5 times more performance.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 143902Nico Coesel wrote: > NXP's LPC1700 series (Cortex M3) is probably cheaper and has at least > 5 times more performance. You are right, the chip is interesting. The smallest one of the LPC1700 family with network support costs about the same as the W7100, but has an additional DAC, ADC and USB: http://search.digikey.com/scripts/DkSearch/dksus.dll?vendor=0&keywords=lpc1764 -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 143903
Sam Kerr <stkerr@purdue.edu> wrote: > I'm trying to create a ring oscillator for my FPGA design but I've run > into some problems. Namely, it doesn't seem like any oscillation is > occurring. I've hooked up the output signal to LEDs and the serial port, > but neither of these shows any oscillations. > > A few things I think might be happening is that the oscillation is so fast > I just can't see it, the oscillation is too fast for the board, it's > getting optimized out during synthesis, or (probably) my Verilog file is > implemented incorrectly. If you really mean "see", I am pretty sure it would be too fast to see on the LED. In the CD4000 series days, we used to make slower ones with three inverters and an RC delay. (Or maybe with just one.) If you do keep all three inverters (no optimizing them away), you should be in the 100's of MHz range. Run through a 30 bit ripple counter and then you should be able to see it. -- glenArticle: 143904
I design FPGA based test boards with CyPress EZ USB 2.0 Device. This allows us to commmunicate to the test boards from the Host PC over USB2.0 link from Host PC to the test board. The Ez USB device on the test board connects to the FPGA with a simplified General Purpose Interface. But some times we have multipe FPGAs on the test board. We have a mechanism to pass the primary General Purpose Bus from the EzUSB device to the secondary General Purpose bus of the othe FPGAs. I was curious if there is standard developed for inter FPGA communication bus. It may be more efficient to follow such a standard. Any comments?Article: 143905
On Nov 2, 8:36=A0pm, Frank Buss <f...@frank-buss.de> wrote: > Nico Coesel wrote: > > NXP's LPC1700 series (Cortex M3) is probably cheaper and has at least > > 5 times more performance. > > You are right, the chip is interesting. The smallest one of the LPC1700 > family with network support costs about the same as the W7100, but has an > additional DAC, ADC and USB: > > http://search.digikey.com/scripts/DkSearch/dksus.dll?vendor=3D0&keyword..= . > > -- > Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-sys= tems.de yes and no, I have the LPC1768 sample on my desk, yet i consider the W7100 interesting too. LPC1768 has no ethernet PHY and W7100 has lots of ethernet "in hardware" so for tasks where you need ETH+something and do not need the extras the W7100 maybe better AnttiArticle: 143906
hello,all
i have built an edk project(based microblaze) . Because my
application c code is very big,when generating linker script ,i put some
big sections into the ddr and others into bram in microblaze.finally,it
displays the results through rs232.
for now,i want to try to import the EDK Project with microblaze as
Sub-system into a ISE project and i use the cammand h "export to project
navigator",then it generate a system.ise file.but,when i put the
system_stub.bit,system_stub_bd.bmm and my_project.elf(software bits)
files
into the board ,it does not work well.
however,if i replace the my_project.elf to TestApp_Memory.elf
(linking script in bram not ddr),it works well.
who can tell me the reasnon ? what can i should do?thank you very
much..
---------------------------------------
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Article: 143907On Nov 2, 12:25=A0pm, Test01 <cpan...@yahoo.com> wrote: > I design FPGA based test boards with CyPress EZ USB 2.0 Device. This > allows us to commmunicate to the test boards from the Host PC over > USB2.0 link from Host PC to the test board. =A0The Ez USB device on the > test board connects to the FPGA with a simplified General Purpose > Interface. > > But some times we have multipe FPGAs on the test board. We have a > mechanism to pass the primary General Purpose Bus from the EzUSB > device to the secondary General Purpose bus of the othe FPGAs. > > I was curious if there is standard developed for inter FPGA > communication bus. =A0It may be more efficient to follow such a > standard. > > Any comments? In the early days of FPGAs, *nothing* got done in a single FPGA. One board I worked on had 32 of them. A google search gets 2.7 hits... Including papers from Altera and MIT. Your two basic options are "serial" and "parallel", and you can create simplex, half-duplex and full-duplex interfaces. I would be tempted to start with something that looked like a FIFO inside the FPGA, and had data, clock and strobe on the interconnect pins. ALArticle: 143908
On Oct 27, 10:17=A0pm, luudee <rudolf.usselm...@gmail.com> wrote: > On Oct 27, 9:47=A0pm, austin <aus...@xilinx.com> wrote: > > > Rudi, > > > I do not know. =A0That is the purpose of documentation, to document. > > > One thought I had is that this works by measuring the difference > > between an open line, and a terminated line, at the transmitter. =A0Suc= h > > analog measurement techniques only work for an exact fixed length of > > the PCIe bus connection. =A0If you are using extension cables, or an > > extension card, the length of the transmission lines may affect the > > measurement. > > > Austin > > Hi Austin, > > I feel that in this case the documentation fails to document. > The description for Receiver Detect is a) incomplete; and, > b) scattered throughout unrelated sections. > > My understanding is that this logic works by measuring the > time it takes to charge the coupling capacitor. (It is present and > correct value on my board). Cable length should not matter. > > Receiver Detection is described starting on page 151 in ug198. > It clearly shows a waveform diagram, where I enter powermode > 2'b10, and the next cycle assert TXDETECTRX. And some time > later, I will get PHYSTATUS, that validates the value on RXSTATUS > lines. > > But than, in table 5-14 (page 111) I find out that TXELECIDLE > also must be asserted to initiate Receiver Detection. > > And again, in other parts of the document, I find that when > changing powermode, I need to wait for PHYSTATUS to indicate > that power mode has been changed (change completed). > > I have tried the original description as on page 151, as well, > as adding the other bits I found out. And still, I consistently > get "No Receiver Detected". > > The other side has no problem detecting my hardware. > > Is there somebody who knows this stuff inside out and can > shed some light on how to make this work ? > > Thanks, > rudi I am curious. Has anybody out there actually used the Remote Receiver detect function ? Am I the only one ? Thanks, rudiArticle: 143909
On Nov 3, 4:27=A0am, "gentel" <gente...@163.com> wrote: > hello,all > =A0 =A0 =A0 i have built an edk project(based microblaze) . Because my > application c code is very big,when generating linker script ,i put some > big sections into the ddr and others into bram in microblaze.finally,it > displays the results through rs232. > =A0 =A0 =A0 for now,i want to try to import the EDK Project with microbla= ze as > Sub-system into a ISE project and i use the cammand h "export to project > navigator",then it generate a system.ise file.but,when i put the > .system_stub.bit,system_stub_bd.bmm and my_project.elf(software bits) > files > into the board ,it does not work well. > =A0 =A0 =A0 =A0however,if i replace the my_project.elf to TestApp_Memory.= elf > (linking script in bram not ddr),it works well. > =A0 =A0 =A0 =A0who can tell me the reasnon ? what can i should do?thank y= ou very > much.. > > --------------------------------------- =A0 =A0 =A0 =A0 > This message was sent using the comp.arch.fpga web interface onhttp://www= .FPGARelated.com and what magic loads the object into the extenal DDR memory? maybe you forget the ram loader? AnttiArticle: 143910
On Nov 3, 12:12=A0am, Frank Buss <f...@frank-buss.de> wrote: > > BTW: the W7100 microcontroller sounds interesting: 64 kB flash, 64 kB SRA= M, > 32 IO ports and TCP/IP for $6.40 (http://tinyurl.com/yev4vzy). Reminds me of the DS80C4xx from Dallas, which also has 64K RAM, only that has ROM, (and no Phy) - price of $8/1K on the Dallas part, and it's not clear what the volume price of the W7100 is. (ie that $6.40 looks like a promo price ..? ) No ADCs and no SPI port - so the Ethernet pumps nicely into this device, but where does it go from there ? [Could make a nice FPGA peripheral ? ;) ] Seems to need TWO crystals ?, and has interesting ROM/FLASH speed comparisons. ROM looks 4x faster, so they have simple maths libraries included in ROM How well does the W7100 debug tool chain work ? -jgArticle: 143911
On Nov 3, 3:20=A0am, Sam Kerr <stk...@purdue.edu> wrote: > I'm trying to create a ring oscillator for my FPGA design but I've run > into some problems. Namely, it doesn't seem like any oscillation is > occurring. I've hooked up the output signal to LEDs and the serial port, > but neither of these shows any oscillations. It is 'good practice' when doing ring oscillators, to build them using alternate inverter/nand/inverter/nand + final inverter/nand and enable the nands from your reset. This ensures it does start correctly, and also helps avoid the optimize away diseases... Start with a LOT of elements in your ring, and calculate a delay for a pair, then revisit your element count. Not many data sheets have these numbers... I guess they are scared designers might rely on the numbers. -jgArticle: 143912
On Nov 3, 9:34=A0am, -jg <jim.granvi...@gmail.com> wrote: > On Nov 3, 12:12=A0am, Frank Buss <f...@frank-buss.de> wrote: > > > > > BTW: the W7100 microcontroller sounds interesting: 64 kB flash, 64 kB S= RAM, > > 32 IO ports and TCP/IP for $6.40 (http://tinyurl.com/yev4vzy). > > Reminds me of the DS80C4xx from Dallas, which also has 64K RAM, only > that has ROM, (and no Phy) - price of $8/1K on the Dallas part, and > it's not clear what the volume price of the W7100 is. > (ie that $6.40 looks like a promo price ..? ) > > No ADCs and no SPI port - so the Ethernet pumps nicely into this > device, but where does it go from there ? > [Could make a nice FPGA peripheral ? ;) ] > > Seems to need TWO crystals ?, and has interesting ROM/FLASH speed > comparisons. ROM looks 4x faster, so they have simple > maths libraries included in ROM > > How well does the W7100 debug tool chain work ? > > -jg Jim, I do not know yet :( as I wrote, I had W3100 samples, and never used them.. (they had silicon errata too much..) the 2 clock is sure major PITA, but it less hassle then external PHY hm.. I also have samples of another 8051ETH mcu with PHY and 512KB flash that cost below 6$ but there is no 49$ devkit for that one, maybe time for me to make one:) as of W7100 its all about the "easy", it makes sense to use it, if there support and reference design are just superior, if not then no reason to consider the wiznet iMCU my 2 cents AnttiArticle: 143913
>On Nov 3, 4:27=A0am, "gentel" <gente...@163.com> wrote: >> hello,all >> =A0 =A0 =A0 i have built an edk project(based microblaze) . Because my >> application c code is very big,when generating linker script ,i put some >> big sections into the ddr and others into bram in microblaze.finally,it >> displays the results through rs232. >> =A0 =A0 =A0 for now,i want to try to import the EDK Project with microbla= >ze as >> Sub-system into a ISE project and i use the cammand h "export to project >> navigator",then it generate a system.ise file.but,when i put the >> .system_stub.bit,system_stub_bd.bmm and my_project.elf(software bits) >> files >> into the board ,it does not work well. >> =A0 =A0 =A0 =A0however,if i replace the my_project.elf to TestApp_Memory.= >elf >> (linking script in bram not ddr),it works well. >> =A0 =A0 =A0 =A0who can tell me the reasnon ? what can i should do?thank y= >ou very >> much.. >> >> --------------------------------------- =A0 =A0 =A0 =A0 >> This message was sent using the comp.arch.fpga web interface onhttp://www= >.FPGARelated.com > >and what magic loads the object into the extenal DDR memory? > >maybe you forget the ram loader? > >Antti > >thanks for your reply!when generating linker script,i put sections such as heap,.stack,.text,and.bss into the ddr ,it works well when downloading the board in sdk.ram loader ?what do you mean? --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143914
>On Nov 3, 4:27=A0am, "gentel" <gente...@163.com> wrote: >> hello,all >> =A0 =A0 =A0 i have built an edk project(based microblaze) . Because my >> application c code is very big,when generating linker script ,i put some >> big sections into the ddr and others into bram in microblaze.finally,it >> displays the results through rs232. >> =A0 =A0 =A0 for now,i want to try to import the EDK Project with microbla= >ze as >> Sub-system into a ISE project and i use the cammand h "export to project >> navigator",then it generate a system.ise file.but,when i put the >> .system_stub.bit,system_stub_bd.bmm and my_project.elf(software bits) >> files >> into the board ,it does not work well. >> =A0 =A0 =A0 =A0however,if i replace the my_project.elf to TestApp_Memory.= >elf >> (linking script in bram not ddr),it works well. >> =A0 =A0 =A0 =A0who can tell me the reasnon ? what can i should do?thank y= >ou very >> much.. >> >> --------------------------------------- =A0 =A0 =A0 =A0 >> This message was sent using the comp.arch.fpga web interface onhttp://www= >.FPGARelated.com > >and what magic loads the object into the extenal DDR memory? > >maybe you forget the ram loader? > >Antti > >thanks for your reply!when generating linker script,i put sections such as heap,.stack,.text,and.bss into the ddr ,it works well when downloading the board in sdk.ram loader ?what do you mean? --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143915
On Nov 3, 9:41=A0am, -jg <jim.granvi...@gmail.com> wrote: > On Nov 3, 3:20=A0am, Sam Kerr <stk...@purdue.edu> wrote: > > > I'm trying to create a ring oscillator for my FPGA design but I've run > > into some problems. Namely, it doesn't seem like any oscillation is > > occurring. I've hooked up the output signal to LEDs and the serial port= , > > but neither of these shows any oscillations. > > =A0It is 'good practice' =A0when doing ring oscillators, to build them > using > alternate inverter/nand/inverter/nand + final inverter/nand and enable > the nands from your reset. > > =A0This ensures it does start correctly, and also helps avoid the > optimize away diseases... > > =A0Start with a LOT of elements in your ring, and calculate a delay for > a pair, then revisit your element count. > =A0Not many data sheets have these numbers... I guess they are scared > designers might rely on the numbers. > > -jg Jim, and others: 4 levels of logic in the "ring" delivers usable clock on most known FPGA's (assuming it is real 4 levels of logic, that is not optimized into single lut) the clock from "4 LL ring oscillator" may be too high to be used as main system clock, so its good practice to divide with F/F, and use the divided clock for the rest of the system, or for more margin pre divide by 4 or 8 the ring clock will be in the frequency range where 1 F/F safely triggers (this clock may be over 200MHz! depend on family) AnttiArticle: 143916
On Nov 3, 9:57=A0am, "gentel" <gente...@163.com> wrote: > >On Nov 3, 4:27=3DA0am, "gentel" <gente...@163.com> wrote: > >> hello,all > >> =3DA0 =3DA0 =3DA0 i have built an edk project(based microblaze) . Beca= use my > >> application c code is very big,when generating linker script ,i put > some > >> big sections into the ddr and others into bram in microblaze.finally,i= t > >> displays the results through rs232. > >> =3DA0 =3DA0 =3DA0 for now,i want to try to import the EDK Project with > microbla=3D > >ze as > >> Sub-system into a ISE project and i use the cammand h "export to > project > >> navigator",then it generate a system.ise file.but,when i put the > >> .system_stub.bit,system_stub_bd.bmm and my_project.elf(software bits) > >> files > >> into the board ,it does not work well. > >> =3DA0 =3DA0 =3DA0 =3DA0however,if i replace the my_project.elf to > TestApp_Memory.=3D > >elf > >> (linking script in bram not ddr),it works well. > >> =3DA0 =3DA0 =3DA0 =3DA0who can tell me the reasnon ? what can i should= do?thank > y=3D > >ou very > >> much.. > > >> --------------------------------------- =3DA0 =3DA0 =3DA0 =3DA0 > >> This message was sent using the comp.arch.fpga web interface > onhttp://www=3D > >.FPGARelated.com > > >and what magic loads the object into the extenal DDR memory? > > >maybe you forget the ram loader? > > >Antti > > >thanks for your reply!when generating linker script,i put sections such = as > > .heap,.stack,.text,and.bss into the ddr ,it works well when downloading t= he > board in sdk.ram loader ?what do you mean? =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > This message was sent using the comp.arch.fpga web interface onhttp://www= .FPGARelated.com i mean you need to write YOUR OWN code and ELF to something conversion tools, and use some flash or removable media to "bootstrap" your application or use XMD during debugging AnttiArticle: 143917
>On Nov 3, 9:57=A0am, "gentel" <gente...@163.com> wrote: >> >On Nov 3, 4:27=3DA0am, "gentel" <gente...@163.com> wrote: >> >> hello,all >> >> =3DA0 =3DA0 =3DA0 i have built an edk project(based microblaze) . Beca= >use my >> >> application c code is very big,when generating linker script ,i put >> some >> >> big sections into the ddr and others into bram in microblaze.finally,i= >t >> >> displays the results through rs232. >> >> =3DA0 =3DA0 =3DA0 for now,i want to try to import the EDK Project with >> microbla=3D >> >ze as >> >> Sub-system into a ISE project and i use the cammand h "export to >> project >> >> navigator",then it generate a system.ise file.but,when i put the >> >> .system_stub.bit,system_stub_bd.bmm and my_project.elf(software bits) >> >> files >> >> into the board ,it does not work well. >> >> =3DA0 =3DA0 =3DA0 =3DA0however,if i replace the my_project.elf to >> TestApp_Memory.=3D >> >elf >> >> (linking script in bram not ddr),it works well. >> >> =3DA0 =3DA0 =3DA0 =3DA0who can tell me the reasnon ? what can i should= > do?thank >> y=3D >> >ou very >> >> much.. >> >> >> --------------------------------------- =3DA0 =3DA0 =3DA0 =3DA0 >> >> This message was sent using the comp.arch.fpga web interface >> onhttp://www=3D >> >.FPGARelated.com >> >> >and what magic loads the object into the extenal DDR memory? >> >> >maybe you forget the ram loader? >> >> >Antti >> >> >thanks for your reply!when generating linker script,i put sections such = >as >> >> .heap,.stack,.text,and.bss into the ddr ,it works well when downloading t= >he >> board in sdk.ram loader ?what do you mean? =A0 =A0 =A0 =A0 >> >> --------------------------------------- =A0 =A0 =A0 =A0 >> This message was sent using the comp.arch.fpga web interface onhttp://www= >.FPGARelated.com > >i mean you need to write YOUR OWN code and ELF to something conversion >tools, and use some >flash or removable media to "bootstrap" your application > >or use XMD during debugging > >Antti > >oh,i use the xilinx virtex_2 pro borad and it only has a cf card interface and i can not understand fully what you have said .now i do not know how to doļ¼can you tell me some detailed steps or pdf instructions?thanks very much.. --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143918
> >oh,i use the xilinx virtex_2 pro borad and it only has a cf card interfa= ce > > .and i can not understand fully what you have said .now i do not know how > to do=EF=BC=8Ccan you tell me some detailed steps or pdf instructions?tha= nks very > much.. =C2=A0 =C2=A0 if you have systemace based board then you can load the image from CF also it does use the JTAG debug interface for software loading, this however only works if you load from ace file, if you load the bit file over jtag with debug cable the soft would not get initialized otherwise creating an custom ram loader is one ore more MAN-WEEK of work this is the time YOU have to spend doing real work, asking for help doesnt count as work done AnttiArticle: 143919
>> >oh,i use the xilinx virtex_2 pro borad and it only has a cf card interfa= >ce >> >> .and i can not understand fully what you have said .now i do not know how >> to do=EF=BC=8Ccan you tell me some detailed steps or pdf instructions?tha= >nks very >> much.. =C2=A0 =C2=A0 > >if you have systemace based board then you can load the image from CF >also >it does use the JTAG debug interface for software loading, this >however only >works if you load from ace file, if you load the bit file over jtag >with debug cable >the soft would not get initialized > >otherwise creating an custom ram loader is one ore more MAN-WEEK of >work >this is the time YOU have to spend doing real work, asking for help >doesnt >count as work done > >Antti >thank you very much.thanks for your reply. --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143920
Some weeks ago I asked about the availability of the Source Files for the Image processing example on the Xilinx Spartan6 SP601 demoboard. What happened? The file rdf0003.zip on http://www.xilinx.com/products/boards/sp601/reference_designs.htm was silently exchanged and grew from 1.4 MByte to over 17.5 MByte and now contains the full fledge project! So anybody also in quest for the sources should download rdf0003.zip again. Some note on the webpage about the update would have made things much clearer! -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 143921
Hi all, I am simulating a entity with Modelsim (v6.5c). Modelsim only displays the input/output signals of the simulated top entity. When I run simulation Modelsim displays only changes of input/output signals of the top entity verilog module i.e. testbench (in objects window i.e. in wave window), but nothing happening with signals declared in the instantiated verilog modules. (PS: In Cadence SimVision, I know that I was able to see changes of all signals in testbench and also in instantiated verilog modules, in wave window) Is there a way of viewing the internal signals declared in the instantiated verilog modules in Modelsim in wave window? Thanks very much RegardsArticle: 143922
On Nov 3, 2:29=A0pm, "melinda" <melinda.m...@gmail.com> wrote: > Hi all, > > I am simulating a entity with Modelsim (v6.5c). Modelsim > only displays the input/output signals of the simulated top entity. > > When I run simulation Modelsim displays only changes of input/output > signals of the top entity verilog module i.e. testbench (in objects windo= w > i.e. in wave window), but nothing happening with signals declared in the > instantiated verilog modules. > (PS: In Cadence SimVision, I know that I was able to see changes of all > signals in testbench and also in instantiated verilog modules, in wave > window) > > Is there a way of viewing the internal signals declared in the instantiat= ed > verilog modules in Modelsim in wave window? > > Thanks very much > > Regards Hi Melinda I assume you're using ModelSim SE? By default, SE optimizes the design for maximum performance, which includes removing the capability to log internal nodes. This optimization is done by the vopt command, which you can call explicitly after compilation else is run implicitly when you start vsim (you'll see "** Note: (vsim-3812) Design is being optimized..." in the transcript). To enable the ability to log internal signals you must give vopt some additional parameters The following will enable access to all objects in the whole design Explicit vopt: vopt my_top +acc -o top_opt vsim top_opt Implicit vopt: vsim my_top -voptargs=3D"+acc" Obviously, this will slow the simulation down compared to the fully optimised design. You can control what is 'accessible' (object types / modules / instances etc) by adding more options to the vopt command (see the User Manual for details) if you want to balance debug vs. performance. Hope this helps - NigelArticle: 143923
On Mon, 2 Nov 2009 09:20:45 -0500 Sam Kerr <stkerr@purdue.edu> wrote: > [snip a ring oscillator] You know, for one pin, a tinylogic schmitt trigger, an R, and a C (sum total < $0.10 in quantity), you could have a much easier to work with clock source. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 143924
Thanks Nigel, I was try that, but I'm still not able to see any changes of signals in instantiated modules(in wave form window). When I put some signals from instantiated verilog modules to wave form window, after I hit "run" simulation those signals remain X. Do you have any idea why is that so? Best Regards --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com
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