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On Oct 14, 10:56=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > Weng Tianxiang <wtx...@gmail.com> wrote: > > < I am interested in reading the post on "ASIC Prototyping using FPGA" > < in which it mentioned that in ASIC, flip-flops are used to be replaced > < with latchs. > > < I cound't understand it. > > < For example, a state machine. If FFs are used, after the next clock > < pulse, FFs change status. If latches are used, I don't know how the > < latches can be kept unchanged while code outside the state machine is > < using the state information. > > < anyone would like to expain it more in details? > > I agree. =A0As far as I know, ASIC libraries use the same type > of edge triggered FF's as FPGAs. =A0Well, in the old days people > used to do strange things, like dynamic logic. =A0The 8080 and 8086 > have minimum clock rates, as the registers will lose their > contents if you clock too slow. =A0When the Z80 came out with > static logic people were much happier. =A0(You can slow the clock > down and watch instructions execute one at a time.) > > Also, with a two phase clock you can use simpler latches, but as > far as I know, that isn't the way current logic works. > > -- glen Hi glen, Thank you for your comments. I have a great relief, otherwise all of my knowledge of the digital circuit designs would be useless if latchs would overwhelm the FFs. In all my 10 digital circuit designs, I have never used a latch. The only legal and valuable use of a latch I have learned was from an asynchronous FIFO design by Peter and Conning. WengArticle: 143526
Weng Tianxiang <wtxwtx@gmail.com> wrote: (big snip) < Thank you for your comments. < I have a great relief, otherwise all of my knowledge of the digital < circuit designs would be useless if latchs would overwhelm the FFs. In < all my 10 digital circuit designs, I have never used a latch. < The only legal and valuable use of a latch I have learned was from an < asynchronous FIFO design by Peter and Conning. These days most of the time latch means the same thing as FF. For the other kind, the term transparent latch should be used. In the TTL days, you could put a transparent latch between a counter and a 7447 seven segment decoder. Then it works like the lap timer on a stopwatch where you can latch the count while the counter runs, or watch the counter output. I suppose I can also see it for a FIFO, especially if the FIFO is required to pass the input directly to the output when it is empty. -- glenArticle: 143527
>On Tue, 13 Oct 2009 14:10:34 -0500, "dc207" <jaap.mol@planet.nl> wrote: > > >>Anyhow, what we see is not a "normal" reflection, but a RC-curve on top of >>the reflection. This RC-curve is "killing", the reflection itself is more >>or less as expected. If we manually place a 100 ohm resistor on the board, >>and disable the on-die termination, the RC-curve has disappeared, and the >>signal looks as neat as you can possibly expect. > >... but do the data errors disappear? Yes, the data errors disappear like "snow in the sun" with the external (on-board) termination resistor.... > >I may have a suspicious mind but it looks possible that the visible reflections >are a red herring, and the internal termination works just fine ... but >something else is causing data corruption. Today, we managed to get the ADI TS201 EZ-lite DSP eval board connected to the Xilinx ML403 board running without data errors, using the LVDS-based DSP Link Port, two RJ45/UTP cable to interconnect the DSP to the FPGA, and a simple loopback implemented in the Virtex4 (FX) FPGA. This is a confirmation that we are doing something wrong, but we have (re)verified so many possible causes already, and are running out of options. Tomorrow we will be testing a completly stripped-down FPGA, e.g. only with loopbacks implemented on multiple DSP Link Ports and absolutelly nothing else. As if we were connecting 6 UTP loopback cables to each DSP Link Port... We will see what will we measure. Meanwhile, somebody is performing Power Integrity simulations (Hyperlynx PI) on our PCB design, but until now the tool crashes due to shortage of memory, e.g. the design seems too big even for high-end (memory-rich) PC platforms (?). Sending the design to Mentor requires a signed NDA, which will probably take weeks to complete (based on our experiences with several NDA contracts)... ;-( > >The best time to discover that is _not_ when you get the revised board layout >back... > >- Brian > > --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143528
On Oct 15, 9:35=A0am, "dc207" <jaap....@planet.nl> wrote: > >... but do the data errors disappear? > > Yes, the data errors disappear like "snow in the sun" with the external > (on-board) termination resistor.... > What is the time-constant of the RC effect, and final peak/DC amplitudes ? Can you reproduce that same waveform and ~error rates with a deliberately incorrect termination ?. With multiple channels, you could run some external, some internal term, and a couple of 'experimental' ones that you tune to degrade the error rate to around the failing ones. That gives a feel for just how far off it needs to be to spawn the errors. -jgArticle: 143529
http://www.aipst.com/AIPS7100.tar.gzArticle: 143530
On Oct 14, 12:47=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > > These days most of the time latch means the same thing as FF. > For the other kind, the term transparent latch should be used. > My theory is that latches are only used by two extreme classes of designers: Very savvy and experienced ones, when faced with tough timing and asynchronous issues. Or Very naive ones that do not fully appreciate the robust beauty of the edge-triggered flip-flop. The rest of the world happily uses flip-flops. Peter Alfke, speaking for himself.Article: 143531
On Oct 14, 8:25=A0pm, Peter Alfke <al...@sbcglobal.net> wrote: > On Oct 14, 12:47=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> > wrote: > > > > > These days most of the time latch means the same thing as FF. > > For the other kind, the term transparent latch should be used. > > My theory is that latches are only used by two extreme classes of > designers: > > Very savvy and experienced ones, when faced with tough timing and > asynchronous issues. > Or > Very naive ones that do not fully appreciate the robust beauty of the > edge-triggered flip-flop. > > The rest of the world happily uses flip-flops. > > Peter Alfke, speaking for himself. Hi Peter, !!! Excellent and sharp point !!! Have you seen the post "ASIC Prototyping using FPGA" ? Please give a comment over there. I had wondered that ASIC has another new type of logic to overwhelm use latches over flip-flops. WengArticle: 143532
On Oct 14, 11:35=A0am, rickman <gnu...@gmail.com> wrote:
> On Oct 13, 1:06=A0am, GrIsH <grishkun...@gmail.com> wrote:
>
>
>
>
>
> > =A0 =A0I tried lots of data types and the conversion function but didn'=
t
> > get the result what i want......
> > So iam going to put my problem straight forward to you.......your any
> > idea will be gr8ly appreciated....
>
> > Problem:
> > 1. i need to count the pulses from quadrature encoder , value of count
> > can be +ve as well as -ve depending upon direction of rotation of
> > encoder...
> > 2.This value is to be send to uBlaze....
> > 3.I have a code for counting the encoder pulses that is included in
> > the "user_logic"....
> > 4.I have used "user software register" method of transferring data
> > from my custom IP to uBlaze..
> > 5.In phase of transferring the value of count from IP to uBlaze, the
> > value of count must be mapped to IP2Bus_Data in SLV format data
> > type....
> > 6.Here i had defined "count " that counts value of pulses as integer
> > and it should be converted SLV while transferring...
> > 7.But this method didn't work as i expected while receiving data in
> > uBlaze.....
> > So...Plz suggest me in....
>
> > what should be the data type of "count" that support +ve as well -ve
> > numbers and supports operation count<=3Dcount+1/-1
> > ??
> > and how -ve values of count are represented in SLV format??
>
> I don't know that your problem is one of converting data types. =A0You
> clearly are placing the 16 bit data in an odd location on a 32 bit bus
> and you have not told me that you are certain that this is correct. =A0I
> have not worked with the uBlaze, so I'm not familiar with its data bus
> numbering. =A0Is it 0 to N or N downto 0?
>
> Have you simulated your design? =A0Before putting a design into the
> chip, you should always simulate it first to get your logic right.
> Then you can load it into the chip and see if it works with the real
> hardware.
>
> If you don't answer my questions and follow my advice, I can't help
> you.
iam trying to simulate my design and lets see what will be the
result...
>
> To answer your last question, the SLV signal type does not know
> anything about numbers. =A0It is just an array, or a bus, of std_logic
> signals. =A0There is no intended interpretation of this bus as a
> number. =A0That is why the signed and unsigned types were developed.
> They have an explicit representation of signed and unsigned numbers
> respectively. =A0When you talk about "converting" a signed value to an
> SLV, there really is no conversion. =A0It is more like just connecting
> the wires. =A0So the SLV ends up receiving the exact same set of 1s and
> 0s that were in the signed signal, according to the way that they
> connected.
>
> I have never worked with SLV in the 0 to N direction. =A0To be honest, I
> don't remember the details of how assignments are made between buses
> using different directions of indexes. =A0I wouldn't expect any
> surprises, but then I have no experience with them. =A0Is there a reason
> that you are using 0 to N numbering instead of N downto 0 on your SLV
> arrays? =A0This may not be a problem, but if you are stuck, why use this
> uncommon convention?
for IP2Bus_Data we are not allowed to make this convention of N
downto 0 that's why i didn't use this convention.
>
> But before changing anything you need to simulate your design. =A0That
> means you will need a testbench which can be automatically generated
> by many VHDL tools. =A0Then edit the resulting testbench file to add
> stimulus to your inputs and you will be able to observe any signal in
> the design in the waveform window. =A0That will let you see each and
> every change of data in the path from the counter to the uBlaze CPU.
>
> Rick
Article: 143533Peter Alfke <alfke@sbcglobal.net> wrote: <? On Oct 14, 12:47?pm, glen herrmannsfeldt wrote: <?> These days most of the time latch means the same thing as FF. <?> For the other kind, the term transparent latch should be used. <? My theory is that latches are only used by two extreme classes of <? designers: <? Very savvy and experienced ones, when faced with tough timing and <? asynchronous issues. <? Or <? Very naive ones that do not fully appreciate the robust beauty of the <? edge-triggered flip-flop. Yes that sounds about right. I have wondered what all tricks Intel used in the 8080 to do what it does with so few transistors, and then for the 8086. The 8086 is especially tricky with a two phase clock with 33% duty cycle (for full speed operation). I was once wondering why no FPGAs implement the Earle Latch: http://books.google.com/books?id=QR9px-K6qxkC&pg=PA25&lpg=PA25&dq=%22earle+latch%22&source=bl&ots=d522CUmFuO&sig=9Ktu3pygcAoKCRgdDj0B7103H8A&hl=en&ei=VKnWSu-LAo7sMcaqyNEI&sa=X&oi=book_result&ct=result&resnum=4&ved=0CBUQ6AEwAw#v=onepage&q=%22earle%20latch%22&f=false though that would likely only apply to the first category listed above. (Also, it adds the complication of distributing a two phase clock.) I believe it was designed by IBM for the 360/91. -- glenArticle: 143534
Hi NG,
I have got a partial Design with different CAN-Modules to be partial
reconfigured. Most of the time the reconfiguration works quit flawlessly.
Anyway sometimes (unpredictable) the FSMs in my design stop.
In more courious tests i found out, that some FSMs enter two states at the same
time:
(fsm_state = idle & fsm_state=error_frame) == true
Can anyone tell me if there is an initial fsm state after partial reconfiguration?
Any Xilinx-sources on this topic?
using: virtex-2
--
best regards
-- Fabian Schuh
Article: 143535On Oct 14, 5:56=A0pm, Symon <symon_bre...@hotmail.com> wrote: > jay wrote: > > > Peter, > > > The design mostly used latches, I'm unlucky. > > =A0> > Ouch! > > > > > All three clocks are registered by main clock however, I think if I > > can constraint the FF output to BUFG input delay of them (be the > > same), the phase relationship can be kept. Can I do that? > > > Best Regards, > > Jay > > I can think of two choices, both of which use a DCM to make 120MHz from > your 60MHz. > > 1) Rewrite it all to use FFs only (i.e. no latches) clocked at 120MHz. > > 2) Use the 120MHz to make the three clock signals the original design > used. Constrain these with MAXDELAY to three BUFGs to distribute the cloc= ks. > > Do (1) if you're ever gonna add any new features to the design. Do (2) > if you're planning on getting a job somewhere else soon! ;-) > > Good luck, Syms. The ASIC was designed so long ago that it was written by a proprietary HDL code, it will take lots man-months to rewrite it. It has a post-layout Verilog netlist with foundry library models for simulation, I have created all the libraries (gates, Latches, FFs, multipliers, memories) using Verilog RTL, so get a gate level synthesizable design. What I'm thinking now is to replace Latch instance with FF instance in the design like below: latch_cell latch_inst1 (.o(o), .i(i), .en(en)) to ff_cell ff_inst1 (.o (o), .i(i), .en(en), .clk(clk)) So it may fit into a FPGA better, I just need get a high speed clock (120MHz) to every modules, and write a script to convert all latch instances through the design. My concern is 120MHz is fast enough for a low cost FPGA that I will get lots of setup time problems then...Article: 143536
jay <heavenfish@gmail.com> wrote: <> jay wrote: <> > The design mostly used latches, I'm unlucky. (big snip) < The ASIC was designed so long ago that it was written by a proprietary < HDL code, it will take lots man-months to rewrite it. < It has a post-layout Verilog netlist with foundry library models for < simulation, I have created all the libraries (gates, Latches, FFs, < multipliers, memories) using Verilog RTL, so get a gate level < synthesizable design. Yes, that is what I would expect. < What I'm thinking now is to replace Latch instance with FF < instance in the design like below: < latch_cell latch_inst1 (.o(o), .i(i), .en(en)) to ff_cell ff_inst1 (.o < (o), .i(i), .en(en), .clk(clk)) It would depend somewhat on the design, but my first thought is that you just use (en) as the clock. (or ~en depending on rising edge or falling edge.) Does the design have a two phase clock? Does the signal flow go: (latch on phase 1) (gates) (latch on phase 2) (gates) (repeat as needed) In that case, you should be able to replace them all by edge triggered FFs and run the clock twice as fast. How old is this design? < So it may fit into a FPGA better, I just need get a high speed clock < (120MHz) to every modules, and write a script to convert all latch < instances through the design. < My concern is 120MHz is fast enough for a low cost FPGA that I will < get lots of setup time problems then... -- glenArticle: 143537
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On October 12th, 2009, Antti Lukats posted to the newsgroup news:comp.arch.=
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|> | =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
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=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ||
|> |ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATI=
X are Reg. U.S. Pat. & =A0||
|> |Tm. Off. and Altera marks in and outside the U.S. =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0||
|> | =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ||
|> |[?V7AFDXBHCW=3DssID:526469735]" =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0||
|> |-----------------------------------------------------------------------=
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|> =
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|> Dear Sir/Madam, =
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|> =
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|> After following a number of hyperlinks, I was eventually informed on =
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|> WWW.Altera.com/b/twitter-facebook-giveaway-rules.html =
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|> :"[..] =
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|> =
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|> 1. Eligibility: Only legal persons, (i) who are physically located and =
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|> residing in the Continental U.S. or otherwise eligible under =
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|> applicable local laws, [..] =
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|> =
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|> [..]" =
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|> =
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|> I have never been in the Continental U.S.: so am I eligible to win one =
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|> of those kits or did you waste my time? =
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|> =
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|> Yours faithfully, =
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|> Colin Paul Gloster =
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| =
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|waste of time =
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|most such things are for US residents only =
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| =
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|Antti" =
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|--------------------------------------------------------------------------=
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So far I have received no response to the email which I sent to
announcements@Altera.com on October 12th, 2009. I am not pleased.
Colin Paul Gloster
--8323328-1185005735-1255607680=:21518--
Article: 143538On Oct 15, 12:51=A0am, GrIsH <grishkun...@gmail.com> wrote: > On Oct 14, 11:35=A0am, rickman <gnu...@gmail.com> wrote: > > > I have never worked with SLV in the 0 to N direction. =A0To be honest, = I > > don't remember the details of how assignments are made between buses > > using different directions of indexes. =A0I wouldn't expect any > > surprises, but then I have no experience with them. =A0Is there a reaso= n > > that you are using 0 to N numbering instead of N downto 0 on your SLV > > arrays? =A0This may not be a problem, but if you are stuck, why use thi= s > > uncommon convention? > > =A0 =A0 for IP2Bus_Data we are not allowed to make this convention of N > downto 0 that's why i didn't use this convention. Ok, it shouldn't matter really, as long as you use it correctly. Can you explain what this bus is and why it is 0 to 31? Is this a port on the uBlaze? Where exactly does this restriction come from. Why do you assign your counter result to bits 16 to 31? I don't know how the uBlaze reads memory, it's possible that it can read the low 16 bits of the bus as a 16 bit quantity... *if you are using the right instruction* to to read a 16 bit quantity, not 16 bits of a 32 bit quantity. If you are coding in C, you are relying on the compiler to generate the correct code. The easy way to fix this problem in hardware is to assign the upper 16 bits of the bus the value of the sign bit of your result instead of always using zeros. Of course, all of this assumes that bit 31 is the lsb. Do you know that for sure? How do you connect the IP2Bus_Data to the uBlaze data bus? That is what really matters. RickArticle: 143539
On Oct 15, 7:57=A0am, Colin Paul Gloster <Colin_Paul_Glos...@ACM.org> wrote: > > So far I have received no response to the email which I sent to > announceme...@Altera.com on October 12th, 2009. I am not pleased. > > Colin Paul Gloster Did you give them your email address? Is this spam or you just don't like the fact that it is much harder for them to meet the regulations of dozens of countries than it is to only make the offer in the single country where most of their business comes from? I don't like 95% of the advertising email I get. But I've asked for 99% of it and if I don't like it, I just unsubscribe from it. The stuff I get where they got my email address from a spam list encourages me to send an email asking them to get in touch with me. Then I ask them how they got my address and let them know I'm not happy with being spammed. But if you are just complaining that you don't like the way they've set up their offer, why waste your time with that thought... like why am I wasting my time with *this* thought? RickArticle: 143540
Fabian, Does your partial bitstream include the FSM registers? If it does, it will also contain initial conditions for these DFF. There is also the question of reconfiguring while the design is running: if there is a block RAM in your design (BRAM), it only has two ports that may be used simultaneously -- the configuration interface can not be used while the BRAM is being clocked (it will lead to data corruption in the BRAM). The same may be true of the logic, in that the DFF used for the FSM can not be clocked while you are reconfiguring if they get inputs from the reconfigurable section, or are inside the reconfigurable section.Article: 143541
On Oct 13, 8:12=A0am, "colin_toog...@yahoo.com" <colin_toog...@yahoo.com> wrote: > On 13 Oct, 11:52, Martin Thompson <martin.j.thomp...@trw.com> wrote: > > > > > colin <colin_toog...@yahoo.com> writes: > > > I'm trying to implement a simple CLI so that I can do some debugging. > > > I have a microblaze license but I've just taken a look at it and > > > sledgehammers and nuts come to mind. I then took a look on opencores > > > and nothing seems quite finished enough (and few with a C compiler). > > > > Does anyone have a suggestion? > > > Picoblaze (but that's assembly only..) > > > If you can fit a sledgehammer (sorry, microblaze :) in, why not use it? > > What is it you're trying to do - just wiggle some port pins, or > > something more complex? > > > If it's slow pin/signal wiggling, and alternative might be to use > > Chipscope's VIO block - it's not CLI, but I gather it has some tcl > > libraries which you could build something with... > > > Cheers, > > Martin > > > -- > > martin.j.thomp...@trw.com > > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp:/= /www.conekt.net/electronics.html > > Martin > > Your right, using the VIO block answers the question I posted. I need > to read/write a dozen 32 bit registers. However I ultimately want a > processor at the outermost control loop. I will take a look at using > chipscope for debugging and the Picoblaze at the outer loop. Cludgy in > the short term but ultimately quite elegant. > > Colin I have some reservations about it, but I would say you might want to look at the ZPU. I am not a software person anymore, so I think very differently than those guys, but they seem to have caught on and recently I read that National Semi has released some sort of eval board that is using the ZPU in an FPGA. It is supported by a C compiler and can get down to something well under 1000 LUTs, perhaps as low as 600 I think. It's not so fast at that size, but should be plenty fast enough for a CLI (I had to google CLI to figure out what that meant). Another option is one of the two processors from Lattice. I have never read the license in enough detail to actually understand it (I am not a lawyer, thank god) but it is supposed to be open source. I don't know if that is the same as freely usable, but I'm pretty sure you don't have to use it in their parts. They have a Micro8 similar to the Picoblaze and a 32 bit CPU like the uBlaze. If you are interested in using Forth (it comes with the CLI) there are a number of processors to choose from including my own. But I have never completed the compiler so it is assembly only. Even if that is very forth like, it is not a forth compiler. RickArticle: 143542
On Oct 13, 3:11=A0pm, Gael Paul <gael.p...@gmail.com> wrote: > Test01, > > The initial mapping to an FPGA prototyping board is indeed a big > undertaking. However, if you use the dedicated tools described in the > previous post, then updating the prototype when the HDL changes will > be push-button in the vast majority of cases. Changes that would > require some assistance are of the kind that invalidate the partition: > =A0- changes to the interface between two modules that are in different > devices. This would require to incrementally update the partition and > pin assignment (Certify supports this, not sure about Auspy) > =A0- significant increase in resources leading to an overflow of one or > more devices. This would require an incremental update to the > partition to reassign logic in devices with some free room > =A0- etc > > Emulation systems are in fact using commercial FPGAs. Thus, the > conversion effort is virtually identical. However, the partitioning > and board management tasks are fully automated and hidden from the > user. > > The choice between emulation and prototyping should primary be based > on your objectives: > =A0- to perform early-stage functional debug, emulation is the better > choice. To some extent, emulation is HDL simulation on steroids. > =A0- to validate the chip in a (near) real-life environment, find the > late-stage functional bugs, develop and validate the embedded > software, pass certification, etc, prototyping is the better choice. > In fact, power users combine emulation and prototyping to validate > their SoCs. > > Cheers, > > =A0- gael > > PS: a few additional notes on latches: > (1) wether using emulation of prototyping, there is no need to convert > latches to flip-flops as latches are supported in most FPGAs. However, > you cannot fully rely on timing analysis since it does not support > time-borrowing. This introduces the possibility of timing violations > on your emulator/prototype that would appear as functional bugs. If > you run the emulator/prototype at very low frequencies (e.g. < 1Mhz, > like emulators do), then this most likely not a problem. Otherwise, a > good option for power users would be to run PrimeTime (or any ASIC STA > that supports time-borrowing) on the protoype netlist annotated with > delays (SDF). > (2) wether using emulation or prototyping, you can opt for fully > automatic conversion of latches to flip-flops (Precision and Synplify/ > Certify have this feature). While this resolves the above timing > analysis problem, it may create a design that is not functionally > equivalent. However, in my experience, if latches are used properly, > FF conversion will always be functionally equivalent. In other words, > if your ASIC design team is experienced and knows its trade, latches > should not be an issue and converting them to FFs is best option. Have you all heard of vavlog? It seems that some people initially use this software to screen the RTL code. based on the feedback from vavlog, code changes are made to the design (verilog files) to be able to do vaelab synthesis. I am not sure if the output of vavlog can be fed to Synopsys certify.Article: 143543
On Oct 14, 11:40=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote: > I had wondered that ASIC has another new type of logic to overwhelm > use latches over flip-flops. > I believe the motivation for the general liking of latches rather than flip flops in the ASIC world is power consumption. That clock net consumes a sizable chunk of power whether that flip flop actually changes state or not. Just because FPGAs have to cobble together logic to create a latch (and cause potential timing issues in doing so) and that they are not appropriate storage elements in all cases are only reasons why use of latches in FPGAs and CPLDs is usually not a good path to head down. Not all designs live in that world with those constraints. ASIC worlds have a different set of constraints to live within. Don't assume that the ASIC folks don't use the appropriate storage element, just accept that they may not be constrained from using ones that would not work well in a different environment such as an FPGA. KJArticle: 143544
All, A good paper was presented In Monterey FPGA conference 2009 from Intel, on their use of a Xilinx Virtex 5 LX330 to test their Atom processor before layout. One of the things they talk about is how their ASIC standard cell/ custom flow uses Latches for speed and power improvements (over the use of edge triggered flip flops). If you want to learn about why someone would use latches in an ASIC, I suggest reading this paper. I also suggest reading this paper if you have to test your ASIC design before you tapeout, as it talks about converting the latches back to edge-triggered flip flops, and all the other "gothcahs" that people commonly face. All in all, the 70 million transistor Atom core, less cache memories (left with 14 million transistors) fit in the LX330, and operated fast enough to boot operating systems, browse web pages, etc. http://www.ece.wisc.edu/~kati/fpga2009/index.html (Hi Peter! Hows the vines growing?) AustinArticle: 143545
On Oct 15, 8:14=A0am, rickman <gnu...@gmail.com> wrote: > On Oct 15, 12:51=A0am, GrIsH <grishkun...@gmail.com> wrote: > > > On Oct 14, 11:35=A0am, rickman <gnu...@gmail.com> wrote: > > > > I have never worked with SLV in the 0 to N direction. =A0To be honest= , I > > > don't remember the details of how assignments are made between buses > > > using different directions of indexes. =A0I wouldn't expect any > > > surprises, but then I have no experience with them. =A0Is there a rea= son > > > that you are using 0 to N numbering instead of N downto 0 on your SLV > > > arrays? =A0This may not be a problem, but if you are stuck, why use t= his > > > uncommon convention? > > > =A0 =A0 for IP2Bus_Data we are not allowed to make this convention of N > > downto 0 that's why i didn't use this convention. > > Ok, it shouldn't matter really, as long as you use it correctly. =A0Can > you explain what this bus is and why it is 0 to 31? =A0Is this a port on > the uBlaze? =A0Where exactly does this restriction come from. =A0Why do > you assign your counter result to bits 16 to 31? MicroBlaze is big endian. Bits 16 to 31 are the two least significant bytes in a 32-bit word (bit 31 is the right-most bit). -aArticle: 143546
On Oct 14, 9:51=A0pm, GrIsH <grishkun...@gmail.com> wrote: > On Oct 14, 11:35=A0am, rickman <gnu...@gmail.com> wrote: > > I have never worked with SLV in the 0 to N direction. =A0To be honest, = I > > don't remember the details of how assignments are made between buses > > using different directions of indexes. =A0I wouldn't expect any > > surprises, but then I have no experience with them. =A0Is there a reaso= n > > that you are using 0 to N numbering instead of N downto 0 on your SLV > > arrays? =A0This may not be a problem, but if you are stuck, why use thi= s > > uncommon convention? > > =A0 =A0 for IP2Bus_Data we are not allowed to make this convention of N > downto 0 that's why i didn't use this convention. You can freely assign little-endian (foo downto bar) vectors to big- endian vectors (bar to foo). You just have to remember that the bit lanes are always in the same order: foo(16 downto 0) <=3D bar(0 to 16); will put the least-significant bit (right-most bit) in bar (bit 16) into foo(0), and so forth. The only time you will have issues is when you use a loop to iterate over all bits in a vector and you don't pay attention to this (you don't want to assign bar(0) to foo(0), unless that's what you want to do!). -aArticle: 143547
On Oct 15, 10:02=A0am, austin <aus...@xilinx.com> wrote: > All, > > A good paper was presented In Monterey FPGA conference 2009 from > Intel, on their use of a Xilinx Virtex 5 LX330 to test their Atom > processor before layout. > > One of the things they talk about is how their ASIC standard cell/ > custom flow uses Latches for speed and power improvements (over the > use of edge triggered flip flops). > > If you want to learn about why someone would use latches in an ASIC, I > suggest reading this paper. > > I also suggest reading this paper if you have to test your ASIC design > before you tapeout, as it talks about converting the latches back to > edge-triggered flip flops, and all the other "gothcahs" that people > commonly face. > > All in all, the 70 million transistor Atom core, less cache memories > (left with 14 million transistors) fit in the LX330, and operated fast > enough to boot operating systems, browse web pages, etc. > > http://www.ece.wisc.edu/~kati/fpga2009/index.html > > (Hi Peter! =A0Hows the vines growing?) > > Austin Hi Austin, Where is the paper? or its title, or authors? What you mentioned is what I am interested in. WengArticle: 143548
ACM portal, 2009 proceedings There is a fee for this paper (not free). Knowledge sometimes requires money, AustinArticle: 143549
On Oct 15, 11:34=A0am, austin <aus...@xilinx.com> wrote: > ACM portal, > > 2009 proceedings > > There is a fee for this paper (not free). > > Knowledge sometimes requires money, > > Austin Hi Austin, I cannot find the paper by keyword "FPGA 2009" unless one must have its title or its authors, no matter it is a ACM portal or any database interface. Weng
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